mirror of
https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
synced 2025-12-14 18:38:55 +00:00
466 lines
13 KiB
ArmAsm
466 lines
13 KiB
ArmAsm
/*
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* Copyright (c) 2022, Artinchip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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******************************************************************************
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d13x Memory Layout
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******************************************************************************
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配置(1) 配置(2) 配置(3)
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SRAM_S1 OFF SRAM_S1 OFF SRAM_S1 ON
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TCM ON TCM OFF
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0x30040000+----------+ +----------+ +----------+
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| ITCM | | | | |
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| 128K | | | | TCM |
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0x30060000+----------+ | | | + |
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| DTCM | | | | SRAM_S0 |
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| 128k | | SRAM_S0 | | |
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0x30080000+----------+ | 1M | |1M-sram_s1|
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| | | | | size |
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| SRAM_S0 | | | +----------+
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| 768K | | |
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0x3013FFFF+----------+ +----------+
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0x40000000 ------------------------> +----------+
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- sram_s1 size | SRAM_S1 |
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| |
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|128K/256K/|
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|384K/512K/|
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|640K/768K |
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0x3FFFFFFF ------------------------> +----------+
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0x40000000+----------+
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| PSRAM |
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| 4M/8M |
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+----------+
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| FPGA Ext |
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| PSRAM |
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| 64M-psram|
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| size |
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0x43FFFFFF+----------+
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*/
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#include "rtconfig.h"
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#ifdef CONFIG_ENABLE_ROM_API
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INCLUDE rom_api.lds
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#endif
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#ifndef AIC_BOOTLOADER_RESERVE_SIZE
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#define AIC_BOOTLOADER_RESERVE_SIZE 0x40000
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#endif
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#if (AIC_BOOTLOADER_RESERVE_SIZE > AIC_SRAM_S1_SIZE)
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#define AIC_SRAM_RESERVE_SIZE AIC_BOOTLOADER_RESERVE_SIZE
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#else
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#define AIC_SRAM_RESERVE_SIZE AIC_SRAM_S1_SIZE
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#endif
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MEMORY
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{
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BROM : ORIGIN = 0x30000000 , LENGTH = 256K
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#ifdef AIC_TCM_EN
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ITCM : ORIGIN = 0x30040000 , LENGTH = AIC_ITCM_SIZE
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DTCM : ORIGIN = 0x30040000 + AIC_ITCM_SIZE , LENGTH = AIC_DTCM_SIZE
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SRAM_S0 : ORIGIN = 0x30040000 + AIC_ITCM_SIZE + AIC_DTCM_SIZE , LENGTH = AIC_SRAM_TOTAL_SIZE - AIC_SRAM_RESERVE_SIZE - AIC_ITCM_SIZE - AIC_DTCM_SIZE
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#else
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SRAM_S0 : ORIGIN = 0x30040000 , LENGTH = AIC_SRAM_TOTAL_SIZE - AIC_SRAM_RESERVE_SIZE
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#endif
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SRAM_S1_SW : ORIGIN = 0x40000000 - AIC_SRAM_S1_SIZE , LENGTH = AIC_SRAM1_SW_SIZE
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SRAM_S1_CMA : ORIGIN = 0x40000000 - AIC_SRAM_S1_SIZE + AIC_SRAM1_SW_SIZE , LENGTH = AIC_SRAM_S1_SIZE - AIC_SRAM1_SW_SIZE
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PSRAM_SW : ORIGIN = 0x40000000 , LENGTH = AIC_PSRAM_SW_SIZE
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PSRAM_CMA : ORIGIN = 0x40000000 + AIC_PSRAM_SW_SIZE , LENGTH = AIC_PSRAM_SIZE - AIC_PSRAM_SW_SIZE
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#ifdef FPGA_BOARD_ARTINCHIP
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PSRAM_ext : ORIGIN = 0x40000000 + AIC_PSRAM_SIZE , LENGTH = 64M - AIC_PSRAM_SIZE
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#endif
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#ifdef AIC_XIP
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FLASH_XIP : ORIGIN = 0x60000000 + AIC_XIP_FW_OFFSET , LENGTH = 512M - AIC_XIP_FW_OFFSET
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#endif
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}
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#ifdef AIC_TCM_EN
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PROVIDE (__itcm_start = 0x30040000);
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PROVIDE (__itcm_end = __itcm_start + AIC_ITCM_SIZE);
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PROVIDE (__dtcm_start = __itcm_end);
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PROVIDE (__dtcm_end = __itcm_end + AIC_DTCM_SIZE);
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PROVIDE (__sram_s0_start = __dtcm_end);
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PROVIDE (__sram_s0_end = __dtcm_end + AIC_SRAM_TOTAL_SIZE - AIC_SRAM_S1_SIZE - AIC_ITCM_SIZE - AIC_DTCM_SIZE);
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#else
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PROVIDE (__sram_s0_start = 0x30040000);
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PROVIDE (__sram_s0_end = __sram_s0_start + AIC_SRAM_TOTAL_SIZE - AIC_SRAM_S1_SIZE);
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#endif
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PROVIDE (__sram_s1_sw_start = 0x40000000 - AIC_SRAM_S1_SIZE);
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PROVIDE (__sram_s1_sw_end = 0x40000000 - AIC_SRAM_S1_SIZE + AIC_SRAM1_SW_SIZE);
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PROVIDE (__sram_s1_cma_start = __sram_s1_sw_end);
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PROVIDE (__sram_s1_cma_end = 0x40000000);
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PROVIDE (__psram_sw_start = 0x40000000);
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PROVIDE (__psram_sw_end = 0x40000000 + AIC_PSRAM_SW_SIZE);
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PROVIDE (__psram_cma_start = __psram_sw_end);
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PROVIDE (__psram_cma_end = 0x40000000 + AIC_PSRAM_SIZE);
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PROVIDE (__psram_start = 0x40000000);
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PROVIDE (__psram_end = 0x40000000 + AIC_PSRAM_SIZE);
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PROVIDE (__dtb_pos_f = __psram_end - 0x40000);
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#ifdef AIC_TCM_EN
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PROVIDE (__itcm_heap_end = __itcm_end);
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PROVIDE (__dtcm_heap_end = __dtcm_end);
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#endif
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PROVIDE (__sram_s0_sw_heap_end = __sram_s0_end);
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PROVIDE (__sram_s1_cma_heap_end = __sram_s1_cma_end);
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PROVIDE (__sram_s1_sw_heap_end = __sram_s1_sw_end);
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PROVIDE (__psram_cma_heap_end = __psram_cma_end);
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PROVIDE (__psram_sw_heap_end = __psram_sw_end);
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PROVIDE (__min_heap_size = 0x200);
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PROVIDE (__sram_sw_heap_start = __sram_s0_sw_heap_start);
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PROVIDE (__sram_sw_heap_end = __sram_s0_sw_heap_end);
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PROVIDE (__heap_start = __sram_s0_sw_heap_start);
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PROVIDE (__heap_end = __sram_s0_sw_heap_end);
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#ifdef AIC_PSRAM_CMA_EN
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PROVIDE (__cma_heap_start = __psram_cma_heap_start);
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PROVIDE (__cma_heap_end = __psram_cma_heap_end);
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#else
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PROVIDE (__cma_heap_start = __sram_s1_cma_heap_start);
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PROVIDE (__cma_heap_end = __sram_s1_cma_heap_end);
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#endif
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#ifdef AIC_TCM_EN
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REGION_ALIAS("REGION_ITCM" , ITCM);
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REGION_ALIAS("REGION_DTCM" , DTCM);
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#endif
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REGION_ALIAS("REGION_SRAM_S0_SW" , SRAM_S0);
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REGION_ALIAS("REGION_SRAM_S1_CMA" , SRAM_S1_CMA);
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REGION_ALIAS("REGION_SRAM_S1_SW" , SRAM_S1_SW);
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REGION_ALIAS("REGION_PSRAM_CMA" , PSRAM_CMA);
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REGION_ALIAS("REGION_PSRAM_SW" , PSRAM_SW);
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#ifdef AIC_SEC_TEXT_SRAM_S0
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REGION_ALIAS("REGION_TEXT" , SRAM_S0);
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#elif defined AIC_SEC_TEXT_SRAM_S1
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REGION_ALIAS("REGION_TEXT" , SRAM_S1_CMA);
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#elif defined AIC_SEC_TEXT_PSRAM
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REGION_ALIAS("REGION_TEXT" , PSRAM_CMA);
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#elif defined AIC_SEC_TEXT_XIP
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REGION_ALIAS("REGION_TEXT" , FLASH_XIP);
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#else
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REGION_ALIAS("REGION_TEXT" , SRAM_S0);
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#endif
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#ifdef AIC_SEC_RODATA_SRAM_S0
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REGION_ALIAS("REGION_RODATA" , SRAM_S0);
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#elif defined AIC_SEC_RODATA_SRAM_S1
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REGION_ALIAS("REGION_RODATA" , SRAM_S1_CMA);
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#elif defined AIC_SEC_RODATA_PSRAM
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REGION_ALIAS("REGION_RODATA" , PSRAM_CMA);
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#elif defined AIC_SEC_RODATA_XIP
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REGION_ALIAS("REGION_RODATA" , FLASH_XIP);
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#else
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REGION_ALIAS("REGION_RODATA" , SRAM_S0);
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#endif
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#ifdef AIC_SEC_DATA_SRAM_S0
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REGION_ALIAS("REGION_DATA" , SRAM_S0);
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#elif defined AIC_SEC_DATA_SRAM_S1
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REGION_ALIAS("REGION_DATA" , SRAM_S1_CMA);
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#elif defined AIC_SEC_DATA_PSRAM
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REGION_ALIAS("REGION_DATA" , PSRAM_CMA);
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#else
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REGION_ALIAS("REGION_DATA" , SRAM_S0);
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#endif
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#ifdef AIC_SEC_BSS_SRAM_S0
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REGION_ALIAS("REGION_BSS" , SRAM_S0);
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#elif defined AIC_SEC_BSS_SRAM_S1
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REGION_ALIAS("REGION_BSS" , SRAM_S1_CMA);
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#elif defined AIC_SEC_BSS_PSRAM
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REGION_ALIAS("REGION_BSS" , PSRAM_CMA);
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#else
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REGION_ALIAS("REGION_BSS" , PSRAM_CMA);
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#endif
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#ifdef FPGA_BOARD_ARTINCHIP
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PROVIDE (__psram_ext_start = __psram_end);
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PROVIDE (__psram_ext_end = 0x44000000);
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PROVIDE (__temp_ext_heap_end = __psram_ext_end);
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REGION_ALIAS("REGION_FPGA_EXT" , PSRAM_ext);
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#endif
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ENTRY(Reset_Handler)
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SECTIONS
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{
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#ifdef AIC_TCM_EN
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.itcm : {
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. = ALIGN(0x4) ;
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__itcm_code_start = .;
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*(.tcm_code)
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. = ALIGN(0x4) ;
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__itcm_code_end = .;
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__itcm_heap_start = .;
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} > REGION_ITCM AT > REGION_ITCM
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.dtcm : {
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. = ALIGN(0x4) ;
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__dtcm_data_start = .;
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*(.tcm_data)
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. = ALIGN(0x4) ;
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__dtcm_data_end = .;
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__dtcm_heap_start = .;
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} > REGION_DTCM
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#endif
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.text : AT(ADDR(.text)){
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. = ALIGN(0x4) ;
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__stext = . ;
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KEEP(*startup_gcc.o(*.text*))
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*(.text)
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*(.text*)
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*(.text.*)
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*(.gnu.warning)
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*(.stub)
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*(.gnu.linkonce.t*)
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*(.glue_7t)
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*(.glue_7)
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*(.jcr)
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*(.init)
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*(.fini)
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. = ALIGN (4) ;
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PROVIDE(__ctbp = .);
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*(.call_table_data)
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*(.call_table_text)
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/* section information for tiny console shell */
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. = ALIGN(4) ;
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__console_init_start = .;
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KEEP(*(.tinyspl.console.cmd))
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. = ALIGN(4) ;
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__console_init_end = .;
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/* section information for finsh shell */
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. = ALIGN(4);
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__fsymtab_start = .;
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KEEP(*(FSymTab))
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__fsymtab_end = .;
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. = ALIGN(4);
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__vsymtab_start = .;
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KEEP(*(VSymTab))
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__vsymtab_end = .;
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. = ALIGN(4);
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/* section information for initial. */
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. = ALIGN(4);
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__rt_init_start = .;
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KEEP(*(SORT(.rti_fn*)))
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__rt_init_end = .;
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. = ALIGN(4);
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. = ALIGN(0x10) ;
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#ifdef RT_USING_MODULE
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/* section information for modules */
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. = ALIGN(4);
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__rtmsymtab_start = .;
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KEEP(*(RTMSymTab))
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__rtmsymtab_end = .;
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#endif
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__etext = . ;
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} > REGION_TEXT
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.eh_frame_hdr : {
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*(.eh_frame_hdr)
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} > REGION_TEXT
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.eh_frame : ONLY_IF_RO {
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KEEP (*(.eh_frame))
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} > REGION_TEXT
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.gcc_except_table : ONLY_IF_RO {
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*(.gcc_except_table .gcc_except_table.*)
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} > REGION_TEXT
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.rodata :{
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. = ALIGN(0x4) ;
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__srodata = .;
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*(.rdata)
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*(.rdata*)
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*(.rdata1)
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*(.rdata.*)
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*(.rodata)
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*(.rodata1)
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*(.rodata*)
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*(.rodata.*)
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*(.srodata*)
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*(.rodata.str1.4)
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. = ALIGN(0x4) ;
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PROVIDE(__ctors_start__ = .);
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KEEP (*(SORT(.init_array.*)))
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KEEP (*(.init_array))
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PROVIDE(__ctors_end__ = .);
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PROVIDE(__dtors_start__ = .);
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KEEP(*(SORT(.dtors.*)))
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KEEP(*(.dtors))
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PROVIDE(__dtors_end__ = .);
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/* usb host class */
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. = ALIGN(0x8) ;
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__usbh_class_info_start__ = .;
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KEEP(*(.usbh_class_info))
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__usbh_class_info_end__ = .;
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#ifdef AIC_XIP
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. = ALIGN(0x40) ;
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#else
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. = ALIGN(0x4) ;
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#endif
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__erodata = .;
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__rodata_end__ = .;
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} > REGION_RODATA
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#ifdef AIC_XIP
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.ram.code : {
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. = ALIGN(0x8) ;
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__ram_code_start__ = .;
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__sdata = . ;
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__data_start__ = . ;
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*(.ram.code*)
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__ram_code_end__ = .;
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. = ALIGN(0x8) ;
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} > REGION_DATA AT > REGION_DATA
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.data : {
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. = ALIGN(0x4) ;
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#else
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.data : {
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. = ALIGN(0x4) ;
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__data_start__ = . ;
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__sdata = . ;
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#endif
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data_start = . ;
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KEEP(*startup_gcc.o(*.vectors*))
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*(.got.plt)
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*(.got)
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*(.gnu.linkonce.r*)
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*(.data)
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*(.data*)
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*(.data1)
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*(.data.*)
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*(.gnu.linkonce.d*)
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*(.data1)
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*(.gcc_except_table)
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*(.gcc_except_table*)
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__start_init_call = .;
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*(.initcall.init)
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__stop_init_call = .;
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__start_cmd = .;
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*(.bootloaddata.cmd)
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. = ALIGN(4) ;
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__stop_cmd = .;
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__global_pointer$ = .;
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*(.sdata)
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*(.sdata.*)
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*(.gnu.linkonce.s.*)
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*(__libc_atexit)
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*(__libc_subinit)
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*(__libc_subfreeres)
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*(.note.ABI-tag)
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__edata = .;
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__data_end__ = .;
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. = ALIGN(0x4) ;
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} > REGION_DATA AT > REGION_RODATA
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.eh_frame : ONLY_IF_RW {
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KEEP (*(.eh_frame))
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} > REGION_DATA AT > REGION_RODATA
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.gcc_except_table : ONLY_IF_RW {
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*(.gcc_except_table .gcc_except_table.*)
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__data_end__ = .;
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} > REGION_DATA AT > REGION_RODATA
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.bss : {
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. = ALIGN(0x4) ;
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__sbss = ALIGN(0x4) ;
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__bss_start__ = . ;
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*(.dynsbss)
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*(.sbss)
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*(.sbss.*)
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*(.scommon)
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*(.dynbss)
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*(.bss)
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*(.bss.*)
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*(COMMON)
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. = ALIGN(0x4) ;
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__ebss = . ;
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__end = . ;
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end = . ;
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__bss_end__ = .;
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} > REGION_BSS
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._sram_s0_sw_heap : {
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. = ALIGN(0x4) ;
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__sram_s0_sw_heap_start = .;
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. += __min_heap_size;
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. = ALIGN(0x4) ;
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} > REGION_SRAM_S0_SW AT > REGION_SRAM_S0_SW
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.sram_s1_sw : {
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. = ALIGN(0x4) ;
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__sram_s1_sw_data_start = .;
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*(.sram1_sw_data)
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. = ALIGN(0x4) ;
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__sram_s1_sw_data_end = .;
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__sram_s1_sw_heap_start = .;
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} > REGION_SRAM_S1_SW AT > REGION_SRAM_S1_SW
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.sram_s1_cma : {
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. = ALIGN(0x4) ;
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__sram_s1_cma_data_start = .;
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*(.sram1_cma_data)
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. = ALIGN(0x4) ;
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__sram_s1_cma_data_end = .;
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__sram_s1_cma_heap_start = .;
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} > REGION_SRAM_S1_CMA AT > REGION_SRAM_S1_CMA
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.psram_sw : {
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. = ALIGN(0x4) ;
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__psram_sw_data_start = .;
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*(.psram_sw_data)
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. = ALIGN(0x4) ;
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__psram_sw_data_end = .;
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__psram_sw_heap_start = .;
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} > REGION_PSRAM_SW AT > REGION_PSRAM_SW
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.psram_cma : {
|
|
. = ALIGN(0x4) ;
|
|
__psram_cma_data_start = .;
|
|
*(.psram_cma_data)
|
|
. = ALIGN(0x4) ;
|
|
__psram_cma_data_end = .;
|
|
__psram_cma_heap_start = .;
|
|
} > REGION_PSRAM_CMA AT > REGION_PSRAM_CMA
|
|
|
|
#ifdef FPGA_BOARD_ARTINCHIP
|
|
.fpga_ext : {
|
|
. = ALIGN(0x4) ;
|
|
__fpga_ext_data_start = .;
|
|
*(.fpga_ext_data)
|
|
. = ALIGN(0x4) ;
|
|
__fpga_ext_data_end = .;
|
|
__fpga_ext_heap_start = .;
|
|
} > REGION_FPGA_EXT AT > REGION_FPGA_EXT
|
|
#endif
|
|
}
|