mirror of
https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
synced 2025-12-14 10:28:54 +00:00
290 lines
14 KiB
C
290 lines
14 KiB
C
/*
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* Copyright (c) 2022, Artinchip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _AIC_SOC_H_
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#define _AIC_SOC_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef IHS_VALUE
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#define IHS_VALUE (20000000)
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#endif
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#ifndef EHS_VALUE
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#define EHS_VALUE (20000000)
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#endif
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/* frequence */
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#define CLOCK_120M 120000000
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#define CLOCK_100M 100000000
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#define CLOCK_72M 72000000
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#define CLOCK_60M 60000000
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#define CLOCK_50M 50000000
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#define CLOCK_36M 36000000
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#define CLOCK_30M 30000000
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#define CLOCK_AUDIO 24576000
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#define CLOCK_24M 24000000
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#define CLOCK_12M 12000000
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#define CLOCK_4M 4000000
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#define CLOCK_1M 1000000
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#define CLOCK_32K 32768
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#ifndef __ASSEMBLY__
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/* ------------------------- Interrupt Number Definition ------------------------ */
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typedef enum {
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Supervisor_Software_IRQn = 1U,
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Machine_Software_IRQn = 3U,
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Supervisor_Timer_IRQn = 5U,
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CORET_IRQn = 7U,
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Supervisor_External_IRQn = 9U,
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Machine_External_IRQn = 11U,
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DMA_IRQn = 32U,
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CE_IRQn = 33U,
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USB_DEV_IRQn = 34U,
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USB_HOST0_EHCI_IRQn = 35U,
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USB_HOST0_OHCI_IRQn = 36U,
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USB_HOST1_EHCI_IRQn = 37U,
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USB_HOST1_OHCI_IRQn = 38U,
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GMAC0_IRQn = 39U,
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GMAC1_IRQn = 40U,
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QSPI0_IRQn = 44U,
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QSPI1_IRQn = 45U,
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QSPI2_IRQn = 42U,
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QSPI3_IRQn = 43U,
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SDMC0_IRQn = 46U,
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SDMC1_IRQn = 47U,
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SDMC2_IRQn = 48U,
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SPI_ENC_IRQn = 41U,
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PWMCS_FAULT_IRQn = 24U,
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PWMCS_PWM_IRQn = 25U,
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PWMCS_CAP_IRQn = 26U,
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PWMCS_QEP_IRQn = 27U,
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PSADC_IRQn = 28U,
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MTOP_IRQn = 51U,
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I2S0_IRQn = 52U,
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I2S1_IRQn = 53U,
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AUDIO_IRQn = 54U,
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GPIO_IRQn = 68U, /* 68~75 */
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#ifdef QEMU_RUN
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UART0_IRQn = 32U,
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#else
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UART0_IRQn = 76U,
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#endif
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UART1_IRQn = 77U,
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UART2_IRQn = 78U,
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UART3_IRQn = 79U,
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UART4_IRQn = 80U,
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UART5_IRQn = 81U,
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UART6_IRQn = 82U,
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UART7_IRQn = 83U,
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LCD_IRQn = 55U,
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MIPI_DSI_IRQn = 56U,
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DVP_IRQn = 57U,
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MIPI_CSI_IRQn = 58U,
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DE_IRQn = 59U,
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GE_IRQn = 60U,
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VE_IRQn = 61U,
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WDT_IRQn = 64U,
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RTC_IRQn = 50U,
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I2C0_IRQn = 84U,
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I2C1_IRQn = 85U,
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I2C2_IRQn = 86U,
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I2C3_IRQn = 87U,
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CAN0_IRQn = 88U,
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CAN1_IRQn = 89U,
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PWM_IRQn = 90U,
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GPAI_IRQn = 92U,
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RTP_IRQn = 93U,
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TSEN_IRQn = 94U,
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CIR_IRQn = 95U,
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MAX_IRQn,
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} IRQn_Type;
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#define UART_IRQn(id) (UART0_IRQn + id)
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#endif
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/* ================================================================================ */
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/* ================ Device Specific Peripheral Section ================ */
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/* ================================================================================ */
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/* ================================================================================ */
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/* ================ Peripheral memory map ================ */
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/* ================================================================================ */
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#ifdef QEMU_RUN
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/*
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qemu-system-riscv64 -cpu c906fd -machine smarth -nographic -s -S -monitor stdio
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(qemu) info mtree
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address-space: memory
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0000000000000000-ffffffffffffffff (prio 0, i/o): system
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0000000000000000-0000000007ffffff (prio 0, ram): smarth.sdram
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0000000010002000-0000000010002fff (prio 0, i/o): csky_exit
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0000000010011000-0000000010011fff (prio 0, i/o): csky_timer
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0000000010015000-0000000010015fff (prio 0, i/o): csky_uart
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0000004000000000-0000004003ffffff (prio 0, i/o): csky_plic
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0000004004000000-000000400400ffff (prio 0, i/o): csky_clint
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*/
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#define C906_PLIC_BASE 0x4000000000UL
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#define C906_CINT_BASE 0x4004000000UL
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#define DRAM_BASE 0x00000000UL
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#define UART0_BASE 0x10015000UL
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#define UART_BASE(id) (UART0_BASE + (id) * 0x1000UL)
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#define QEMU_IO_BASE 0x07000000UL
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#define BROM_BASE QEMU_IO_BASE
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#define SRAM_BASE QEMU_IO_BASE
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#define DMA_BASE QEMU_IO_BASE
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#define CE_BASE QEMU_IO_BASE
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#define USB_DEV_BASE QEMU_IO_BASE
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#define USB_HOST0_BASE QEMU_IO_BASE
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#define USB_HOST1_BASE QEMU_IO_BASE
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#define GMAC0_BASE QEMU_IO_BASE
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#define GMAC1_BASE QEMU_IO_BASE
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#define QSPI0_BASE QEMU_IO_BASE
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#define QSPI1_BASE QEMU_IO_BASE
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#define QSPI2_BASE QEMU_IO_BASE
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#define QSPI3_BASE QEMU_IO_BASE
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#define SDMC0_BASE QEMU_IO_BASE
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#define SDMC1_BASE QEMU_IO_BASE
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#define SDMC2_BASE QEMU_IO_BASE
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#define PBUS_BASE QEMU_IO_BASE
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#define SYSCFG_BASE QEMU_IO_BASE
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#define CMU_BASE QEMU_IO_BASE
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#define CMT_BASE QEMU_IO_BASE
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#define SPI_ENC_BASE QEMU_IO_BASE
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#define PWMCS_BASE QEMU_IO_BASE
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#define PSADC_BASE QEMU_IO_BASE
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#define DDR_CTL_BASE QEMU_IO_BASE
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#define DDR_MTOP_BASE QEMU_IO_BASE
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#define DDR_PHY_BASE QEMU_IO_BASE
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#define I2S0_BASE QEMU_IO_BASE
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#define I2S1_BASE QEMU_IO_BASE
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#define AUDIO_BASE QEMU_IO_BASE
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#define GPIO_BASE QEMU_IO_BASE
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#define PMT_BASE QEMU_IO_BASE
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#define UART1_BASE QEMU_IO_BASE
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#define UART2_BASE QEMU_IO_BASE
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#define UART3_BASE QEMU_IO_BASE
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#define UART4_BASE QEMU_IO_BASE
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#define UART5_BASE QEMU_IO_BASE
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#define UART6_BASE QEMU_IO_BASE
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#define UART7_BASE QEMU_IO_BASE
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#define LCD_BASE QEMU_IO_BASE
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#define LVDS_BASE QEMU_IO_BASE
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#define MIPI_DSI_BASE QEMU_IO_BASE
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#define DVP_BASE QEMU_IO_BASE
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#define MIPI_CSI_BASE QEMU_IO_BASE
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#define DE_BASE QEMU_IO_BASE
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#define GE_BASE QEMU_IO_BASE
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#define VE_BASE QEMU_IO_BASE
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#define WDT_BASE QEMU_IO_BASE
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#define WRI_BASE QEMU_IO_BASE
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#define SID_BASE QEMU_IO_BASE
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#define RTC_BASE QEMU_IO_BASE
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#define GTC_BASE QEMU_IO_BASE
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#define I2C0_BASE QEMU_IO_BASE
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#define I2C1_BASE QEMU_IO_BASE
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#define I2C2_BASE QEMU_IO_BASE
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#define I2C3_BASE QEMU_IO_BASE
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#define CAN0_BASE QEMU_IO_BASE
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#define CAN1_BASE QEMU_IO_BASE
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#define PWM_BASE QEMU_IO_BASE
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#define ADCIM_BASE QEMU_IO_BASE
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#define GPAI_BASE QEMU_IO_BASE
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#define RTP_BASE QEMU_IO_BASE
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#define TSEN_BASE QEMU_IO_BASE
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#define CIR_BASE QEMU_IO_BASE
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#else
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#define BROM_BASE 0x00000000UL /* - 0x0000FFFF, 64KB ,1MB */
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#define SRAM_BASE 0x00100000UL /* - 0x00117FFF, 96KB ,1MB */
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#define DMA_BASE 0x10000000UL /* - 0x1000FFFF, 64KB ,64KB */
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#define CE_BASE 0x10020000UL /* - 0x1002FFFF, 64KB ,64KB */
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#define USB_DEV_BASE 0x10200000UL /* - 0x1020FFFF, 64KB ,-- */
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#define USB_HOST0_BASE 0x10210000UL /* - 0x1021FFFF, 64KB ,-- */
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#define USB_HOST1_BASE 0x10220000UL /* - 0x1022FFFF, 64KB ,512KB */
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#define GMAC0_BASE 0x10280000UL /* - 0x1028FFFF, 64KB ,-- */
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#define GMAC1_BASE 0x10290000UL /* - 0x1029FFFF, 64KB ,512KB */
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#define QSPI0_BASE 0x10400000UL /* - 0x1040FFFF, 64KB ,-- */
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#define QSPI1_BASE 0x10410000UL /* - 0x1041FFFF, 64KB ,256KB */
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#define QSPI2_BASE 0x10420000UL /* - 0x1042FFFF, 64KB ,256KB */
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#define QSPI3_BASE 0x10430000UL /* - 0x1043FFFF, 64KB ,256KB */
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#define SDMC0_BASE 0x10440000UL /* - 0x1044FFFF, 64KB ,-- */
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#define SDMC1_BASE 0x10450000UL /* - 0x1045FFFF, 64KB ,-- */
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#define SDMC2_BASE 0x10460000UL /* - 0x1046FFFF, 64KB ,256KB */
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#define PBUS_BASE 0x107F0000UL /* - 0x1080FFFF, 128KB ,8MB */
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#define SYSCFG_BASE 0x18000000UL /* - 0x18000FFF, 4KB ,64KB */
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#define CMU_BASE 0x18020000UL /* - 0x18020FFF, 4KB ,32KB */
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#define CMT_BASE 0x18028000UL /* - 0x1802FFFF, 32KB ,-- */
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#define SPI_ENC_BASE 0x18100000UL /* - 0x18100FFF, 4KB ,-- */
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#define PWMCS_BASE 0x18200000UL /* - 0x1820FFFF, 64KB ,-- */
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#define PSADC_BASE 0x18210000UL /* - 0x18210FFF, 4KB ,-- */
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#define DDR_CTL_BASE 0x18400000UL /* - 0x1840FFFF, 64KB ,1MB */
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#define MTOP_BASE 0x184FF000UL /* - 0x184FFFFF, 4KB ,-- */
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#define DDR_PHY_BASE 0x18500000UL /* - 0x1850FFFF, 64KB ,1MB */
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#define I2S0_BASE 0x18600000UL /* - 0x18600FFF, 4KB ,-- */
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#define I2S1_BASE 0x18601000UL /* - 0x18601FFF, 4KB ,64KB */
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#define AUDIO_BASE 0x18610000UL /* - 0x18610FFF, 4KB ,64KB */
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#define GPIO_BASE 0x18700000UL /* - 0x18700FFF, 4KB ,64KB */
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#define PMT_BASE 0x1870F000UL /* - 0x1870FFFF, 4KB ,-- */
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#define UART0_BASE 0x18710000UL /* - 0x18710FFF, 4KB ,-- */
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#define UART1_BASE 0x18711000UL /* - 0x18711FFF, 4KB ,-- */
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#define UART2_BASE 0x18712000UL /* - 0x18712FFF, 4KB ,-- */
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#define UART3_BASE 0x18713000UL /* - 0x18713FFF, 4KB ,-- */
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#define UART4_BASE 0x18714000UL /* - 0x18714FFF, 4KB ,-- */
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#define UART5_BASE 0x18715000UL /* - 0x18715FFF, 4KB ,-- */
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#define UART6_BASE 0x18716000UL /* - 0x18716FFF, 4KB ,-- */
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#define UART7_BASE 0x18717000UL /* - 0x18717FFF, 4KB ,64KB */
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#define UART_BASE(id) (UART0_BASE + (id) * 0x1000UL)
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#define LCD_BASE 0x18800000UL /* - 0x18800FFF, 4KB ,64KB */
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#define LVDS_BASE 0x18810000UL /* - 0x18810FFF, 4KB ,64KB */
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#define MIPI_DSI_BASE 0x18820000UL /* - 0x18820FFF, 4KB ,64KB */
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#define DVP_BASE 0x18830000UL /* - 0x18830FFF, 4KB ,64KB */
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#define MIPI_CSI_BASE 0x18840000UL /* - 0x18840FFF, 4KB ,64KB */
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#define DE_BASE 0x18A00000UL /* - 0x18AFFFFF, 1MB ,1MB */
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#define GE_BASE 0x18B00000UL /* - 0x18BFFFFF, 1MB ,1MB */
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#define VE_BASE 0x18C00000UL /* - 0x18CFFFFF, 1MB ,1MB */
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#define WDT_BASE 0x19000000UL /* - 0x19000FFF, 4KB ,64KB */
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#define WRI_BASE 0x1900F000UL /* - 0x1900FFFF, 4KB ,64KB */
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#define SID_BASE 0x19010000UL /* - 0x19010FFF, 4KB ,64KB */
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#define RTC_BASE 0x19030000UL /* - 0x19030FFF, 4KB ,64KB */
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#define GTC_BASE 0x19050000UL /* - 0x19051FFF, 8KB ,64KB */
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#define I2C0_BASE 0x19220000UL /* - 0x19220FFF, 4KB ,-- */
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#define I2C1_BASE 0x19221000UL /* - 0x19221FFF, 4KB ,-- */
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#define I2C2_BASE 0x19222000UL /* - 0x19222FFF, 4KB ,-- */
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#define I2C3_BASE 0x19223000UL /* - 0x19223FFF, 4KB ,64KB */
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#define CAN0_BASE 0x19230000UL /* - 0x19230FFF, 4KB ,-- */
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#define CAN1_BASE 0x19231000UL /* - 0x19231FFF, 4KB ,64KB */
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#define PWM_BASE 0x19240000UL /* - 0x19240FFF, 4KB ,64KB */
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#define ADCIM_BASE 0x19250000UL /* - 0x19250FFF, 4KB ,-- */
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#define GPAI_BASE 0x19251000UL /* - 0x19251FFF, 4KB ,-- */
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#define RTP_BASE 0x19252000UL /* - 0x19252FFF, 4KB ,-- */
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#define TSEN_BASE 0x19253000UL /* - 0x19253FFF, 4KB ,-- */
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#define CIR_BASE 0x19260000UL /* - 0x19260FFF, 4KB ,-- */
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#define C906_CORE_BASE CPU_BASE
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#define C906_PLIC_BASE CPU_BASE
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#define C906_CINT_BASE (CPU_BASE + 0x4000000UL)
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#define DRAM_BASE 0x40000000UL /* - 0x7FFFFFFF, 1GB ,1GB */
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#endif
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/* ================================================================================ */
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/* ================ Peripheral declaration ================ */
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/* ================================================================================ */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _AIC_SOC_H_ */
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