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https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
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135 lines
3.3 KiB
C
135 lines
3.3 KiB
C
/*
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* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: matteo <duanmt@artinchip.com>
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*/
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#include "aic_core.h"
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#include "mpp_vin.h"
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#include "hal_dvp.h"
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static inline void dvp_writel(u32 val, int reg)
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{
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writel(val, DVP_BASE + reg);
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}
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static inline u32 dvp_readl(int reg)
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{
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return readl(DVP_BASE + reg);
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}
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static void aic_dvp_reg_enable(int offset, int bit, int enable)
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{
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int tmp;
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tmp = dvp_readl(offset);
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tmp &= ~bit;
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if (enable)
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tmp |= bit;
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dvp_writel(tmp, offset);
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}
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void aich_dvp_enable(int enable)
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{
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aic_dvp_reg_enable(DVP_CTL, DVP_CTL_DROP_FRAME_EN, enable);
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aic_dvp_reg_enable(DVP_CTL, DVP_CTL_EN, enable);
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}
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void aich_dvp_capture_start(void)
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{
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dvp_writel(DVP_OUT_CTL_CAP_ON, DVP_OUT_CTL);
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}
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void aich_dvp_capture_stop(void)
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{
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dvp_writel(0, DVP_OUT_CTL);
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}
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void aich_dvp_clr_fifo(void)
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{
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aic_dvp_reg_enable(DVP_CTL, DVP_CTL_CLR, 1);
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}
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int aich_dvp_clr_int(void)
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{
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int sta = dvp_readl(DVP_IRQ_STA);
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dvp_writel(sta, DVP_IRQ_STA);
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return sta;
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}
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void aich_dvp_enable_int(int enable)
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{
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aic_dvp_reg_enable(DVP_IRQ_EN, DVP_IRQ_EN_UPDATE_DONE, enable);
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aic_dvp_reg_enable(DVP_IRQ_EN, DVP_IRQ_EN_FRAME_DONE, enable);
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}
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void aich_dvp_set_pol(u32 flags)
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{
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u32 href_pol, pclk_pol, vref_pol, field_pol;
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href_pol = flags & MEDIA_SIGNAL_HSYNC_ACTIVE_HIGH ?
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DVP_IN_CFG_HREF_POL_ACTIVE_HIGH : 0;
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vref_pol = flags & MEDIA_SIGNAL_VSYNC_ACTIVE_HIGH ?
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DVP_IN_CFG_VSYNC_POL_ACTIVE_HIGH : 0;
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pclk_pol = flags & MEDIA_SIGNAL_PCLK_SAMPLE_RISING ?
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DVP_IN_CFG_PCLK_POL_RISING_EDGE : 0;
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field_pol = flags & MEDIA_SIGNAL_FIELD_EVEN_HIGH ?
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DVP_IN_CFG_FILED_POL_NORMAL : 0;
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dvp_writel(href_pol | vref_pol | pclk_pol | field_pol, DVP_IN_CFG);
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}
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void aich_dvp_set_cfg(struct aic_dvp_config *cfg)
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{
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dvp_writel(DVP_CTL_IN_FMT(cfg->input)
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| DVP_CTL_IN_SEQ(cfg->input_seq)
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| DVP_CTL_OUT_FMT(cfg->output)
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| DVP_CTL_DROP_FRAME_EN | DVP_CTL_EN, DVP_CTL);
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dvp_writel(DVP_OUT_HOR_NUM(cfg->width), DVP_OUT_HOR_SIZE);
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dvp_writel(DVP_OUT_VER_NUM(cfg->height), DVP_OUT_VER_SIZE);
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if ((cfg->stride[0] == 0) || (cfg->stride[1] == 0)) {
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hal_log_err("Invalid stride: 0x%x 0x%x\n", cfg->stride[0], cfg->stride[1]);
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return;
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}
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dvp_writel(cfg->stride[0], DVP_OUT_LINE_STRIDE0);
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dvp_writel(cfg->stride[1], DVP_OUT_LINE_STRIDE1);
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}
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void aich_dvp_update_buf_addr(dma_addr_t y, dma_addr_t uv)
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{
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if ((y == 0) || (uv == 0)) {
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hal_log_err("Invalid DMA address: Y 0x%x, UV 0x%x\n", (u32)y, (u32)uv);
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return;
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}
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dvp_writel(y, DVP_OUT_ADDR_BUF(0));
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dvp_writel(uv, DVP_OUT_ADDR_BUF(1));
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}
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void aich_dvp_update_ctl(void)
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{
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dvp_writel(1, DVP_OUT_UPDATE_CTL);
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}
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void aich_dvp_record_mode(void)
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{
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dvp_writel(0x80000000, DVP_OUT_FRA_NUM);
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}
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void aich_dvp_qos_cfg(u32 high, u32 low, u32 inc_thd, u32 dec_thd)
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{
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u32 val = DVP_QOS_CUSTOM;
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val |= (inc_thd << DVP_QOS_INC_THR_SHIFT) & DVP_QOS_INC_THR_MASK;
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val |= (dec_thd << DVP_QOS_DEC_THR_SHIFT) & DVP_QOS_DEC_THR_MASK;
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val |= (high << DVP_QOS_HIGH_SHIFT) & DVP_QOS_HIGH_MASK;
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val |= low & DVP_QOS_LOW_MASK;
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hal_log_info("DVP QoS is enable: 0x%x\n", val);
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dvp_writel(val, DVP_QOS_CFG);
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}
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