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https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
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282 lines
6.4 KiB
C
282 lines
6.4 KiB
C
/*
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* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: matteo <duanmt@artinchip.com>
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*/
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#include <string.h>
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#include "aic_core.h"
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#include "aic_hal_clk.h"
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#include "hal_cap.h"
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#define AIC_CAP_CH_NUM AIC_HRTIMER_CH_NUM
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/* Register definition of PWMCS Controller */
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#define CAP_BASE(n) (PWMCS_BASE + 0x1000 + 0x100 * (n))
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#define GLB_BASE (PWMCS_BASE + 0xF000)
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#define CAP_CNT_V(n) (CAP_BASE(n) + 0x00)
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#define CAP_CNT_PHV(n) (CAP_BASE(n) + 0x04)
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#define CAP_CNT_PRDV(n) (CAP_BASE(n) + 0x08)
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#define CAP_CNT_CMPV(n) (CAP_BASE(n) + 0x0c)
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#define CAP_CNT_PRDV_SH(n) (CAP_BASE(n) + 0x10)
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#define CAP_CNT_CMPV_SH(n) (CAP_BASE(n) + 0x14)
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#define CAP_CONF1(n) (CAP_BASE(n) + 0x18)
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#define CAP_CONF2(n) (CAP_BASE(n) + 0x1c)
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#define CAP_INT_EN(n) (CAP_BASE(n) + 0x20)
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#define CAP_FLG(n) (CAP_BASE(n) + 0x24)
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#define CAP_FLG_CLR(n) (CAP_BASE(n) + 0x28)
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#define CAP_SW_FRC(n) (CAP_BASE(n) + 0x2c)
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#define CAP_IN_FLT(n) (CAP_BASE(n) + 0x30)
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#define CAP_IN_SRC(n) (CAP_BASE(n) + 0x34)
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#define CAP_VER(n) (CAP_BASE(n) + 0xfc)
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#define GLB_CLK_CTL (GLB_BASE + 0x00)
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#define GLB_CAP_INT_STS (GLB_BASE + 0x0C)
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#define GLB_CLK_CTL_CAP_EN(n) (BIT(16) << (n))
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#define GLB_CAP_INT_STS_MASK(n) (1 << (n))
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#define CAP_CONF2_PWM_MODE BIT(9)
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#define CAP_CONF2_CNT_EN BIT(4)
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#define CAP_INT_EN_CNT_CMP BIT(7)
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#define CAP_INT_EN_CNT_PRD BIT(6)
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#define CAP_FLG_CLR_CMP BIT(7)
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#define CAP_FLG_CLR_PRD BIT(6)
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// #define CAP_USE_CMP_INT
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struct aic_cap_arg {
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u16 available;
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u16 id;
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u32 freq;
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u32 prd;
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u32 irq_cnt;
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};
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static struct aic_cap_arg g_cap_args[AIC_CAP_CH_NUM] = {{0}};
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static int g_cap_inited = 0;
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static void _cap_ch_info(char *buf, u32 ch, u32 en, struct aic_cap_arg *arg)
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{
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sprintf(buf, "%2d %2d %9d %10d/%-10d %10d\n",
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ch, en & GLB_CLK_CTL_CAP_EN(ch) ? 1 : 0,
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arg->freq, readl(CAP_CNT_PRDV(ch)), arg->prd, arg->irq_cnt);
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}
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void hal_cap_status_show(void)
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{
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int ver = readl(CAP_VER(0));
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int enable = readl(GLB_CLK_CTL);
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char info[AIC_CAP_CH_NUM][128] = {{0}};
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u32 i;
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printf("In CAP V%d.%02d:\n"
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"CAP Enable: 0x%x, IRQ Enable: 0x%x\n"
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"Ch En %9s %15s %16s\n",
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ver >> 8, ver & 0xFF, enable, readl(GLB_CAP_INT_STS),
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"Frequency", "Timeout cnt", "IRQ cnt");
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for (i = 0; i < AIC_CAP_CH_NUM; i++) {
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_cap_ch_info(info[i], i, enable, &g_cap_args[i]);
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printf("%s", info[i]);
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}
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}
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static void _cap_reg_enable(int addr, int bit, int enable)
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{
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int tmp;
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tmp = readl((ulong)addr);
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if (enable)
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tmp |= bit;
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else
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tmp &= ~bit;
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writel(tmp, (ulong)addr);
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}
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void hal_cap_ch_init(u32 ch)
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{
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struct aic_cap_arg *arg = &g_cap_args[ch];
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arg->available = 1;
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}
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void hal_cap_ch_deinit(u32 ch)
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{
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struct aic_cap_arg *arg = &g_cap_args[ch];
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arg->available = 0;
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}
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void hal_cap_int_enable(u32 ch, int enable)
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{
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if (enable) {
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#ifdef CAP_USE_CMP_INT
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writel(CAP_INT_EN_CNT_CMP, CAP_INT_EN(ch));
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#else
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writel(CAP_INT_EN_CNT_PRD, CAP_INT_EN(ch));
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#endif
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} else {
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writel(0, CAP_INT_EN(ch));
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}
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}
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u32 hal_cap_int_sta(void)
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{
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return readl(GLB_CAP_INT_STS);
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}
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u32 hal_cap_is_pending(u32 ch)
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{
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u32 pending = readl_bit(GLB_CAP_INT_STS_MASK(ch), GLB_CAP_INT_STS);
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g_cap_args[ch].irq_cnt += pending;
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if (pending)
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#ifdef CAP_USE_CMP_INT
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writel(CAP_FLG_CLR_CMP, CAP_FLG_CLR(ch));
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#else
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writel(CAP_FLG_CLR_PRD, CAP_FLG_CLR(ch));
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#endif
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return pending;
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}
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int hal_cap_enable(u32 ch)
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{
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struct aic_cap_arg *arg = &g_cap_args[ch];
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if (!arg->available) {
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hal_log_err("ch%d is unavailable\n", ch);
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return -EINVAL;
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}
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_cap_reg_enable(GLB_CLK_CTL, GLB_CLK_CTL_CAP_EN(ch), 1);
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_cap_reg_enable(CAP_CONF2(ch), CAP_CONF2_PWM_MODE, 1);
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writel(readl(CAP_FLG(ch)), CAP_FLG_CLR(ch));
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return 0;
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}
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int hal_cap_disable(u32 ch)
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{
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struct aic_cap_arg *arg = &g_cap_args[ch];
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if (!arg->available) {
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hal_log_err("ch%d is unavailable\n", ch);
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return -EINVAL;
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}
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_cap_reg_enable(GLB_CLK_CTL, GLB_CLK_CTL_CAP_EN(ch), 0);
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return 0;
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}
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void hal_cap_cnt_start(u32 ch)
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{
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_cap_reg_enable(CAP_CONF2(ch), CAP_CONF2_CNT_EN, 1);
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}
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void hal_cap_cnt_stop(u32 ch)
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{
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_cap_reg_enable(CAP_CONF2(ch), CAP_CONF2_CNT_EN, 0);
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}
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int hal_cap_set_freq(u32 ch, u32 freq)
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{
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struct aic_cap_arg *arg = &g_cap_args[ch];
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if (!arg->available) {
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hal_log_err("ch%d is unavailable\n", ch);
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return -EINVAL;
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}
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if (freq > CAP_MAX_FREQ) {
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hal_log_err("ch%d freq %d is out of range\n", ch, freq);
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return -ERANGE;
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}
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arg->freq = freq;
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arg->prd = PWMCS_CLK_RATE / freq;
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return 0;
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}
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int hal_cap_set_cnt(u32 ch, u32 cnt)
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{
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struct aic_cap_arg *arg = &g_cap_args[ch];
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if (!arg->available) {
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hal_log_err("ch%d is unavailable\n", ch);
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return -EINVAL;
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}
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arg->prd = (PWMCS_CLK_RATE / arg->freq) * cnt;
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writel(arg->prd, CAP_CNT_PRDV(ch));
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#ifdef CAP_USE_CMP_INT
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writel(arg->prd - (arg->prd >> 4), CAP_CNT_CMPV(ch));
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#endif
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writel(0, CAP_CNT_V(ch));
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return 0;
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}
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int hal_cap_get(u32 ch)
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{
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return readl(CAP_CNT_V(ch));
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}
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int hal_cap_init(void)
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{
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int i, ret = 0;
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if (g_cap_inited) {
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hal_log_debug("PWMCS was already inited\n");
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return 0;
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}
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ret = hal_clk_set_freq(CLK_PWMCS, PWMCS_CLK_RATE);
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if (ret < 0) {
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hal_log_err("Failed to set PWMCS clk %d\n", PWMCS_CLK_RATE);
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return -1;
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}
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ret = hal_clk_enable(CLK_PWMCS);
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if (ret < 0) {
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hal_log_err("Failed to enable PWMCS clk\n");
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return -1;
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}
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ret = hal_clk_enable_deassertrst(CLK_PWMCS);
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if (ret < 0) {
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hal_log_err("Failed to reset PWMCS deassert\n");
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return -1;
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}
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/* default configuration */
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for (i = 0; i < AIC_CAP_CH_NUM; i++) {
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g_cap_args[i].id = i;
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g_cap_args[i].freq = CAP_MAX_FREQ;
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}
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g_cap_inited = 1;
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return 0;
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}
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int hal_cap_deinit(void)
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{
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u32 i;
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for (i = 0; i < AIC_CAP_CH_NUM; i++)
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if (g_cap_args[i].available)
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hal_cap_disable(i);
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hal_clk_disable_assertrst(CLK_PWMCS);
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hal_clk_disable(CLK_PWMCS);
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g_cap_inited = 0;
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return 0;
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}
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