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321 lines
8.1 KiB
C
321 lines
8.1 KiB
C
/*
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* Copyright (C) 2020-2022 Artinchip Technology Co. Ltd
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*
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* author: <qi.xu@artinchip.com>
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* Desc: avc register
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*/
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#ifndef __H264_HAL_H__
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#define __H264_HAL_H__
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#define AVC_RESET_REG 0x100
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struct reg_avc_sps
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{
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unsigned pic_height_in_map_units_minus1 : 7; //[6:0]
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unsigned r0 : 1;
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unsigned pic_width_in_mbs_minus1 : 7;// [14:8]
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unsigned r1 : 1;
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unsigned direct_8x8_inference_flag : 1;
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unsigned mb_adaptive_frame_filed_flag : 1;
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unsigned frame_mbs_only_flag : 1;
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unsigned uv_interleave : 1;
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unsigned uv_alter : 1;
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unsigned chroma_format_idc : 2; //[22:21]:
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unsigned r : 8;
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unsigned pic_init : 1;
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};
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#define AVC_SPS_REG 0x104
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struct reg_avc_pps
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{
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unsigned transform_8x8_mode_flag : 1;
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unsigned constrained_intra_pred_flag : 1;
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unsigned weighted_bipred_idc : 2;
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unsigned weighted_pred_flag : 1;
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unsigned entropy_coding_mode_flag : 1;
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unsigned r0 : 2;
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unsigned num_ref_idx_l1_active_minus1_pic : 5;
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unsigned r1 : 3;
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unsigned num_ref_idx_l0_active_minus1_pic : 5;
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unsigned r2 : 11;
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};
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#define AVC_PPS_REG 0x108
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struct reg_avc_sh1
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{
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unsigned cabac_init_idc : 2; // [1:0]
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unsigned direct_spatial_mv_pred_flag : 1;
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unsigned bottom_field_flag : 1;
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unsigned field_pic_flag : 1;
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unsigned first_slice_in_pic : 1;
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unsigned r0 : 2;
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unsigned slice_type : 4;
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unsigned nal_ref_flag : 1;
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unsigned r1 : 3;
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unsigned first_mb_y : 7;
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unsigned r2 : 1;
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unsigned first_mb_x : 7;
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unsigned r3 : 1;
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};
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#define AVC_SHS1_REG 0x10C
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struct reg_avc_sh2
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{
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unsigned slice_beta_offset_div2 : 4;
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unsigned slice_alpha_offset_div2 : 4;
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unsigned disable_deblocking_filter_idc : 2;
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unsigned r0 : 2;
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unsigned num_ref_idx_active_override_flag : 1;
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unsigned r1 : 3;
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unsigned num_ref_idx_l1_active_minus1 : 5;
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unsigned r2 : 3;
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unsigned num_ref_idx_l0_active_minus1 : 5;
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unsigned r3 : 3;
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};
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#define AVC_SHS2_REG 0x110
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struct reg_avc_shs_wp
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{
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unsigned r : 24;
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unsigned chroma_log2_weight_denom : 3;
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unsigned r0 : 1;
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unsigned luma_log2_weight_denom : 3;
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unsigned r1 : 1;
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};
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#define AVC_SHS_WP_REG 0x114
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struct reg_avc_weight_pred
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{
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unsigned offset : 8; // [7:0]:offset
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unsigned weight : 9; // [16:8]:weight
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unsigned r : 7;
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/*
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0x00-0x1F is Luma_L0;
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0x20-0x3F is Chroma_Cb_L0;
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0x40-0x5F is Chroma_Cr_L0;
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0x60-0x7F is Luma_L1;
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0x80-0x9F is Chroma_Cb_L1;
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0xA0-0xBF is Chroma_Cr_L1
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*/
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unsigned weight_pred_addr : 8;
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};
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#define AVC_WEIGHT_PRED_REGISTER 0x118
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struct reg_avc_scaling_matrix
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{
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unsigned scaling_matrix_data : 9; // [8:0],
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unsigned r0 : 7;
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/*
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000: S1_4x4_intra_Y
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001: S1_4x4_intra_Cb
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010: S1_4x4_intra_Cr
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011: S1_4x4_inter_Y
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100: S1_4x4_inter_Cb
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101: S1_4x4_inter_Cr
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110: S1_8x8_intra_Y
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111: S1_8x8_inter_Y
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*/
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unsigned matrix_addr : 8; // [23:16]
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unsigned r1 : 6;
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unsigned write_enable : 1; // [30]
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unsigned matrix_access : 1; // [31]
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};
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#define AVC_SCALING_MATRIX_REGISTER 0x11C
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struct reg_avc_shs_qp
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{
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unsigned slice_qpy : 6; // [5:0]: Slice header qp_y, value range 0~51
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unsigned r0 : 2;
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unsigned chroma_qp_idx_offset : 6; // [13:8]: Cb qp offset, value range -12~12
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unsigned r1 : 2;
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unsigned second_chroma_qp_idx_offset : 6; // [21:16]: Cr qp offset, value range -12~12
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unsigned r2 : 10;
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};
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#define AVC_SHS_QP_REG 0x120
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struct reg_avc_ctrl
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{
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unsigned r0 : 3;
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unsigned dec_finish_int_enable : 1; // [3]: finish irq enable
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unsigned dec_error_int_enable : 1; // [4]: error irq enable
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unsigned bit_request_int_enable : 1; // [5]: bit request irq enable
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unsigned r1 : 7;
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unsigned eptb_detection : 1; // [13], detect emulation_prevention_three_byte (0x03) enable
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unsigned stcd_detect_en : 1; // [14], detect startcode enable
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unsigned r2 : 16;
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unsigned slice_start : 1; // [31], slice decode start
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};
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#define AVC_CTRL_REG 0x124
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struct reg_ve_status
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{
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unsigned busy_status : 9; // [0]: (RO) internal module status
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unsigned r0 : 7;
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unsigned ve_finish : 1; // [16]: finish status, write 1 clear irq
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unsigned bit_request : 1; // [17]: bitrequest status, write 1 clear irq
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unsigned ve_error : 1; // [18]: error status, write 1 clear irq
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unsigned r1 : 9;
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unsigned error_case : 4; // [28]: mb_prefix dec err
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// [29]: mb header dec err
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// [30]: blk coeff dec err
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// [31]: bit stream err
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};
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#define VE_STATUS_REG 0x128
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#define CORRECT_DECODE_MB_NUMBER_REG 0x12C
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struct reg_ve_bit_buffer_valid
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{
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unsigned data_first : 1; // [0]: first part of a picture data
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unsigned data_last : 1; // [1]: last part
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unsigned r : 29;
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unsigned data_valid : 1; // [31]: valid data
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};
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#define BIT_BUFFER_DATA_VALID_REG 0x130
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#define BIT_BUFFER_START_ADDR_REG 0x134
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#define BIT_BUFFER_END_ADDR_REG 0x138
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#define BIT_BUFFER_BIT_OFFSET_REG 0x13C
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#define BIT_BUFFER_BIT_LEN_REG 0x140
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struct reg_avc_ref_list
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{
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unsigned field_sel_list0 : 1; // [0]: 0:top field, 1:bottom field
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unsigned buf_idx_list0 : 5; // [5:1]: frame idx of forward reference
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unsigned r0 : 2;
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unsigned field_sel_list1 : 1; // [8]: 0:top field, 1:bottom field
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unsigned buf_idx_list1 : 5; // [13:9]: frame idx of backward reference
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unsigned r1 : 2;
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unsigned ref_idx : 5; // [20:16]: ref idx of refrence list, val range 0-31.
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unsigned r2 : 10;
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unsigned ref_idx_rw : 1; // [31]: 0:read from ve; 1: write to ve
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};
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#define AVC_REF_LIST_REGISTER 0x144
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struct frame_struct_ref_info
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{
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// top field refrence type: 00 (short-term); 01 (long-term); 10 (non-refrence); 11(reserve)
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unsigned top_ref_type : 2;
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unsigned r0 : 2;
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// bottom field refrence type: 00 (short-term); 01 (long-term); 10 (non-refrence); 11(reserve)
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unsigned bot_ref_type : 2;
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unsigned r1 : 2;
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// picture type: 00 (frame); 01(field); 10(mbaff)
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unsigned frm_struct : 2;
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unsigned r2 : 22;
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};
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struct reg_avc_buf_info
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{
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/*
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select content of frame buffer
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000：top poc
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001：bottom poc
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010：pic info, Frame_Struct_Ref_Info
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101：top field/frame mv collocated info start address in DRAM
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110：bottpm field/frame mv collocated info start address in DRAM
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*/
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unsigned curr_frame_idx : 5; // [4:0]
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unsigned r0 : 3;
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unsigned buf_idx : 5; // [12:8]
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unsigned r1 : 3;
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unsigned content_select : 3; // [18:16]
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unsigned r2 : 12;
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unsigned buf_info_rw : 1; // [31]:
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};
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#define AVC_BUF_INFO_REGISTER 0x148
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#define AVC_BUF_INFO_CONTENT_REGISTER 0x14C
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// co-located info used for direct pred in B-skip, need memory size(17 * 4K byte)
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#define MB_COL_BUF_ADDR_REG 0x150
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#define MBINFO_BUF_ADDR_REG 0x154
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//* store the last line data of last mb line for intra-pred
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#define MB_INTRAP_ADDR_REG 0x1D4
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#define CYCLES_REG 0x1F8
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/***************************************************************************************************/
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/***************************** DBLK reg **********************************************************/
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struct reg_pic_type
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{
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unsigned bottom_field_flag : 1; // 0: top field, 1: bottom field;
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unsigned field : 1; // 0: frame picture, 1: field
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unsigned mbaff : 1; // mbaffFrameFlag
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unsigned r1 : 29;
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};
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#define DBLK_PIC_TYPE_REG 0x210
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struct reg_pic_size
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{
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unsigned pic_ysize : 12; // [11:0]
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unsigned r0 : 4;
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unsigned pic_xsize : 12; // [27:16]
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unsigned r1 : 4;
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};
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#define DBLK_PIC_SIZE_REG 0x214
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struct reg_dblk_type
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{
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unsigned dblk_enable : 1; //
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unsigned r1 : 31;
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};
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#define DBLK_EN_REG 0x240
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#define DBLK_BUF_Y_REG 0x244
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#define DBLK_BUF_C_REG 0x248
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struct reg_dec_config
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{
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unsigned r0 : 2;
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unsigned uv_interleave : 1; //
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unsigned uv_alternative : 1; // 0:cbcr 1:crcb
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unsigned dec_chroma_idc : 2; // 00-420; 01-400
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unsigned dec_luma_only : 1;
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unsigned r1 : 1;
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unsigned dec_wr_en : 1; // write 1
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unsigned r : 23;
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};
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#define DEC_CONFIG_REG 0x24C
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#define DEC_FRAME_IDX_REG 0x250
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/********************************** MC *************************************************************/
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#define MC_DMA_MODE_REG 0x448
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struct mc_wp_en
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{
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unsigned implicited_en: 1; // B slice && weighted_bipred_idc == 2, set 1
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unsigned weighted_en : 1; // weighted pred enable
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unsigned r : 30;
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};
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#define MC_WP_EN_REG 0x480
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struct mc_wp_logwd
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{
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unsigned logwd_y : 3;
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unsigned logwd_c : 3;
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unsigned r : 26;
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};
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#define MC_WP_LOGWD_REG 0x484
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/*******************************************************************************************************/
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enum AVC_STATUS
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{
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AVC_FINISH = 1<<16,
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AVC_BIT_REQ = 1 << 17,
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AVC_ERROR = 1 << 18,
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};
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#endif
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