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58 lines
1.3 KiB
C
58 lines
1.3 KiB
C
/*
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* Copyright (c) 2023, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: matteo <duanmt@artinchip.com>
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*/
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#ifndef _ARTINCHIP_HAL_WRI_H_
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#define _ARTINCHIP_HAL_WRI_H_
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#include "aic_common.h"
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#if defined(AIC_WRI_DRV_V12) || defined(AIC_WRI_DRV_V11) || defined(AIC_WRI_DRV_V10)
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enum aic_warm_reset_type {
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WRI_TYPE_POR = 0,
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WRI_TYPE_RTC,
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WRI_TYPE_EXT,
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WRI_TYPE_DM,
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WRI_TYPE_WDT,
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WRI_TYPE_TSEN,
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WRI_TYPE_CMP,
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WRI_TYPE_MAX
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};
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#endif
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#if defined(AIC_WRI_DRV_V13)
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enum aic_warm_reset_type {
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WRI_TYPE_VDD11_SP_POR = 0,
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WRI_TYPE_VDD11_SW_POR,
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WRI_TYPE_RTC_POR,
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WRI_TYPE_PIN_RST,
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WRI_TYPE_THS_RST,
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WRI_TYPE_SP_WDOG_SYS_RST,
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WRI_TYPE_SP_WDOG_CPU_RST,
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WRI_TYPE_SP_DM_NDM_RST,
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WRI_TYPE_SP_DM_CPU_RST,
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WRI_TYPE_CS_WDOG_SYS_RST,
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WRI_TYPE_CS_WDOG_CPU_RST,
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WRI_TYPE_CS_DM_NDM_RST,
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WRI_TYPE_CS_DM_CPU_RST,
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WRI_TYPE_SC_WDOG_SYS_RST,
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WRI_TYPE_SC_WDOG_CPU_RST,
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WRI_TYPE_SC_DM_NDM_RST,
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WRI_TYPE_SC_DM_CPU_RST,
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WRI_TYPE_SE_WDOG_SYS_RST,
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WRI_TYPE_SE_WDOG_CPU_RST,
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WRI_TYPE_SE_DM_NDM_RST,
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WRI_TYPE_MAX
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};
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#endif
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enum aic_warm_reset_type aic_wr_type_get(void);
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enum aic_reboot_reason aic_judge_reboot_reason(enum aic_warm_reset_type hw,
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u32 sw);
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#endif
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