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541 lines
19 KiB
ArmAsm
541 lines
19 KiB
ArmAsm
/*
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* FreeRTOS Kernel V10.4.3 LTS Patch 3
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* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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* 1 tab == 4 spaces!
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*/
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/*
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* The FreeRTOS kernel's RISC-V port is split between the the code that is
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* common across all currently supported RISC-V chips (implementations of the
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* RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
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*
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* + The code that is common to all RISC-V chips is implemented in
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* FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one
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* portASM.S file because the same file is used no matter which RISC-V chip is
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* in use.
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*
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* + The code that tailors the kernel's RISC-V port to a specific RISC-V
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* chip is implemented in freertos_risc_v_chip_specific_extensions.h. There
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* is one freertos_risc_v_chip_specific_extensions.h that can be used with any
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* RISC-V chip that both includes a standard CLINT and does not add to the
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* base set of RISC-V registers. There are additional
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* freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations
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* that do not include a standard CLINT or do add to the base set of RISC-V
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* registers.
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*
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* CARE MUST BE TAKEN TO INCLDUE THE CORRECT
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* freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP
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* IN USE. To include the correct freertos_risc_v_chip_specific_extensions.h
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* header file ensure the path to the correct header file is in the assembler's
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* include path.
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*
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* This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips
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* that include a standard CLINT and do not add to the base set of RISC-V
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* registers.
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*
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*/
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#include "cpuport.h"
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#if __riscv_xlen == 64
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#define portWORD_SIZE 8
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#define store_x sd
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#define load_x ld
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#elif __riscv_xlen == 32
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#define store_x sw
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#define load_x lw
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#define portWORD_SIZE 4
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#else
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#error Assembler did not define __riscv_xlen
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#endif
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#if defined(__riscv_d)
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#define portFWORD_SIZE 8
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#define store_f fsd
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#define load_f fld
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#elif defined(__riscv_f)
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#define store_f fsw
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#define load_f flw
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#define portFWORD_SIZE 4
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#endif
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#include "freertos_risc_v_chip_specific_extensions.h"
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/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line
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definitions. */
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#if defined( portasmHAS_CLINT ) && defined( portasmHAS_MTIME )
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#error The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME. portasmHAS_CLINT and portasmHAS_MTIME cannot both be defined at once. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
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#endif
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#ifdef portasmHAS_CLINT
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#warning The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT. For now portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT are derived from portasmHAS_CLINT. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
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#define portasmHAS_MTIME portasmHAS_CLINT
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#define portasmHAS_SIFIVE_CLINT portasmHAS_CLINT
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#endif
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#ifndef portasmHAS_MTIME
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#error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_MTIME to either 1 (MTIME clock present) or 0 (MTIME clock not present). See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
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#endif
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#ifndef portasmHAS_SIFIVE_CLINT
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#define portasmHAS_SIFIVE_CLINT 0
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#endif
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/* Only the standard core registers are stored by default. Any additional
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registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and
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portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip
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specific version of freertos_risc_v_chip_specific_extensions.h. See the notes
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at the top of this file. */
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#if defined(__riscv_p)
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#define portCONTEXT_SIZE ( 31 * portWORD_SIZE )
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#else
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#define portCONTEXT_SIZE ( 30 * portWORD_SIZE )
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#endif
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#if defined(__riscv_d) || defined(__riscv_f)
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#define FLOAT_REG_NUM 32
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#define portFCONTEXT_SIZE ( FLOAT_REG_NUM * portFWORD_SIZE )
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#endif
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.global xPortStartFirstTask
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.global PendSV_Handler
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.global freertos_risc_v_trap_handler
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.global pxPortInitialiseStack
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.extern pxCurrentTCB
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.extern ulPortTrapHandler
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.extern vTaskSwitchContext
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.extern xTaskIncrementTick
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.extern Timer_IRQHandler
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.extern pullMachineTimerCompareRegister
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.extern pullNextTime
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.extern uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */
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.extern xISRStackTop
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.extern portasmHANDLE_INTERRUPT
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/*-----------------------------------------------------------*/
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/*
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* Functions: vPortYield
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*/
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.global vPortYield
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.type vPortYield, %function
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vPortYield:
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li t0, TSPEND_ADDR
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lb t1, (t0)
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li t2, 0x01
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or t1, t1, t2
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sb t1, (t0)
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/* make sure wite instruction is complete */
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fence
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lb t1, (t0)
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fence
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#ifdef __riscv_xthead
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sync.i
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#else
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.long 0x01a0000b
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#endif
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ret
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.align 8
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.func
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PendSV_Handler:
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freertos_risc_v_trap_handler:
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#ifdef CONFIG_THEAD_EXT_SPSWAPEN
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csrrw sp, mscratch, sp
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#endif
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// portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
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#if defined(__riscv_d) || defined(__riscv_f)
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addi sp, sp, -portFCONTEXT_SIZE
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store_f f0, 0 * portFWORD_SIZE( sp )
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store_f f1, 1 * portFWORD_SIZE( sp )
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store_f f2, 2 * portFWORD_SIZE( sp )
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store_f f3, 3 * portFWORD_SIZE( sp )
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store_f f4, 4 * portFWORD_SIZE( sp )
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store_f f5, 5 * portFWORD_SIZE( sp )
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store_f f6, 6 * portFWORD_SIZE( sp )
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store_f f7, 7 * portFWORD_SIZE( sp )
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store_f f8, 8 * portFWORD_SIZE( sp )
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store_f f9, 9 * portFWORD_SIZE( sp )
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store_f f10, 10 * portFWORD_SIZE( sp )
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store_f f11, 11 * portFWORD_SIZE( sp )
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store_f f12, 12 * portFWORD_SIZE( sp )
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store_f f13, 13 * portFWORD_SIZE( sp )
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store_f f14, 14 * portFWORD_SIZE( sp )
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store_f f15, 15 * portFWORD_SIZE( sp )
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store_f f16, 16 * portFWORD_SIZE( sp )
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store_f f17, 17 * portFWORD_SIZE( sp )
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store_f f18, 18 * portFWORD_SIZE( sp )
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store_f f19, 19 * portFWORD_SIZE( sp )
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store_f f20, 20 * portFWORD_SIZE( sp )
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store_f f21, 21 * portFWORD_SIZE( sp )
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store_f f22, 22 * portFWORD_SIZE( sp )
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store_f f23, 23 * portFWORD_SIZE( sp )
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store_f f24, 24 * portFWORD_SIZE( sp )
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store_f f25, 25 * portFWORD_SIZE( sp )
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store_f f26, 26 * portFWORD_SIZE( sp )
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store_f f27, 27 * portFWORD_SIZE( sp )
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store_f f28, 28 * portFWORD_SIZE( sp )
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store_f f29, 29 * portFWORD_SIZE( sp )
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store_f f30, 30 * portFWORD_SIZE( sp )
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store_f f31, 31 * portFWORD_SIZE( sp )
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#endif
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addi sp, sp, -portCONTEXT_SIZE
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store_x x1, 1 * portWORD_SIZE( sp )
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store_x x5, 2 * portWORD_SIZE( sp )
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store_x x6, 3 * portWORD_SIZE( sp )
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store_x x7, 4 * portWORD_SIZE( sp )
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store_x x8, 5 * portWORD_SIZE( sp )
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store_x x9, 6 * portWORD_SIZE( sp )
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store_x x10, 7 * portWORD_SIZE( sp )
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store_x x11, 8 * portWORD_SIZE( sp )
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store_x x12, 9 * portWORD_SIZE( sp )
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store_x x13, 10 * portWORD_SIZE( sp )
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store_x x14, 11 * portWORD_SIZE( sp )
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store_x x15, 12 * portWORD_SIZE( sp )
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store_x x16, 13 * portWORD_SIZE( sp )
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store_x x17, 14 * portWORD_SIZE( sp )
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store_x x18, 15 * portWORD_SIZE( sp )
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store_x x19, 16 * portWORD_SIZE( sp )
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store_x x20, 17 * portWORD_SIZE( sp )
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store_x x21, 18 * portWORD_SIZE( sp )
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store_x x22, 19 * portWORD_SIZE( sp )
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store_x x23, 20 * portWORD_SIZE( sp )
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store_x x24, 21 * portWORD_SIZE( sp )
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store_x x25, 22 * portWORD_SIZE( sp )
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store_x x26, 23 * portWORD_SIZE( sp )
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store_x x27, 24 * portWORD_SIZE( sp )
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store_x x28, 25 * portWORD_SIZE( sp )
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store_x x29, 26 * portWORD_SIZE( sp )
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store_x x30, 27 * portWORD_SIZE( sp )
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store_x x31, 28 * portWORD_SIZE( sp )
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csrr t0, mstatus /* Required for MPIE bit. */
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store_x t0, 29 * portWORD_SIZE( sp )
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#if defined(__riscv_p)
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csrr t0, vxsat
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store_x t0, 30 * portWORD_SIZE( sp )
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#endif
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csrr a1, mepc
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store_x a1, 0( sp ) /* Save updated exception return address. */
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load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */
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store_x sp, 0( t0 ) /* Write sp to first TCB member. */
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load_x sp, xISRStackTop /* Switch to ISR stack before function call. */
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jal vTaskSwitchContext
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#ifdef TSPEND_NEED_CLEAR
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/* clear software interrupt */
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li t0, TSPEND_ADDR
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li t1, 0x0
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sw t1, (t0)
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/* make sure wite instruction is complete */
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fence
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lb t1, (t0)
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#endif
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load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */
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load_x sp, 0( t1 ) /* Read sp from first TCB member. */
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/* Load mret with the address of the next instruction in the task to run next. */
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load_x t0, 0( sp )
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csrw mepc, t0
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#if defined(__riscv_p)
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load_x t0, 30( sp )
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csrw vxsat, t0
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#endif
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/* Load mstatus with the interrupt enable bits used by the task. */
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load_x t0, 29 * portWORD_SIZE( sp )
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csrw mstatus, t0 /* Required for MPIE bit. */
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load_x x1, 1 * portWORD_SIZE( sp )
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load_x x5, 2 * portWORD_SIZE( sp ) /* t0 */
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load_x x6, 3 * portWORD_SIZE( sp ) /* t1 */
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load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */
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load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
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load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
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load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */
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load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */
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load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */
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load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */
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load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */
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load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */
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load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */
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load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */
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load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */
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load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */
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load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */
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load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */
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load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */
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load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */
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load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */
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load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */
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load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */
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load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */
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load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */
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load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */
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load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */
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load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */
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addi sp, sp, portCONTEXT_SIZE
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//portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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#if defined(__riscv_d) || defined(__riscv_f)
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load_f f0, 0 * portFWORD_SIZE( sp )
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load_f f1, 1 * portFWORD_SIZE( sp )
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load_f f2, 2 * portFWORD_SIZE( sp )
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load_f f3, 3 * portFWORD_SIZE( sp )
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load_f f4, 4 * portFWORD_SIZE( sp )
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load_f f5, 5 * portFWORD_SIZE( sp )
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load_f f6, 6 * portFWORD_SIZE( sp )
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load_f f7, 7 * portFWORD_SIZE( sp )
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load_f f8, 8 * portFWORD_SIZE( sp )
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load_f f9, 9 * portFWORD_SIZE( sp )
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load_f f10, 10 * portFWORD_SIZE( sp )
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load_f f11, 11 * portFWORD_SIZE( sp )
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load_f f12, 12 * portFWORD_SIZE( sp )
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load_f f13, 13 * portFWORD_SIZE( sp )
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load_f f14, 14 * portFWORD_SIZE( sp )
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load_f f15, 15 * portFWORD_SIZE( sp )
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load_f f16, 16 * portFWORD_SIZE( sp )
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load_f f17, 17 * portFWORD_SIZE( sp )
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load_f f18, 18 * portFWORD_SIZE( sp )
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load_f f19, 19 * portFWORD_SIZE( sp )
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load_f f20, 20 * portFWORD_SIZE( sp )
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load_f f21, 21 * portFWORD_SIZE( sp )
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load_f f22, 22 * portFWORD_SIZE( sp )
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load_f f23, 23 * portFWORD_SIZE( sp )
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load_f f24, 24 * portFWORD_SIZE( sp )
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load_f f25, 25 * portFWORD_SIZE( sp )
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load_f f26, 26 * portFWORD_SIZE( sp )
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load_f f27, 27 * portFWORD_SIZE( sp )
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load_f f28, 28 * portFWORD_SIZE( sp )
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load_f f29, 29 * portFWORD_SIZE( sp )
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load_f f30, 30 * portFWORD_SIZE( sp )
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load_f f31, 31 * portFWORD_SIZE( sp )
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addi sp, sp, portFCONTEXT_SIZE
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#endif
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#ifdef CONFIG_THEAD_EXT_SPSWAPEN
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csrrw sp, mscratch, sp
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#endif
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mret
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.endfunc
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/*-----------------------------------------------------------*/
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.align 8
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.func
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xPortStartFirstTask:
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load_x sp, pxCurrentTCB /* Load pxCurrentTCB. */
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load_x sp, 0( sp ) /* Read sp from first TCB member. */
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load_x x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
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#if defined(__riscv_p)
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load_x t0, 30( sp )
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csrw vxsat, t0
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#endif
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load_x x6, 3 * portWORD_SIZE( sp ) /* t1 */
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load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */
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load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
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load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
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load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */
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load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */
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load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */
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load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */
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load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */
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load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */
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load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */
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load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */
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load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */
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load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */
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load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */
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load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */
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load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */
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load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */
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load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */
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load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */
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load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */
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load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */
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load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */
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load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */
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load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */
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load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */
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load_x x5, 29 * portWORD_SIZE( sp ) /* Initial mstatus into x5 (t0) */
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addi x5, x5, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */
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csrrw x0, mstatus, x5 /* Interrupts enabled from here! */
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load_x x5, 2 * portWORD_SIZE( sp ) /* Initial x5 (t0) value. */
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addi sp, sp, portCONTEXT_SIZE
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|
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//portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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#if defined(__riscv_d) || defined(__riscv_f)
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load_f f0, 0 * portFWORD_SIZE( sp )
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load_f f1, 1 * portFWORD_SIZE( sp )
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load_f f2, 2 * portFWORD_SIZE( sp )
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load_f f3, 3 * portFWORD_SIZE( sp )
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load_f f4, 4 * portFWORD_SIZE( sp )
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load_f f5, 5 * portFWORD_SIZE( sp )
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load_f f6, 6 * portFWORD_SIZE( sp )
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load_f f7, 7 * portFWORD_SIZE( sp )
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load_f f8, 8 * portFWORD_SIZE( sp )
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load_f f9, 9 * portFWORD_SIZE( sp )
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load_f f10, 10 * portFWORD_SIZE( sp )
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load_f f11, 11 * portFWORD_SIZE( sp )
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load_f f12, 12 * portFWORD_SIZE( sp )
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load_f f13, 13 * portFWORD_SIZE( sp )
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load_f f14, 14 * portFWORD_SIZE( sp )
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load_f f15, 15 * portFWORD_SIZE( sp )
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load_f f16, 16 * portFWORD_SIZE( sp )
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load_f f17, 17 * portFWORD_SIZE( sp )
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load_f f18, 18 * portFWORD_SIZE( sp )
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load_f f19, 19 * portFWORD_SIZE( sp )
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load_f f20, 20 * portFWORD_SIZE( sp )
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|
load_f f21, 21 * portFWORD_SIZE( sp )
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load_f f22, 22 * portFWORD_SIZE( sp )
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|
load_f f23, 23 * portFWORD_SIZE( sp )
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|
load_f f24, 24 * portFWORD_SIZE( sp )
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load_f f25, 25 * portFWORD_SIZE( sp )
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|
load_f f26, 26 * portFWORD_SIZE( sp )
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|
load_f f27, 27 * portFWORD_SIZE( sp )
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load_f f28, 28 * portFWORD_SIZE( sp )
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|
load_f f29, 29 * portFWORD_SIZE( sp )
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load_f f30, 30 * portFWORD_SIZE( sp )
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load_f f31, 31 * portFWORD_SIZE( sp )
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addi sp, sp, portFCONTEXT_SIZE
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#endif
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ret
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.endfunc
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/*-----------------------------------------------------------*/
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|
|
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/*
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* Unlike other ports pxPortInitialiseStack() is written in assembly code as it
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* needs access to the portasmADDITIONAL_CONTEXT_SIZE constant. The prototype
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|
* for the function is as per the other ports:
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|
* StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters );
|
|
*
|
|
* As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in
|
|
* a1, and pvParameters in a2. The new top of stack is passed out in a0.
|
|
*
|
|
* RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
|
|
* for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
|
|
*
|
|
* Register ABI Name Description Saver
|
|
* x0 zero Hard-wired zero -
|
|
* x1 ra Return address Caller
|
|
* x2 sp Stack pointer Callee
|
|
* x3 gp Global pointer -
|
|
* x4 tp Thread pointer -
|
|
* x5-7 t0-2 Temporaries Caller
|
|
* x8 s0/fp Saved register/Frame pointer Callee
|
|
* x9 s1 Saved register Callee
|
|
* x10-11 a0-1 Function Arguments/return values Caller
|
|
* x12-17 a2-7 Function arguments Caller
|
|
* x18-27 s2-11 Saved registers Callee
|
|
* x28-31 t3-6 Temporaries Caller
|
|
*
|
|
* The RISC-V context is saved t FreeRTOS tasks in the following stack frame,
|
|
* where the global and thread pointers are currently assumed to be constant so
|
|
* are not saved:
|
|
*
|
|
* mstatus
|
|
* x31
|
|
* x30
|
|
* x29
|
|
* x28
|
|
* x27
|
|
* x26
|
|
* x25
|
|
* x24
|
|
* x23
|
|
* x22
|
|
* x21
|
|
* x20
|
|
* x19
|
|
* x18
|
|
* x17
|
|
* x16
|
|
* x15
|
|
* x14
|
|
* x13
|
|
* x12
|
|
* x11
|
|
* pvParameters
|
|
* x9
|
|
* x8
|
|
* x7
|
|
* x6
|
|
* x5
|
|
* portTASK_RETURN_ADDRESS
|
|
* [chip specific registers go here]
|
|
* pxCode
|
|
*/
|
|
.align 8
|
|
.func
|
|
pxPortInitialiseStack:
|
|
#if defined(__riscv_d) || defined(__riscv_f)
|
|
addi t0, x0, FLOAT_REG_NUM /* The number of float registers. */
|
|
chip_float_stack_frame: /* First add any float registers to the stack frame being created. */
|
|
beq t0, x0, 1f /* No more float registers to save. */
|
|
addi a0, a0, -portFWORD_SIZE /* Make space for float register. */
|
|
store_f f0, 0(a0) /* Give the float register an initial value of zero. */
|
|
addi t0, t0, -1 /* Decrement the count of float registers remaining. */
|
|
j chip_float_stack_frame /* Until no more float registers. */
|
|
1:
|
|
#endif
|
|
|
|
#if defined(__riscv_p)
|
|
csrr t0, vxsat
|
|
addi a0, a0, -portWORD_SIZE
|
|
store_x t0, 0(a0) /* vxsat onto the stack. */
|
|
#endif
|
|
|
|
csrr t0, mstatus /* Obtain current mstatus value. */
|
|
andi t0, t0, ~0x8 /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the schedulre has been started, otherwise interrupts would be disabled anyway. */
|
|
addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
|
|
slli t1, t1, 4
|
|
or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */
|
|
|
|
addi a0, a0, -portWORD_SIZE
|
|
store_x t0, 0(a0) /* mstatus onto the stack. */
|
|
addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x11-x31. */
|
|
store_x a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
|
|
addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9. */
|
|
store_x x0, 0(a0) /* Return address onto the stack, could be portTASK_RETURN_ADDRESS */
|
|
|
|
addi a0, a0, -portWORD_SIZE
|
|
store_x a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */
|
|
ret
|
|
.endfunc
|
|
/*-----------------------------------------------------------*/
|