mirror of
https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
synced 2025-12-14 10:28:54 +00:00
453 lines
14 KiB
C
453 lines
14 KiB
C
/*
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* Copyright (c) 2022, Artinchip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <rtconfig.h>
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#include <stdbool.h>
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#include <string.h>
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#include <stdint.h>
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#include <aic_common.h>
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#include <aic_core.h>
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#include <aic_hal.h>
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#include <hal_dma.h>
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#include <hal_qspi.h>
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#include "qspi_internal.h"
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#ifdef AIC_QSPI_DRV_V11
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#include "qspi_hw_v1.1.h"
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int hal_qspi_slave_init(qspi_slave_handle *h, struct qspi_slave_config *cfg)
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{
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struct qspi_slave_state *qspi;
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u32 base, sclk;
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int ret;
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CHECK_PARAM(h, -EINVAL);
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CHECK_PARAM(cfg, -EINVAL);
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qspi = (struct qspi_slave_state *)h;
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base = qspi_hw_index_to_base(cfg->idx);
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if (base == QSPI_INVALID_BASE) {
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hal_log_err("invalid spi controller index %d\n", cfg->idx);
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return -ENODEV;
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}
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sclk = cfg->clk_in_hz;
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if (sclk > HAL_QSPI_MAX_FREQ_HZ)
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sclk = HAL_QSPI_MAX_FREQ_HZ;
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else if (sclk < HAL_QSPI_MIN_FREQ_HZ)
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sclk = HAL_QSPI_MIN_FREQ_HZ;
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qspi->idx = cfg->idx;
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show_freq("freq (input)", qspi->idx, sclk);
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hal_clk_set_freq(cfg->clk_id, sclk);
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ret = hal_clk_enable(cfg->clk_id);
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if (ret < 0) {
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hal_log_err("QSPI %d clk enable failed!\n", cfg->idx);
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return -EFAULT;
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}
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ret = hal_clk_enable_deassertrst(cfg->clk_id);
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if (ret < 0) {
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hal_log_err("QSPI %d reset deassert failed!\n", cfg->idx);
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return -EFAULT;
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}
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qspi_hw_init_default(base);
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qspi_hw_set_ctrl_mode(base, QSPI_CTRL_MODE_SLAVE);
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qspi_hw_interrupt_disable(base, ICR_BIT_ALL_MSK);
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qspi_hw_set_cpol(base, cfg->cpol);
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qspi_hw_set_cpha(base, cfg->cpha);
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qspi_hw_set_lsb_en(base, cfg->lsb_en);
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qspi_hw_set_cs_polarity(base, cfg->cs_polarity);
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if (cfg->cs_polarity == QSPI_CS_POL_VALID_LOW)
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qspi_hw_set_cs_level(base, QSPI_CS_LEVEL_HIGH);
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else
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qspi_hw_set_cs_level(base, QSPI_CS_LEVEL_LOW);
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if (cfg->cs_auto)
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qspi_hw_set_cs_owner(base, QSPI_CS_CTL_BY_HW);
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else
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qspi_hw_set_cs_owner(base, QSPI_CS_CTL_BY_SW);
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qspi_hw_drop_invalid_data(base, QSPI_DROP_INVALID_DATA);
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qspi_hw_reset_fifo(base);
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qspi_hw_set_fifo_watermark(base, QSPI_TX_WATERMARK, QSPI_RX_WATERMARK);
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qspi->clk_id = cfg->clk_id;
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qspi->cb = NULL;
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qspi->cb_priv = NULL;
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return 0;
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}
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void hal_qspi_slave_fifo_reset(qspi_slave_handle *h, u32 fifo)
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{
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struct qspi_slave_state *qspi;
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u32 base;
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CHECK_PARAM_RET(h);
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qspi = (struct qspi_slave_state *)h;
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base = qspi_hw_index_to_base(qspi->idx);
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hal_qspi_fifo_reset(base, fifo);
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}
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int hal_qspi_slave_deinit(qspi_slave_handle *h)
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{
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struct qspi_slave_state *qspi;
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CHECK_PARAM(h, -EINVAL);
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qspi = (struct qspi_slave_state *)h;
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qspi->cb = NULL;
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qspi->cb_priv = NULL;
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qspi->async_tx = NULL;
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qspi->async_rx = NULL;
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qspi->async_tx_remain = 0;
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qspi->async_rx_remain = 0;
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return 0;
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}
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int hal_qspi_slave_set_bus_width(qspi_slave_handle *h, u32 bus_width)
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{
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struct qspi_slave_state *qspi;
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u32 base;
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CHECK_PARAM(h, -EINVAL);
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qspi = (struct qspi_slave_state *)h;
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base = qspi_hw_index_to_base(qspi->idx);
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qspi_hw_set_bus_width(base, bus_width);
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qspi->bus_width = bus_width;
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if (qspi->bus_width == 0)
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qspi->bus_width = QSPI_BUS_WIDTH_SINGLE;
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return 0;
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}
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int hal_qspi_slave_register_cb(qspi_slave_handle *h, qspi_slave_async_cb cb, void *priv)
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{
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struct qspi_slave_state *qspi;
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CHECK_PARAM(h, -EINVAL);
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CHECK_PARAM(cb, -EINVAL);
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qspi = (struct qspi_slave_state *)h;
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qspi->cb = cb;
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qspi->cb_priv = priv;
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return 0;
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}
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int hal_qspi_slave_get_status(qspi_slave_handle *h)
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{
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struct qspi_slave_state *qspi;
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CHECK_PARAM(h, -EINVAL);
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qspi = (struct qspi_slave_state *)h;
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return (qspi->status) & (~HAL_QSPI_STATUS_INTERNAL_MSK);
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}
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void hal_qspi_show_ists(u32 id, u32 sts)
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{
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if (sts) {
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printf("QSPI%d:\n", id);
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}
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if (sts & ISTS_BIT_RF_RDY)
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printf(" ISTS_BIT_RF_RDY\n");
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if (sts & ISTS_BIT_RF_EMP)
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printf(" ISTS_BIT_RF_EMP\n");
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if (sts & ISTS_BIT_RF_FUL)
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printf(" ISTS_BIT_RF_FUL\n");
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if (sts & ISTS_BIT_TF_RDY)
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printf(" ISTS_BIT_TF_RDY\n");
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if (sts & ISTS_BIT_TF_EMP)
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printf(" ISTS_BIT_TF_EMP\n");
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if (sts & ISTS_BIT_TF_FUL)
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printf(" ISTS_BIT_TF_FUL\n");
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if (sts & ISTS_BIT_RF_OVF)
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printf(" ISTS_BIT_RF_OVF\n");
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if (sts & ISTS_BIT_RF_UDR)
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printf(" ISTS_BIT_RF_UDR\n");
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if (sts & ISTS_BIT_TF_OVF)
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printf(" ISTS_BIT_TF_OVF\n");
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if (sts & ISTS_BIT_TF_UDR)
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printf(" ISTS_BIT_TF_UDR\n");
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if (sts & ISTS_BIT_CS_INV)
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printf(" ISTS_BIT_CS_INV\n");
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if (sts & ISTS_BIT_TDONE)
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printf(" ISTS_BIT_TDONE\n");
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}
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void hal_qspi_slave_irq_handler(qspi_slave_handle *h)
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{
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struct qspi_slave_state *qspi;
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u32 base, sts, imsk;
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CHECK_PARAM_RET(h);
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qspi = (struct qspi_slave_state *)h;
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base = qspi_hw_index_to_base(qspi->idx);
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qspi_hw_get_interrupt_status(base, &sts);
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if (sts & ISTS_BIT_TF_OVF)
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qspi->status |= HAL_QSPI_STATUS_TX_OVER_FLOW;
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if ((sts & ISTS_BIT_TF_EMP) || (sts & ISTS_BIT_TF_RDY)) {
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u32 dolen, free_len;
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if ((qspi->work_mode == QSPI_WORK_MODE_ASYNC_TX_CPU) &&
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qspi->async_tx) {
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u32 total;
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free_len = QSPI_FIFO_DEPTH - qspi_hw_get_tx_fifo_cnt(base);
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if (qspi->async_tx_remain) {
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dolen = min(free_len, qspi->async_tx_remain);
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qspi_hw_write_fifo(base, qspi->async_tx, dolen);
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qspi->async_tx += dolen;
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qspi->async_tx_wcnt += dolen;
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qspi->async_tx_remain -= dolen;
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} else {
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imsk = ISTS_BIT_TF_EMP | ISTS_BIT_TF_RDY;
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qspi_hw_interrupt_disable(base, imsk);
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}
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total = qspi->async_tx_remain + qspi->async_tx_wcnt;
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qspi->async_tx_count = total - qspi_hw_get_tx_fifo_cnt(base);
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}
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}
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if (sts & ISTS_BIT_RF_UDR)
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qspi->status |= HAL_QSPI_STATUS_RX_UNDER_RUN;
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if (sts & ISTS_BIT_RF_OVF)
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qspi->status |= HAL_QSPI_STATUS_RX_OVER_FLOW;
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if ((sts & ISTS_BIT_RF_FUL) || (sts & ISTS_BIT_RF_RDY) || (sts & ISTS_BIT_TDONE)) {
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u32 dolen;
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if ((qspi->work_mode == QSPI_WORK_MODE_ASYNC_RX_CPU) && qspi->async_rx &&
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qspi->async_rx_remain) {
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dolen = qspi_hw_get_rx_fifo_cnt(base);
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if (dolen > qspi->async_rx_remain)
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dolen = qspi->async_rx_remain;
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qspi_hw_read_fifo(base, qspi->async_rx, dolen);
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qspi->async_rx += dolen;
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qspi->async_rx_count += dolen;
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qspi->async_rx_remain -= dolen;
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}
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}
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if ((sts & ISTS_BIT_TF_EMP) && (sts & ISTS_BIT_TDONE)) {
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/* Write 4 bytes 0 to clear TX Buffer,
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* Note:
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* Every time user send new data, please reset TX FIFO
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*/
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u32 zeros = 0;
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qspi_hw_write_fifo(base, (void *)&zeros, 4);
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}
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if (sts & ISTS_BIT_TDONE) {
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if (qspi->status == HAL_QSPI_STATUS_IN_PROGRESS)
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qspi->status = HAL_QSPI_STATUS_OK;
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else
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qspi->status &= ~HAL_QSPI_STATUS_IN_PROGRESS;
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imsk = ICR_BIT_ALL_MSK;
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imsk &= ~ICR_BIT_TDONE_INTE;
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imsk &= ~ICR_BIT_CS_INV_INTE;
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qspi_hw_interrupt_disable(base, imsk);
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qspi->status |= HAL_QSPI_STATUS_ASYNC_TDONE;
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if (QSPI_IS_ASYNC_ALL_DONE(qspi->status, qspi->done_mask)) {
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if (qspi->work_mode == QSPI_WORK_MODE_ASYNC_RX_DMA) {
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qspi->async_rx_count =
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qspi->async_rx_remain - qspi_hw_get_idma_rx_len(base);
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aicos_dcache_invalid_range(qspi->async_rx, qspi->async_rx_count);
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}
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if (qspi->work_mode == QSPI_WORK_MODE_ASYNC_TX_DMA) {
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qspi->async_tx_count =
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qspi->async_tx_remain - qspi_hw_get_tx_fifo_cnt(base);
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}
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if (qspi->cb)
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qspi->cb(h, qspi->cb_priv);
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}
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}
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qspi_hw_clear_interrupt_status(base, sts);
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}
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int qspi_slave_transfer_cpu_async(struct qspi_slave_state *qspi,
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struct qspi_transfer *t)
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{
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u32 base, txlen, rxlen;
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int ret = 0;
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base = qspi_hw_index_to_base(qspi->idx);
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if ((t->tx_data == NULL) && (t->rx_data == NULL))
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return -EINVAL;
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if (t->data_len == 0)
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return -EINVAL;
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qspi_hw_interrupt_disable(base, ICR_BIT_ALL_MSK);
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qspi->status = HAL_QSPI_STATUS_IN_PROGRESS;
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if (t->tx_data) {
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txlen = t->data_len;
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qspi->work_mode = QSPI_WORK_MODE_ASYNC_TX_CPU;
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qspi->done_mask = HAL_QSPI_STATUS_ASYNC_TDONE;
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qspi->async_rx = NULL;
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qspi->async_rx_count = 0;
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qspi->async_rx_remain = 0;
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qspi->async_tx = t->tx_data;
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qspi->async_tx_count = 0;
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qspi->async_tx_wcnt = 0;
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qspi->async_tx_remain = txlen;
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if (qspi->bus_width > 1)
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qspi_hw_set_slave_output_en(base, 1);
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else
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qspi_hw_set_slave_output_en(base, 0);
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qspi_hw_interrupt_enable(base, ICR_BIT_ERRS | ICR_BIT_TDONE_INTE |
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ISTS_BIT_TF_RDY | ISTS_BIT_TF_EMP |
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ICR_BIT_CS_INV_INTE);
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qspi_hw_clear_interrupt_status(base, ISTS_BIT_ALL_MSK);
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} else if (t->rx_data) {
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rxlen = t->data_len;
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qspi->work_mode = QSPI_WORK_MODE_ASYNC_RX_CPU;
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qspi->done_mask = HAL_QSPI_STATUS_ASYNC_TDONE;
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qspi->async_tx = NULL;
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qspi->async_tx_count = 0;
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qspi->async_tx_remain = 0;
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qspi->async_rx = t->rx_data;
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qspi->async_rx_count = 0;
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qspi->async_rx_remain = rxlen;
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qspi_hw_set_slave_output_en(base, 0);
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qspi_hw_interrupt_enable(base, ICR_BIT_ERRS | ICR_BIT_TDONE_INTE |
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ICR_BIT_CS_INV_INTE);
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qspi_hw_clear_interrupt_status(base, ISTS_BIT_ALL_MSK);
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}
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return ret;
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}
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static int qspi_slave_transfer_dma_async(struct qspi_slave_state *qspi, struct qspi_transfer *t)
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{
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u32 base, txlen, rxlen, imsk;
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int ret = 0;
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base = qspi_hw_index_to_base(qspi->idx);
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if ((t->tx_data == NULL) && (t->rx_data == NULL))
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return -EINVAL;
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if (t->data_len == 0)
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return -EINVAL;
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qspi_hw_set_idma_busrt_auto_len_en(base, 1);
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qspi_hw_interrupt_disable(base, ICR_BIT_ALL_MSK);
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qspi->status = HAL_QSPI_STATUS_IN_PROGRESS;
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if (t->tx_data) {
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qspi->work_mode = QSPI_WORK_MODE_ASYNC_TX_DMA;
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qspi->done_mask = HAL_QSPI_STATUS_ASYNC_TDONE;
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txlen = t->data_len;
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qspi->async_tx_remain = txlen;
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qspi->async_tx = t->tx_data;
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aicos_dcache_clean_range(qspi->async_tx, txlen);
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if (qspi->bus_width > 1)
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qspi_hw_set_slave_output_en(base, 1);
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qspi_hw_set_idma_tx_addr(base, (u32)t->tx_data);
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qspi_hw_set_idma_tx_len(base, (u32)txlen);
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qspi_hw_set_idma_tx_en(base, 1);
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qspi_hw_interrupt_enable(base, ICR_BIT_IDMA_MSK | ICR_BIT_CS_INV_INTE);
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} else if (t->rx_data) {
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qspi->work_mode = QSPI_WORK_MODE_ASYNC_RX_DMA;
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qspi->done_mask = HAL_QSPI_STATUS_ASYNC_TDONE;
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rxlen = t->data_len;
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qspi->async_rx_remain = rxlen;
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qspi->async_rx = t->rx_data;
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qspi_hw_set_slave_output_en(base, 0);
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qspi_hw_set_idma_rx_addr(base, (u32)t->rx_data);
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qspi_hw_set_idma_rx_len(base, (u32)rxlen);
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qspi_hw_set_idma_rx_en(base, 1);
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imsk = ICR_BIT_IDMA_MSK | ICR_BIT_CS_INV_INTE;
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imsk &= ~ISTS_BIT_TF_UDR;
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qspi_hw_interrupt_enable(base, imsk);
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}
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qspi_hw_clear_interrupt_status(base, ISTS_BIT_ALL_MSK);
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return ret;
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}
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static int qspi_slave_can_dma(struct qspi_slave_state *qspi, struct qspi_transfer *t)
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{
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#ifdef AIC_DMA_DRV
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if (t->tx_data) {
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/* Meet DMA's address align requirement */
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if (((unsigned long)t->tx_data) & (AIC_DMA_ALIGN_SIZE - 1))
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return 0;
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}
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if (t->rx_data) {
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/* RX: date length require 4 bytes alignment */
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if (t->data_len & 0x3)
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return 0;
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/* Meet DMA's address align requirement */
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if (((unsigned long)t->rx_data) & (AIC_DMA_ALIGN_SIZE - 1))
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return 0;
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}
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return 1;
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#else
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return 0;
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#endif
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}
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int hal_qspi_slave_transfer_async(qspi_slave_handle *h, struct qspi_transfer *t)
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{
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struct qspi_slave_state *qspi;
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CHECK_PARAM(h, -EINVAL);
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CHECK_PARAM(t, -EINVAL);
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qspi = (struct qspi_slave_state *)h;
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if (qspi_slave_can_dma(qspi, t))
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return qspi_slave_transfer_dma_async(qspi, t);
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return qspi_slave_transfer_cpu_async(qspi, t);
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}
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int hal_qspi_slave_transfer_abort(qspi_slave_handle *h)
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{
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struct qspi_slave_state *qspi;
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u32 base;
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qspi = (struct qspi_slave_state *)h;
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base = qspi_hw_index_to_base(qspi->idx);
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if (qspi->work_mode == QSPI_WORK_MODE_ASYNC_RX_CPU) {
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qspi_hw_clear_interrupt_status(base, ISTS_BIT_ALL_MSK);
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qspi_hw_interrupt_disable(base, ICR_BIT_ALL_MSK);
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}
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if (qspi->work_mode == QSPI_WORK_MODE_ASYNC_TX_CPU) {
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qspi_hw_clear_interrupt_status(base, ISTS_BIT_ALL_MSK);
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qspi_hw_interrupt_disable(base, ICR_BIT_ALL_MSK);
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}
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if (qspi->work_mode == QSPI_WORK_MODE_ASYNC_RX_DMA) {
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qspi_hw_clear_interrupt_status(base, ISTS_BIT_ALL_MSK);
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qspi_hw_interrupt_disable(base, ICR_BIT_ALL_MSK);
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qspi_hw_set_idma_rx_en(base, 0);
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qspi_hw_set_idma_rx_len(base, 0);
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}
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if (qspi->work_mode == QSPI_WORK_MODE_ASYNC_TX_DMA) {
|
|
qspi_hw_clear_interrupt_status(base, ISTS_BIT_ALL_MSK);
|
|
qspi_hw_interrupt_disable(base, ICR_BIT_ALL_MSK);
|
|
qspi_hw_set_idma_tx_en(base, 0);
|
|
qspi_hw_set_idma_tx_len(base, 0);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int hal_qspi_slave_transfer_count(qspi_slave_handle *h)
|
|
{
|
|
struct qspi_slave_state *qspi;
|
|
|
|
qspi = (struct qspi_slave_state *)h;
|
|
if ((qspi->work_mode == QSPI_WORK_MODE_ASYNC_RX_CPU) ||
|
|
(qspi->work_mode == QSPI_WORK_MODE_ASYNC_RX_DMA)) {
|
|
return qspi->async_rx_count;
|
|
}
|
|
if ((qspi->work_mode == QSPI_WORK_MODE_ASYNC_TX_CPU) ||
|
|
(qspi->work_mode == QSPI_WORK_MODE_ASYNC_TX_DMA)) {
|
|
return qspi->async_tx_count;
|
|
}
|
|
return -1;
|
|
}
|
|
|
|
#endif
|