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<div class=" wh_topic_content body "><main role="main"><article class="- topic/topic topic" role="article" aria-labelledby="ariaid-title1"><span class="edit-link" style="font-size:12px; opacity:0.6; text-align:right; vertical-align:middle"><a target="_blank" href="http://172.16.35.88/tasks/jdssno1uvvbf2mltu9kb9v3if05d5gopuakboe8hlud18rma/edit/F:/aicdita/aicdita-cn/topics/sdk/cmu/cmu-design-guide-lite.dita">Edit online</a></span><h1 class="- topic/title title topictitle1" id="ariaid-title1">设计说明</h1><div class="date inPage">15 Jan 2024</div><div style="color: gray;">
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Read time: 1 minute(s)
|
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</div><div class="- topic/body body"><section class="- topic/section section" id="id__section_ul3_k44_mdc" data-ofbid="id__section_ul3_k44_mdc"><h2 class="- topic/title title sectiontitle">源码说明</h2>
|
||
|
||
<div class="- topic/p p" data-ofbid="d172899e24__20250121171622">CMU 相关 <span class="+ topic/ph sw-d/filepath ph filepath">.c</span> 和 <span class="+ topic/ph sw-d/filepath ph filepath">.h</span> 文件分别位于
|
||
<span class="+ topic/ph sw-d/filepath ph filepath">luban-lite\bsp\artinchip\hal\cmu</span> 和
|
||
<span class="+ topic/ph sw-d/filepath ph filepath">luban-lite\bsp\artinchip\include\hal</span> 目录。主要源文件说明如下：<div class="table-container"><table class="- topic/table table frame-all" id="id__table_kkq_yhd_bdc" data-ofbid="id__table_kkq_yhd_bdc" data-cols="2"><caption></caption><colgroup><col style="width:42.19409282700421%"/><col style="width:57.80590717299579%"/></colgroup><thead class="- topic/thead thead"><tr class="- topic/row"><th class="- topic/entry entry colsep-1 rowsep-1" id="id__table_kkq_yhd_bdc__entry__1">文件</th><th class="- topic/entry entry colsep-0 rowsep-1" id="id__table_kkq_yhd_bdc__entry__2">说明</th></tr></thead><tbody class="- topic/tbody tbody"><tr class="- topic/row"><td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><span class="+ topic/ph sw-d/filepath ph filepath">aic_clk_id.h</span></td><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2">时钟 ID 以及 寄存器设置</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_clk.h</span></td><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2">hal 层 clk api 的头文件</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_clk.c</span></td><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2">hal 层 clk api 的实现</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_reset.h</span></td><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2">hal 层 reset api 的头文件</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_reset.c</span></td><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2">hal 层 reset api 的实现</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_pll_clk.c</span></td><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2">PLL 时钟的具体实现</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_fixed_rate_clk.c</span></td><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2">固定频率时钟的具体实现</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_fixed_parent_clk.c</span></td><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2">单个父时钟的时钟的具体实现</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_multi_parent_clk.c</span></td><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2">多个父时钟的时钟的具体实现</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_disp_clk.c</span></td><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2">DISP 时钟的具体实现</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_fpga_clk_def_v10.</span>c</td><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2">CMU V1.0 的 Clock 配置</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_fpga_clk_def_v11.c</span></td><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2">CMU V1.1 的 Clock 配置</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_fpga_clk_def_v12.c</span></td><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2">CMU V1.2 的 Clock 配置</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_reset_def_v10.c</span></td><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2">CMU V1.0 的 Reset 配置</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_reset_def_v11.c</span></td><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2">CMU V1.1 的 Reset 配置</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-1 rowsep-0" headers="id__table_kkq_yhd_bdc__entry__1"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_reset_def_v12.c</span></td><td class="- topic/entry entry colsep-0 rowsep-0" headers="id__table_kkq_yhd_bdc__entry__2">CMU V1.2 的 Reset 配置 </td></tr></tbody></table></div></div>
|
||
</section><section xml:lang="zh-CN" lang="zh-CN" class="- topic/section section" id="id__id3" data-ofbid="id__id3"><h2 class="- topic/title title sectiontitle">Clock
|
||
和 Reset 类型</h2>
|
||
|
||
<figure class="- topic/fig fig fignone" data-ofbid="d172899e155__20250121171622"><br/><div class="imagecenter"><img class="- topic/image image imagecenter" id="id__image_lkq_yhd_bdc" src="../../../images/cmu/cmu_sw_system.png" alt="sw_system10"/></div><br/></figure>
|
||
<div class="- topic/p p" data-ofbid="d172899e160__20250121171622">CMU
|
||
驱动的逻辑相对简单，目前只在
|
||
HAL 层提供了 Clock 和 Reset 的 API 接口。RTOS 驱动和 Baremetal 驱动都可以直接使用。
|
||
<div class="- topic/note note note note_note" id="id__note_ocn_5mx_bdc" data-ofbid="id__note_ocn_5mx_bdc"><span class="note__title">注：</span> 相对时钟树来说，仅终端模块才有 Reset 控制的需求。在下列时钟树中，仅 <span class="+ topic/keyword pr-d/parmname keyword parmname">fixed parent
|
||
clock</span> 同时拥有 Reset 功能。</div></div>
|
||
</section><section class="- topic/section section" id="id__section_itz_c44_mdc" data-ofbid="id__section_itz_c44_mdc"><h2 class="- topic/title title sectiontitle">时钟树</h2>
|
||
|
||
<div class="- topic/div div section">
|
||
<figure class="- topic/fig fig fignone" id="id__fig_rxf_3l4_mdc" data-ofbid="id__fig_rxf_3l4_mdc"><br/><div class="imagecenter"><img class="- topic/image image imagecenter" id="id__image_sxf_3l4_mdc" src="../../../reusables/reused-topics/../../images/cmu/cmu_clock_structure_tree.png" alt="clock_tree"/></div><br/><figcaption data-caption-side="bottom" class="- topic/title title figcapcenter"><span class="figtitleprefix fig--title-label">图<span class="fig--title-label-number"> 1</span><span class="fig--title-label-punctuation">. </span></span><span class="fig--title">时钟树</span></figcaption></figure>
|
||
<div class="- topic/p p" id="id__p_five_type_clock" data-ofbid="id__p_five_type_clock">CMU 驱动将时钟树中的时钟分为五种类型，每种类型的时钟具有不同的特性和功能：<ul class="- topic/ul ul simple" id="id__ul_nkq_yhd_bdc" data-ofbid="id__ul_nkq_yhd_bdc"><li class="- topic/li li" data-ofbid="d172899e185__20250121171622">
|
||
<p class="- topic/p p" data-ofbid="d172899e187__20250121171622"><span class="+ topic/keyword pr-d/parmname keyword parmname">fixed rate
|
||
clock</span>：具有固定的输出频率，通常用于驱动一些不需要动态调整频率的外设。时钟频率固定，不能调节频率，不能打开或关闭。固定频率时钟包括
|
||
OSC24M、RC1M 和 OSC32K。</p>
|
||
</li><li class="- topic/li li" data-ofbid="d172899e192__20250121171622">
|
||
<p class="- topic/p p" data-ofbid="d172899e194__20250121171622"><span class="+ topic/keyword pr-d/parmname keyword parmname">fixed parent module
|
||
clock</span>：从另一个时钟信号派生出来的时钟，其输出频率与父时钟信号的频率相同。该类型时钟可以实现只有一个父时钟源的时钟驱动，主要用于各个外设模块的时钟驱动。该类型时钟可以改变时钟频率，打开或关闭时钟，获取父时钟源参数，但不能设置或改变父时钟源。</p>
|
||
</li><li class="- topic/li li" data-ofbid="d172899e199__20250121171622">
|
||
<p class="- topic/p p" data-ofbid="d172899e201__20250121171622"><span class="+ topic/keyword pr-d/parmname keyword parmname">multiple parent module clock</span>：可以从多个父时钟源中选择其中一个作为其输入，并根据需要调整输出频率。
|
||
该类型时钟可以实现有多个父时钟源的时钟驱动，主要用于各种总线时钟驱动，可以打开或关闭时钟，调节频率，获取或改变父时钟源。</p>
|
||
</li><li class="- topic/li li" data-ofbid="d172899e206__20250121171622">
|
||
<p class="- topic/p p" data-ofbid="d172899e208__20250121171622"><span class="+ topic/keyword pr-d/parmname keyword parmname">display module clock：</span>
|
||
实现了几个与显示模块相关的时钟驱动，除了自身的模块时钟外，显示模块还有一个像素时钟，相应的底层寄存器的设计也不同，所以显示相关的几个时钟重新设计了底层驱动。</p>
|
||
</li><li class="- topic/li li" data-ofbid="d172899e213__20250121171622">
|
||
<p class="- topic/p p" data-ofbid="d172899e215__20250121171622"><span class="+ topic/keyword pr-d/parmname keyword parmname">pll clock</span>：实现了 CMU 的 PLL 时钟驱动。PLL 是一种能够产生高频时钟信号的电路。PLL
|
||
可以将一个低频率的参考时钟信号乘以一个整数倍的频率因子，从而得到一个高频率的时钟信号。</p>
|
||
</li></ul></div>
|
||
<div class="- topic/p p" data-ofbid="d172899e221__20250121171622">下列表格列出了各种时钟分类对应的时钟树：<div class="table-container"><table class="- topic/table table colwidths-given docutils align-default frame-all" id="id__table_txf_3l4_mdc" data-ofbid="id__table_txf_3l4_mdc" data-cols="2"><caption></caption><colgroup><col style="width:41.32231404958678%"/><col style="width:58.67768595041321%"/></colgroup><thead class="- topic/thead thead"><tr class="- topic/row"><th class="- topic/entry entry colsep-1 rowsep-1" id="id__table_txf_3l4_mdc__entry__1">类型</th><th class="- topic/entry entry colsep-0 rowsep-1" id="id__table_txf_3l4_mdc__entry__2">时钟</th></tr></thead><tbody class="- topic/tbody tbody"><tr class="- topic/row"><td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_txf_3l4_mdc__entry__1" rowspan="3">fixed rate clock</td><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">OSC24M</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">OSC32K</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">RC1M</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_txf_3l4_mdc__entry__1" rowspan="31">fixed parent clock</td><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_DMA</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_CE</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_USBD</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_USBH0-1</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_USB_PHY0-1</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_GMAC0-1</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_SPI0-1</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_SDMMC0-2</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_SYSCON</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_RTC</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_I2S0-1</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_ADDA</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_DE</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_GE</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_VE</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_WDOG</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_SID</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_GTC</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_GPIO</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_UART0-7</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_I2C0-3</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_CAN0-1</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_PWM</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_ADCIM</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_GPADC</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_RTP</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_TSEN</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_CIR</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_RGB</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_LVDS</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_MIPIDSI</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_txf_3l4_mdc__entry__1" rowspan="9">multi parent clock</td><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_CPU</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_AHB0</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_APB0</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_APB1</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_AXI0</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_OUT0</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_OUT1</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_OUT2</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_OUT3</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_txf_3l4_mdc__entry__1" rowspan="5">pll clock</td><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_PLL_INT0</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_PLL_INT1</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_PLL_FRA0</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_PLL_FRA1</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_PLL_FRA2</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-1 rowsep-0" headers="id__table_txf_3l4_mdc__entry__1" rowspan="2">disp clock</td><td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2">CLK_PIX</td></tr><tr class="- topic/row"><td class="- topic/entry entry colsep-0 rowsep-0" headers="id__table_txf_3l4_mdc__entry__2">CLK_SCLK</td></tr></tbody></table></div></div>
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