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<div class=" wh_topic_content body "><main role="main"><article class="- topic/topic concept/concept topic concept" role="article" aria-labelledby="ariaid-title1"><span class="edit-link" style="font-size:12px; opacity:0.6; text-align:right; vertical-align:middle"><a target="_blank" href="http://172.16.35.88/tasks/jdssno1uvvbf2mltu9kb9v3if05d5gopuakboe8hlud18rma/edit/F:/aicdita/aicdita-cn/topics/sdk/dvp/dvp_data_struct.dita">Edit online</a></span><h1 class="- topic/title title topictitle1" id="ariaid-title1">数据结构设计</h1><div class="date inPage">2 Dec 2024</div><div style="color: gray;">
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Read time: 3 minute(s)
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</div><div class="- topic/body concept/conbody body conbody"><div class="- topic/p p" data-ofbid="d228403e22__20250121171649">DVP 自定义的数据结构都在 <span class="+ topic/ph sw-d/filepath ph filepath">aic_dvp.h</span> 中。<ul class="- topic/ul ul" id="dvp_data_structure__ul_wjp_2dh_d1c" data-ofbid="dvp_data_structure__ul_wjp_2dh_d1c"><li class="- topic/li li" data-ofbid="d228403e28__20250121171649">struct aic_dvp：定义了 DVP
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控制器的设备管理信息：<pre class="+ topic/pre pr-d/codeblock pre codeblock language-c" id="dvp_data_structure__codeblock_pgx_fdh_d1c" data-ofbid="dvp_data_structure__codeblock_pgx_fdh_d1c"><strong class="hl-keyword">struct</strong> aic_dvp {
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<em class="hl-comment">/* Device resources */</em>
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<strong class="hl-keyword">struct</strong> device *dev;
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<strong class="hl-keyword">void</strong> __iomem *regs;
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<strong class="hl-keyword">struct</strong> clk *clk;
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<strong class="hl-keyword">struct</strong> reset_control *rst;
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u32 clk_rate;
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<strong class="hl-keyword">int</strong> irq;
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<strong class="hl-keyword">int</strong> ch;
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<strong class="hl-keyword">struct</strong> vb2_v4l2_buffer *vbuf[DVP_MAX_BUF];
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<strong class="hl-keyword">struct</strong> aic_dvp_config cfg; <em class="hl-comment">/* The configuration of DVP HW */</em>
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<strong class="hl-keyword">struct</strong> v4l2_fwnode_bus_parallel bus; <em class="hl-comment">/* The format of input data */</em>
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<strong class="hl-keyword">struct</strong> v4l2_pix_format_mplane fmt; <em class="hl-comment">/* The format of output data */</em>
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<em class="hl-comment">/* Main Device */</em>
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<strong class="hl-keyword">struct</strong> v4l2_device v4l2;
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<strong class="hl-keyword">struct</strong> media_device mdev;
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<strong class="hl-keyword">struct</strong> video_device vdev;
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<strong class="hl-keyword">struct</strong> media_pad vdev_pad;
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<em class="hl-comment">/* Local subdev */</em>
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<strong class="hl-keyword">struct</strong> v4l2_subdev subdev;
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<strong class="hl-keyword">struct</strong> media_pad subdev_pads[DVP_SUBDEV_PAD_NUM];
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<strong class="hl-keyword">struct</strong> v4l2_mbus_framefmt subdev_fmt;
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<em class="hl-comment">/* V4L2 Async variables */</em>
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<strong class="hl-keyword">struct</strong> v4l2_async_subdev asd;
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<strong class="hl-keyword">struct</strong> v4l2_async_notifier notifier;
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<strong class="hl-keyword">struct</strong> v4l2_subdev *src_subdev;
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<strong class="hl-keyword">int</strong> src_pad;
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<em class="hl-comment">/* V4L2 variables */</em>
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<strong class="hl-keyword">struct</strong> mutex lock;
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<em class="hl-comment">/* Videobuf2 */</em>
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<strong class="hl-keyword">struct</strong> vb2_queue queue;
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<strong class="hl-keyword">struct</strong> list_head buf_list;
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spinlock_t qlock;
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<strong class="hl-keyword">unsigned</strong> <strong class="hl-keyword">int</strong> sequence;
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};</pre></li><li class="- topic/li li" data-ofbid="d228403e32__20250121171649">struct aic_dvp_config：定义了 V4L2 媒体数据的配置信息：<pre class="+ topic/pre pr-d/codeblock pre codeblock language-c" id="dvp_data_structure__codeblock_n1b_gdh_d1c" data-ofbid="dvp_data_structure__codeblock_n1b_gdh_d1c"><span class="hl-tag-doctype-comment">/**
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* Save the configuration information for DVP controller.</span><span class="- topic/ph ph">
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* @code: media bus format code (MEDIA_BUS_FMT_*, in media-bus-format.h)
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* @field: used interlacing type (<strong class="hl-keyword">enum</strong> v4l2_field)
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* @width: frame width
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* @height: frame height
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*/</span>
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<strong class="hl-keyword">struct</strong> aic_dvp_config {
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<em class="hl-comment">/* Input format */</em>
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<strong class="hl-keyword">enum</strong> dvp_input input;
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<strong class="hl-keyword">enum</strong> dvp_input_yuv_seq input_seq;
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<strong class="hl-keyword">enum</strong> v4l2_field field;
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<em class="hl-comment">/* Output format */</em>
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<strong class="hl-keyword">enum</strong> dvp_output output;
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u32 width;
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u32 height;
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u32 stride[DVP_MAX_PLANE];
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u32 sizeimage[DVP_MAX_PLANE];
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};</pre></li><li class="- topic/li li" data-ofbid="d228403e39__20250121171649">aic_dvp_buf<div class="- topic/p p" data-ofbid="d228403e41__20250121171649">定义了 DVP 驱动的 Buf
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管理信息：<pre class="+ topic/pre pr-d/codeblock pre codeblock language-c" id="dvp_data_structure__codeblock_ymc_gdh_d1c" data-ofbid="dvp_data_structure__codeblock_ymc_gdh_d1c"><strong class="hl-keyword">struct</strong> aic_dvp_buf {
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<strong class="hl-keyword">struct</strong> vb2_v4l2_buffer vb;
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<strong class="hl-keyword">struct</strong> list_head list;
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dma_addr_t paddr[DVP_MAX_PLANE];
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bool dvp_using;
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};</pre></div></li></ul></div><section class="- topic/section section" id="dvp_data_structure__section_ytx_qzm_4dc" data-ofbid="dvp_data_structure__section_ytx_qzm_4dc"><h2 class="- topic/title title sectiontitle"> 输入输出的数据格式</h2>
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<ul class="- topic/ul ul" id="dvp_data_structure__ul_upd_5xm_4dc" data-ofbid="dvp_data_structure__ul_upd_5xm_4dc"><li class="- topic/li li" data-ofbid="d228403e51__20250121171649">
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<div class="- topic/div div section" id="dvp_data_structure__enum-dvp-input">
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<strong class="+ topic/ph hi-d/b ph b">enum dvp_input</strong>
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<div class="- topic/p p" data-ofbid="d228403e58__20250121171649"><span class="- topic/ph ph">属于 HAL 层接口，</span>定义了 DVP
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输入数据的格式：<pre class="+ topic/pre pr-d/codeblock pre codeblock language-c" id="dvp_data_structure__codeblock_jf1_mkt_2dc" data-ofbid="dvp_data_structure__codeblock_jf1_mkt_2dc"><strong class="hl-keyword">enum</strong> dvp_input {
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DVP_IN_RAW = <span class="hl-number">0</span>,
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DVP_IN_YUV422 = <span class="hl-number">1</span>,
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DVP_IN_BT656 = <span class="hl-number">2</span>,
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};</pre></div></div>
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</li><li class="- topic/li li" data-ofbid="d228403e65__20250121171649">
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<div class="- topic/div div section" id="dvp_data_structure__enum-dvp-input-yuv-seq">
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<strong class="+ topic/ph hi-d/b ph b">enum dvp_input_yuv_seq</strong>
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<div class="- topic/p p" data-ofbid="d228403e72__20250121171649"><span class="- topic/ph ph">属于 HAL 层接口，</span>定义了 DVP 输入数据的 YUV
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格式：<pre class="+ topic/pre pr-d/codeblock pre codeblock language-c" id="dvp_data_structure__codeblock_bkq_mkt_2dc" data-ofbid="dvp_data_structure__codeblock_bkq_mkt_2dc"><strong class="hl-keyword">enum</strong> dvp_input_yuv_seq {
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DVP_YUV_DATA_SEQ_YUYV = <span class="hl-number">0</span>,
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DVP_YUV_DATA_SEQ_YVYU = <span class="hl-number">1</span>,
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DVP_YUV_DATA_SEQ_UYVY = <span class="hl-number">2</span>,
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DVP_YUV_DATA_SEQ_VYUY = <span class="hl-number">3</span>,
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};</pre></div></div>
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</li><li class="- topic/li li" data-ofbid="d228403e79__20250121171649">
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<div class="- topic/div div section" id="dvp_data_structure__enum-dvp-output">
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<strong class="+ topic/ph hi-d/b ph b">enum dvp_output</strong>
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<div class="- topic/p p" data-ofbid="d228403e86__20250121171649"><span class="- topic/ph ph">属于 HAL 层接口，</span>定义了 DVP
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输出数据的格式：<pre class="+ topic/pre pr-d/codeblock pre codeblock language-c" id="dvp_data_structure__codeblock_l3v_mkt_2dc" data-ofbid="dvp_data_structure__codeblock_l3v_mkt_2dc"><strong class="hl-keyword">enum</strong> dvp_output {
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DVP_OUT_RAW_PASSTHROUGH = <span class="hl-number">0</span>,
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DVP_OUT_YUV422_COMBINED_NV16 = <span class="hl-number">1</span>,
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DVP_OUT_YUV420_COMBINED_NV12 = <span class="hl-number">2</span>,
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};</pre></div></div>
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