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212 lines
6.2 KiB
C
212 lines
6.2 KiB
C
/*
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* Copyright (c) 2022, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ARTINCHIP_HAL_DMA_REG_H_
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#define _ARTINCHIP_HAL_DMA_REG_H_
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#include "aic_core.h"
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#include "hal_dma.h"
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#include "aic_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define TASK_MAX_NUM 24
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#define DELAY_DEF_VAL 0x40
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#define DMA_IRQ_CHAN_NR 4
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#define DMA_IRQ_EN_REG(x) ((x) * 0x04 + 0x00)
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#define DMA_IRQ_DIS_REG(x) ((x) * 0x04 + 0x20)
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#if defined(AIC_DMA_DRV_V10) || defined(AIC_DMA_DRV_V11) \
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|| defined(AIC_DMA_DRV_V12)
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#define DMA_CHAN_OFFSET (0x40)
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#define DMA_IRQ_STA_REG(x) ((x) * 0x04 + 0x10)
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#define DMA_CH_STA_REG (0x0030)
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#define DMA_LINK_END_FLAG 0xFFFFF800
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#endif
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#ifdef AIC_DMA_DRV_V20
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#define DMA_CHAN_OFFSET (0x80)
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#define DMA_IRQ_STA_REG(x) ((x) * 0x04 + 0x40)
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#define DMA_CH_STA_REG (0x00A0)
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#define DMA_LINK_ID_DEF 0xa1c86688
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#define DMA_LINK_END_FLAG 0xFFFFFFFC
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#endif
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/*
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* define dma_v1.x register list
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*/
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#define DMA_MEM_CFG (0x0020)
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#define DMA_GATE_REG (0x0028)
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#define DMA_CH_EN_REG (0x0000)
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#define DMA_CH_PAUSE_REG (0x0004)
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#define DMA_CH_TASK_REG (0x0008)
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#define DMA_CH_CFG_REG (0x000C)
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#define DMA_CH_SRC_REG (0x0010)
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#define DMA_CH_SINK_REG (0x0014)
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#define DMA_CH_LEFT_REG (0x0018)
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#define DMA_CH_MODE_REG (0x0028)
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#define DMA_CH_PKG_NUM_REG (0x0030)
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#define DMA_CH_MEMSET_VAL_REG (0x0034)
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/*
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* define dma_v2.x register list
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*/
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#define DMA_BUS_CFG_REG (0x80)
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#define DMA_SET_LINK_ID_REG (0x88)
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#define DMA_FIFO_SIZE_REG (0x90)
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/* channel config */
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#define DMA_CH_CTL1_REG (0x00)
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#define DMA_CH_CTL2_REG (0x04)
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#define DMA_CH_TASK_ADD1_REG (0x08)
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#define DMA_CH_TASK_ADD2_REG (0x0C)
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#define DMA_CH_CTL3_REG (0x10)
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#define DMA_CH_CTL4_REG (0x14)
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#define DMA_CH_MEM_SET_REG (0x18)
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#define DMA_CH_TASK_BCNT_REG (0x1c)
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#define DMA_LINK_ID_REG (0x20)
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/* task config */
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#define DMA_TASK_CFG1_REG (0x24)
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#define DMA_BLOCK_LEN_REG (0x28)
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#define DMA_SRC_ADDR_REG (0x2C)
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#define DMA_DST_ADDR_REG (0x30)
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#define DMA_TASK_LEN_REG (0x34)
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#define DMA_TASK_CFG2_REG (0x38)
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#define DMA_NEXT_TASK_ADDR_REG (0x3c)
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#define DMA_SRC_WB_ADDR_SET_REG (0x40)
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#define DMA_DST_WB_ADDR_SET_REG (0x44)
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#define DMA_SRC_WB_DATA_REG (0x48)
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#define DMA_DST_WB_DATA_REG (0x4C)
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#define DMA_DEBUG_REG (0x60)
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/*
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* define macro for access register for specific channel
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*/
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#if defined(AIC_DMA_DRV_V10) || defined(AIC_DMA_DRV_V11) \
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|| defined(AIC_DMA_DRV_V12)
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#define DMA_IRQ_HALF_TASK BIT(0)
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#define DMA_IRQ_ONE_TASK BIT(1)
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#define DMA_IRQ_ALL_TASK BIT(2)
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#define DMA_IRQ_CH_WIDTH (4)
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#define DMA_IRQ_MASK(ch) (GENMASK(2, 0) << DMA_IRQ_SHIFT(ch))
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#endif
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#ifdef AIC_DMA_DRV_V20
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#define DMA_IRQ_HALF_TASK BIT(0)
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#define DMA_IRQ_ONE_TASK BIT(1)
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#define DMA_IRQ_LINK_TASK BIT(2)
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#define DMA_IRQ_ID_ERR BIT(3)
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#define DMA_IRQ_ADDR_ERR BIT(4)
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#define DMA_IRQ_RD_AHB_ERR BIT(5)
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#define DMA_IRQ_WT_AHB_ERR BIT(6)
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#define DMA_IRQ_WT_AXI_ERR BIT(7)
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#define DMA_IRQ_CH_WIDTH (8)
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#define DMA_IRQ_MASK(ch) (GENMASK(7, 0) << DMA_IRQ_SHIFT(ch))
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#endif
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#define DMA_IRQ_SHIFT(ch) (DMA_IRQ_CH_WIDTH * (ch))
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#define AIC_DMA_BUS_WIDTH \
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(BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_16_BYTES))
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/*
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* define bit index in channel configuration register
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*/
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#if defined(AIC_DMA_DRV_V10) || defined(AIC_DMA_DRV_V11) \
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|| defined(AIC_DMA_DRV_V12)
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/* dma_v1.x task config */
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#define DST_WIDTH_BITSHIFT 25
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#define DST_ADDR_BITSHIFT 24
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#define DST_BURST_BITSHIFT 22
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#define DST_PORT_BITSHIFT 16
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#define SRC_WIDTH_BITSHIFT 9
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#define SRC_ADDR_BITSHIFT 8
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#define SRC_BURST_BITSHIFT 6
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#define SRC_PORT_BITSHIFT 0
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#define ADDR_LINEAR_MODE 0
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#define ADDR_FIXED_MODE 1
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#endif
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#ifdef AIC_DMA_DRV_V20
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/* dma_v2.x task config */
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#define SRC_PORT_BITSHIFT 0
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#define SRC_BURST_BITSHIFT 6
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#define SRC_TYPE_BITSHIFT 8
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#define SRC_WIDTH_BITSHIFT 12
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#define DST_PORT_BITSHIFT 16
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#define DST_BURST_BITSHIFT 22
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#define DST_TYPE_BITSHIFT 24
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#define DST_WIDTH_BITSHIFT 28
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#define TYPE_IO_SINGLE 0
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#define TYPE_BURST 1
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#define TYPE_MEMORY 2
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#define TYPE_MEMORYSET 3
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#endif
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#define DMA_DRQ_PORT_MASK 0x3F
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#define DMA_WAIT_MODE 0
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#define DMA_HANDSHAKE_MODE 1
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#define DMA_DST_MODE_SHIFT 3
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#define DMA_SRC_MODE_SHIFT 2
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#if defined(AIC_DMA_DRV_V12)
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#define DMA_SRC_HANDSHAKE_ENABLE 5
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#define DMA_DST_HANDSHAKE_ENABLE 6
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#else
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#define DMA_SRC_HANDSHAKE_ENABLE 4
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#define DMA_DST_HANDSHAKE_ENABLE 4
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#endif
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#define DMA_S_WAIT_D_HANDSHAKE (DMA_HANDSHAKE_MODE << DMA_DST_MODE_SHIFT)
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#define DMA_S_HANDSHAKE_D_WAIT (DMA_HANDSHAKE_MODE << DMA_SRC_MODE_SHIFT)
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#define DMA_S_WAIT_D_WAIT (DMA_WAIT_MODE)
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#define DMA_FIFO_SIZE 0x200
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/*
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* define bit index in channel pause register
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*/
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#if defined(AIC_DMA_DRV_V10) || defined(AIC_DMA_DRV_V11) \
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|| defined(AIC_DMA_DRV_V12)
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#define DMA_CH_RESUME 0x00
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#define DMA_CH_PAUSE 0x01
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#endif
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#ifdef AIC_DMA_DRV_V20
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#define DMA_CH_RESUME 0x00
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#define DMA_CH_LINK_PAUSE 0x01
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#define DMA_CH_TASK_PAUSE 0x02
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#define DMA_CH_ABANDON 0x04
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#endif
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#define DMA_CH_MEMSET 0x10
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#ifdef __cplusplus
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}
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#endif
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struct aic_dma_dev {
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struct aic_dma_task task[TASK_MAX_NUM];
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s32 inited;
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unsigned long base;
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u32 burst_length; /* burst length capacity */
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u32 addr_widths; /* address width support capacity */
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struct aic_dma_chan dma_chan[AIC_DMA_CH_NUM];
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struct aic_dma_task *freetask;
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};
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struct aic_dma_dev *get_aic_dma_dev(void);
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void *aic_dma_task_add(struct aic_dma_task *prev,
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struct aic_dma_task *next,
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struct aic_dma_chan *chan);
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int aic_set_burst(struct dma_slave_config *sconfig,
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enum dma_transfer_direction direction,
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u32 *p_cfg);
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struct aic_dma_task *aic_dma_task_alloc(void);
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void aic_dma_free_desc(struct aic_dma_chan *chan);
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#endif /*_ARTINCHIP_HAL_DMA_REG_H_ */
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