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41 lines
931 B
C
41 lines
931 B
C
/*
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* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: matteo <duanmt@artinchip.com>
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*/
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#ifndef _ARTINCHIP_HAL_PWMCS_H_
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#define _ARTINCHIP_HAL_PWMCS_H_
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#include "aic_common.h"
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#ifdef CONFIG_FPGA_BOARD_ARTINCHIP
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#define PWMCS_CLK_RATE 24000000 /* 24 MHz */
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#else
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#define PWMCS_CLK_RATE 200000000 /* 200 MHz */
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#endif
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#define CAP_MAX_FREQ 1000000 /* 1MHz */
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void hal_cap_ch_init(u32 ch);
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void hal_cap_ch_deinit(u32 ch);
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void hal_cap_int_enable(u32 ch, int enable);
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u32 hal_cap_is_pending(u32 ch);
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int hal_cap_set_freq(u32 ch, u32 freq);
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int hal_cap_set_cnt(u32 ch, u32 cnt);
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int hal_cap_get(u32 ch);
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int hal_cap_enable(u32 ch);
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int hal_cap_disable(u32 ch);
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void hal_cap_cnt_start(u32 ch);
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void hal_cap_cnt_stop(u32 ch);
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int hal_cap_init(void);
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int hal_cap_deinit(void);
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void hal_cap_status_show(void);
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#endif // end of _ARTINCHIP_HAL_PWMCS_H_
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