2024-06-04 19:00:30 +08:00
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/*
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2025-07-22 11:15:46 +08:00
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* Copyright (c) 2024-2025, ArtInChip Technology Co., Ltd
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2024-06-04 19:00:30 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: Li Siyao <siyao.li@artinchip.com>
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*/
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struct aic_tsen_ch aic_tsen_chs[] = {
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#ifdef AIC_USING_TSEN_CPU
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{
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.id = 0,
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.available = 1,
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.name = "tsen_cpu",
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.mode = AIC_TSEN0_MODE,
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.soft_mode = AIC_TSEN0_SOFT_MODE,
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.hta_enable = 0,
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.lta_enable = 0,
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.otp_enable = 0,
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2025-07-22 11:15:46 +08:00
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#ifndef FPGA_BOARD_ARTINCHIP
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2024-06-04 19:00:30 +08:00
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.slope = -1134,
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.offset = 2439001,
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#endif
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},
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#endif
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#ifdef AIC_USING_TSEN_GPAI
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{
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.id = 1,
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.available = 1,
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.name = "tsen_gpai",
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.mode = AIC_TSEN1_MODE,
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.soft_mode = AIC_TSEN1_SOFT_MODE,
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.hta_enable = 0,
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.lta_enable = 0,
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.otp_enable = 0,
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2025-07-22 11:15:46 +08:00
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#ifndef FPGA_BOARD_ARTINCHIP
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2024-06-04 19:00:30 +08:00
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.slope = -1139,
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.offset = 2450566,
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#endif
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}
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#endif
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};
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