2024-09-03 11:16:08 +08:00
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/**
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******************************************************************************
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*
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* @file asr_sdio.h
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*
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* Copyright (C) ASR
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*
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******************************************************************************
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*/
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#ifndef _ASR_SDIO_H_
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#define _ASR_SDIO_H_
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#include <stdio.h>
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#include "uwifi_platform.h"
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#include "uwifi_ops_adapter.h"
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#define SDIO_PORT_IDX_0 0
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#define SDIO_PORT_IDX_1 1
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#define SDIO_PORT_IDX_2 2
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#define SDIO_PORT_IDX_3 3
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#define SDIO_PORT_IDX_4 4
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#define SDIO_PORT_IDX_5 5
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#define SDIO_PORT_IDX_6 6
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#define SDIO_PORT_IDX_7 7
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#define SDIO_PORT_IDX_8 8
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#define SDIO_PORT_IDX_9 9
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#define SDIO_PORT_IDX_10 10
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#define SDIO_PORT_IDX_11 11
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#define SDIO_PORT_IDX_12 12
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#define SDIO_PORT_IDX_13 13
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#define SDIO_PORT_IDX_14 14
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#define SDIO_PORT_IDX_15 15
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#define SDIO_PORT_IDX(idx) SDIO_PORT_IDX_##idx
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//marvell sdio card reg
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#define H2C_INTEVENT 0x0
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#define HOST_INT_RSR 0x1
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#define HOST_INTMASK 0x2
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#define HOST_INT_UPLD_EN (1 << 0)
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#define HOST_INT_DNLD_EN (1 << 1)
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#define HOST_INT_UNDER_FLOW_EN (1 << 2)
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#define HOST_INT_OVER_FLOW_EN (1 << 3)
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#define HOST_INT_MASK (HOST_INT_UPLD_EN | HOST_INT_DNLD_EN | HOST_INT_UNDER_FLOW_EN | HOST_INT_OVER_FLOW_EN)
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#define HOST_INT_RSR_MASK 0xFF
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#define HOST_INT_STATUS 0x3
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#define HOST_INT_UPLD_ST (1 << 0)
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#define HOST_INT_DNLD_ST (1 << 1)
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#define HOST_INT_UNDER_FLOW_ST (1 << 2)
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#define HOST_INT_OVER_FLOW_ST (1 << 3)
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#define RD_BITMAP_L 0x4
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#define RD_BITMAP_U 0x5
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#define WR_BITMAP_L 0x6
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#define WR_BITMAP_U 0x7
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#define RD_LEN0_L 0x8
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#define RD_LEN0_U 0x9
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#define RD_LEN1_L 0xA
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#define RD_LEN1_U 0xB
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#define RD_LEN2_L 0xC
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#define RD_LEN2_U 0xD
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#define RD_LEN3_L 0xE
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#define RD_LEN3_U 0xF
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#define RD_LEN4_L 0x10
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#define RD_LEN4_U 0x11
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#define RD_LEN5_L 0x12
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#define RD_LEN5_U 0x13
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#define RD_LEN6_L 0x14
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#define RD_LEN6_U 0x15
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#define RD_LEN7_L 0x16
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#define RD_LEN7_U 0x17
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#define RD_LEN8_L 0x18
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#define RD_LEN8_U 0x19
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#define RD_LEN9_L 0x1A
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#define RD_LEN9_U 0x1B
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#define RD_LEN10_L 0x1C
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#define RD_LEN10_U 0x1D
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#define RD_LEN11_L 0x1E
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#define RD_LEN11_U 0x1F
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#define RD_LEN12_L 0x20
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#define RD_LEN12_U 0x21
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#define RD_LEN13_L 0x22
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#define RD_LEN13_U 0x23
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#define RD_LEN14_L 0x24
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#define RD_LEN14_U 0x25
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#define RD_LEN15_L 0x26
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#define RD_LEN15_U 0x27
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#define RD_LEN_L(index) (0x8 + (index) * 2)
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#define RD_LEN_U(index) (0x9 + (index) * 2)
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#define HOST_RESTART 0x28
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#define C2H_INTEVENT 0x30
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#define C2H_DNLD_CARD_RDY (1 << 0)
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#define C2H_UPLD_CARD_RDY (1 << 1)
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#define C2H_CIS_CARD_RDY (1 << 2)
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#define C2H_IO_RDY (1 << 3)
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#define RD_BASE_0 0x40
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#define RD_BASE_1 0x41
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#define RD_BASE_2 0x42
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#define RD_BASE_3 0x43
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#define WR_BASE_0 0x44
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#define WR_BASE_1 0x45
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#define WR_BASE_2 0x46
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#define WR_BASE_3 0x47
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#define RD_INDEX 0x48
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#define WR_INDEX 0x49
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#define SCRATCH_0 0x60
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#define SCRATCH_1 0x61
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#define CRC_SUCCESS (1 << 14)
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#define CRC_FAIL 0xABCE
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#define BOOT_SUCCESS (1 << 15)
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#define SCRATCH0_2 0x62
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#define SCRATCH0_3 0x63
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#define SCRATCH1_0 0x64
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#define SCRATCH1_1 0x65
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#define SCRATCH1_2 0x66
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#define SCRATCH1_3 0x67
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#define SDIO_CONFIG2 0x6c
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#define AUTO_RE_ENABLE_INT (1<<4)
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#define IO_PORT_0 0x78
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#define IO_PORT_1 0x79
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#define IO_PORT_2 0x7a
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#define MAX_POLL_TRIES 1000
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#ifndef SDIO_BLOCK_SIZE
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#define SDIO_BLOCK_SIZE 32//32 //SDIO max transfer in one cmd53:32*512=16KB
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#endif
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#define SDIO_BLOCK_SIZE_DLD SDIO_BLOCK_SIZE
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#define SDIO_DOWNLOAD_BLOCKS 270
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#define ASR_ALIGN_BLKSZ_HI(x) (((x)+SDIO_BLOCK_SIZE-1)&(~(SDIO_BLOCK_SIZE-1)))
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#define ASR_ALIGN_DLDBLKSZ_HI(x) (((x)+SDIO_BLOCK_SIZE_DLD-1)&(~(SDIO_BLOCK_SIZE_DLD-1)))
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/** Macros for Data Alignment : size */
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#define ALIGN_SZ(p, a) \
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(((p) + ((a) - 1)) & ~((a) - 1))
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/** Macros for Data Alignment : address */
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#define ALIGN_ADDR(p, a) \
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((((unsigned int)(p)) + (((unsigned int)(a)) - 1)) & ~(((unsigned int)(a)) - 1))
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#define WLAN_UPLD_SIZE (2312)
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#define DMA_ALIGNMENT 32
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struct sdio_host_sec_fw_header {
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uint32_t sec_fw_len; // total length of FW: should be 4 byte align
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uint32_t sec_crc; // fw bin crc32 results
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uint32_t chip_ram_addr; // address where fw be loaded to
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uint32_t transfer_unit; // download length in once cmd53 transmition
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uint32_t transfer_times; // TX times needed for download FW, not include the first cmd transmition
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};
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struct sdio_fw_sec_fw_header {
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uint32_t sec_fw_len; // total length of FW: should be 4 byte align
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uint32_t sec_crc; // fw bin crc32 results
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uint32_t chip_ram_addr; // address where fw be loaded to
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};
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unsigned char asr_sdio_read_cmd53(unsigned int dataport, unsigned char *data, int size);
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unsigned char sdio_writeb_cmd52(unsigned int addr, unsigned char data);
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unsigned char sdio_readb_cmd52(unsigned int addr, unsigned char *data);
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int asr_sdio_init_config(struct asr_hw *asr_hw);
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int asr_sdio_detect_change();
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int sdio_bus_probe(void);
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int asr_sdio_send_data(struct asr_hw *asr_hw,uint8_t type,uint8_t* src,uint16_t len,uint32_t io_addr,uint16_t bitmap_record);
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//int asr_sdio_download_firmware(const struct firmware *fw_img);
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void sdio_card_gpio_isr(void);
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int asr_sdio_enable_int(uint8_t mask);
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int asr_sdio_disable_int(uint8_t mask);
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int sdio_get_ioport(void);
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int asr_sdio_config_rsr(uint8_t mask);
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int asr_sdio_config_auto_reenable(void);
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2025-01-08 19:12:06 +08:00
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int asr_sdio_tx_common_port_dispatch(struct asr_hw *asr_hw, u8 * src, u32 len, unsigned int io_addr, u16 bitmap_record);
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2024-09-03 11:16:08 +08:00
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uint8_t asr_sdio_tx_get_available_data_port(struct asr_hw *asr_hw,
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uint16_t ava_pkt_num, uint8_t * port_num, unsigned int *io_addr, uint16_t * bitmap_record);
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int asr_sdio_download_firmware(struct asr_hw *asr_hw, uint8_t *fw_img_data, uint32_t fw_img_size);
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void asr_sdio_claim_host(void);
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void asr_sdio_release_host(void);
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#endif /* _ASR_SDIO_H_ */
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