2023-08-30 16:21:18 +08:00
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/*
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2025-04-23 17:54:31 +08:00
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* Copyright (c) 2023-2025, ArtInChip Technology Co., Ltd
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2023-08-30 16:21:18 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: xuan.wen <xuan.wen@artinchip.com>
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*/
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#ifndef __SPINAND_H__
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#define __SPINAND_H__
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#include <aic_core.h>
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#define SPINAND_SUCCESS 0 /**< success */
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#define SPINAND_ERR 1 /**< not found or not supported */
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#define SPINAND_ERR_TIMEOUT 2 /**< timeout error */
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#define SPINAND_ERR_ECC 3 /**< ecc check error */
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2024-06-04 19:00:30 +08:00
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#define SPINAND_TRUE 1
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#define SPINAND_FALSE 0
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2023-08-30 16:21:18 +08:00
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#define SPINAND_DIE_ID0 (0)
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#define SPINAND_DIE_ID1 (1)
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2023-11-09 20:19:51 +08:00
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#undef pr_debug
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#ifdef AIC_SPINAND_DRV_DEBUG
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2023-12-22 10:19:53 +08:00
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#define pr_debug pr_info
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2023-11-09 20:19:51 +08:00
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#else
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#define pr_debug(fmt, ...)
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#endif
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2023-08-30 16:21:18 +08:00
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/**
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* struct nand_bbt - bad block table object
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* @cache: in memory BBT cache
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*/
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struct nand_bbt {
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u8 *cache;
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};
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2023-12-22 10:19:53 +08:00
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struct aic_spinand;
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2024-09-30 17:06:01 +08:00
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/*
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* struct spinand_devid - SPI NAND device id structure
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* @id: device id of current chip
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* @len: number of bytes in device id
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*/
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struct spinand_devid {
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const u8 *id;
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const u8 len;
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};
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#define DEVID(...) \
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{ \
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.id = (const u8[]){ __VA_ARGS__ }, \
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.len = sizeof((u8[]){ __VA_ARGS__ }), \
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}
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2025-01-08 19:12:06 +08:00
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struct aic_oob_region {
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u32 offset;
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u32 length;
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};
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2023-08-30 16:21:18 +08:00
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/* SPI NAND flash information */
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struct aic_spinand_info {
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2024-09-30 17:06:01 +08:00
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struct spinand_devid devid;
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2023-08-30 16:21:18 +08:00
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u16 page_size;
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u16 oob_size;
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2024-01-27 08:47:24 +08:00
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u16 block_per_lun;
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u16 pages_per_eraseblock;
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u8 planes_per_lun;
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2023-08-30 16:21:18 +08:00
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u8 is_die_select;
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const char *sz_description;
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struct spi_nand_cmd_cfg *cmd;
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2023-12-22 10:19:53 +08:00
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int (*get_status)(struct aic_spinand *flash, u8 status);
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2025-01-08 19:12:06 +08:00
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int (*oob_get_user)(struct aic_spinand *flash, int section,
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struct aic_oob_region *oobuser);
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2023-08-30 16:21:18 +08:00
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};
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typedef struct aic_spinand_info *aic_spinand_info_t;
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2024-01-27 08:47:24 +08:00
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#define PAGESIZE(x) (u16)(x)
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#define OOBSIZE(x) (u16)(x)
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#define BPL(x) (u16)(x)
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#define PPB(x) (u16)(x)
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#define PLANENUM(x) (u8)(x)
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#define DIE(x) (u16)(x)
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2023-08-30 16:21:18 +08:00
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#define SPINAND_MAX_ID_LEN 4
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struct spinand_id {
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u8 data[SPINAND_MAX_ID_LEN];
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};
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struct aic_spinand {
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const struct aic_spinand_info *info;
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struct spinand_id id;
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void *user_data;
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void *lock;
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2025-01-08 19:12:06 +08:00
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u8 bus;
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2023-08-30 16:21:18 +08:00
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u8 use_continuous_read;
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u8 qspi_dl_width;
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u8 IsInited;
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u8 *databuf;
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u8 *oobbuf;
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struct nand_bbt bbt;
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};
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typedef struct aic_spinand *aic_spinand_t;
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int spinand_read_id_op(struct aic_spinand *flash, u8 *id);
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int spinand_block_erase(struct aic_spinand *flash, u16 blk);
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int spinand_flash_init(struct aic_spinand *flash);
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int spinand_read_page(struct aic_spinand *flash, u32 page, u8 *data,
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u32 data_len, u8 *spare, u32 spare_len);
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int spinand_block_isbad(struct aic_spinand *flash, u16 blk);
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2024-09-03 11:16:08 +08:00
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int spinand_get_status(struct aic_spinand *flash, u16 blk);
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2025-04-23 17:54:31 +08:00
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int spinand_set_status(struct aic_spinand *flash, u16 blk, u16 status);
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2023-08-30 16:21:18 +08:00
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int spinand_continuous_read(struct aic_spinand *flash, u32 page, u8 *data,
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u32 size);
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int spinand_write_page(struct aic_spinand *flash, u32 page, const u8 *data,
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u32 data_len, const u8 *spare, u32 spare_len);
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int spinand_block_markbad(struct aic_spinand *flash, u16 blk);
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int spinand_config_set(struct aic_spinand *flash, u8 mask, u8 val);
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int spinand_erase(struct aic_spinand *flash, u32 offset, u32 size);
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int spinand_read(struct aic_spinand *flash, u8 *addr, u32 offset, u32 size);
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int spinand_write(struct aic_spinand *flash, u8 *addr, u32 offset, u32 size);
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2025-04-23 17:54:31 +08:00
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int spinand_get_feature(struct aic_spinand *flash, u8 reg_addr);
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2023-08-30 16:21:18 +08:00
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#ifdef AIC_SPINAND_CONT_READ
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#define SPINAND_CMD_READ_FROM_CACHE_X4_CONT_CFG \
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{ \
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SPINAND_CMD_READ_FROM_CACHE_X4, 1, 0, 0, 4, 4 \
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}
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#endif
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/*
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* Standard SPI-NAND flash commands
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*/
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#define SPINAND_CMD_RESET 0xff
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#define SPINAND_CMD_GET_FEATURE 0x0f
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#define SPINAND_CMD_SET_FEATURE 0x1f
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#define SPINAND_CMD_PAGE_READ 0x13
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#define SPINAND_CMD_READ_PAGE_CACHE_RDM 0x30
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#define SPINAND_CMD_READ_PAGE_CACHE_LAST 0x3f
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#define SPINAND_CMD_READ_FROM_CACHE 0x03
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#define SPINAND_CMD_READ_FROM_CACHE_FAST 0x0b
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#define SPINAND_CMD_READ_FROM_CACHE_X2 0x3b
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#define SPINAND_CMD_READ_FROM_CACHE_DUAL_IO 0xbb
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#define SPINAND_CMD_READ_FROM_CACHE_X4 0x6b
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#define SPINAND_CMD_READ_FROM_CACHE_QUAD_IO 0xeb
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#define SPINAND_CMD_BLK_ERASE 0xd8
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#define SPINAND_CMD_PROG_EXC 0x10
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#define SPINAND_CMD_PROG_LOAD 0x02
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#define SPINAND_CMD_PROG_LOAD_RDM_DATA 0x84
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#define SPINAND_CMD_PROG_LOAD_X4 0x32
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#define SPINAND_CMD_PROG_LOAD_RDM_DATA_X4 0x34
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#define SPINAND_CMD_READ_ID 0x9f
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#define SPINAND_CMD_WR_DISABLE 0x04
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#define SPINAND_CMD_WR_ENABLE 0x06
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#define SPINAND_CMD_END 0x0
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#define SPINAND_CMD_GET_FEATURE_CFG \
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{ \
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SPINAND_CMD_GET_FEATURE, 1, 1, 1, 0, 1 \
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}
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#define SPINAND_CMD_SET_FEATURE_CFG \
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{ \
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SPINAND_CMD_SET_FEATURE, 1, 1, 1, 0, 1 \
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}
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#define SPINAND_CMD_WR_ENABLE_CFG \
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{ \
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SPINAND_CMD_WR_ENABLE, 1, 0, 0, 0, 0 \
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}
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#define SPINAND_CMD_WR_DISABLE_CFG \
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{ \
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SPINAND_CMD_WR_DISABLE, 1, 0, 0, 0, 0 \
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}
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#define SPINAND_CMD_PROG_EXC_CFG \
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{ \
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SPINAND_CMD_PROG_EXC, 1, 3, 1, 0, 0 \
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}
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#define SPINAND_CMD_PAGE_READ_CFG \
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{ \
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SPINAND_CMD_PAGE_READ, 1, 3, 1, 0, 0 \
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}
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#define SPINAND_CMD_BLK_ERASE_CFG \
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{ \
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SPINAND_CMD_BLK_ERASE, 1, 3, 1, 0, 0 \
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}
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#define SPINAND_CMD_READ_ID_CFG \
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{ \
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SPINAND_CMD_READ_ID, 1, 0, 1, 1, 1 \
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}
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#define SPINAND_CMD_RESET_CFG \
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{ \
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SPINAND_CMD_RESET, 1, 0, 0, 0, 0 \
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}
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struct spi_nand_cmd_cfg {
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u8 opcode;
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u8 opcode_bits;
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u8 addr_bytes;
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u8 addr_bits;
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u8 dummy_bytes;
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u8 data_bits;
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};
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/* feature registers */
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#define REG_BLOCK_LOCK 0xa0
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#define REG_DIE_SELECT 0xd0
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/* configuration register */
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#define REG_CFG 0xb0
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#define CFG_OTP_ENABLE BIT(6)
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#define CFG_ECC_ENABLE BIT(4)
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#define CFG_BUF_ENABLE BIT(3)
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#define CFG_QUAD_ENABLE BIT(0)
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/* status register */
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2023-12-22 10:19:53 +08:00
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#define REG_STATUS 0xc0
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#define STATUS_BUSY BIT(0)
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#define STATUS_ERASE_FAILED BIT(2)
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#define STATUS_PROG_FAILED BIT(3)
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#define STATUS_ECC_MASK GENMASK(5, 4)
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#define STATUS_ECC_NO_BITFLIPS (0 << 4)
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#define STATUS_ECC_HAS_1_4_BITFLIPS (1 << 4)
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#define STATUS_ECC_UNCOR_ERROR (2 << 4)
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2023-08-30 16:21:18 +08:00
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#ifdef SPI_NAND_WINBOND
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extern const struct spinand_manufacturer winbond_spinand_manufacturer;
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#endif
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#ifdef SPI_NAND_XTX
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extern const struct spinand_manufacturer xtx_spinand_manufacturer;
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#endif
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#ifdef SPI_NAND_GIGADEVICE
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extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
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#endif
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#ifdef SPI_NAND_FORESEE
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extern const struct spinand_manufacturer foresee_spinand_manufacturer;
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#endif
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#ifdef SPI_NAND_TOSHIBA
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extern const struct spinand_manufacturer toshiba_spinand_manufacturer;
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#endif
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#ifdef SPI_NAND_MACRONIX
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extern const struct spinand_manufacturer macronix_spinand_manufacturer;
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#endif
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#ifdef SPI_NAND_ZETTA
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extern const struct spinand_manufacturer zetta_spinand_manufacturer;
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#endif
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#ifdef SPI_NAND_DOSILICON
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extern const struct spinand_manufacturer dosilicon_spinand_manufacturer;
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#endif
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#ifdef SPI_NAND_ETRON
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extern const struct spinand_manufacturer etron_spinand_manufacturer;
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#endif
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#ifdef SPI_NAND_MICRON
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extern const struct spinand_manufacturer micron_spinand_manufacturer;
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#endif
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#ifdef SPI_NAND_ZBIT
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extern const struct spinand_manufacturer zbit_spinand_manufacturer;
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#endif
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#ifdef SPI_NAND_ESMT
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extern const struct spinand_manufacturer esmt_spinand_manufacturer;
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#endif
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#ifdef SPI_NAND_UMTEK
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extern const struct spinand_manufacturer umtek_spinand_manufacturer;
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#endif
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#ifdef SPI_NAND_QUANXING
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extern const struct spinand_manufacturer quanxing_spinand_manufacturer;
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#endif
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2024-04-03 16:40:57 +08:00
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#ifdef SPI_NAND_XINCUN
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extern const struct spinand_manufacturer xincun_spinand_manufacturer;
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#endif
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2025-01-08 19:12:06 +08:00
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#ifdef SPI_NAND_FUDANMICRO
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extern const struct spinand_manufacturer fudanmicro_spinand_manufacturer;
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#endif
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2023-08-30 16:21:18 +08:00
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2024-01-27 08:47:24 +08:00
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extern struct spi_nand_cmd_cfg cmd_cfg_table[];
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2023-08-30 16:21:18 +08:00
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const struct aic_spinand_info *
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2024-09-30 17:06:01 +08:00
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spinand_match_and_init(u8 *devid, const struct aic_spinand_info *table,
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2023-08-30 16:21:18 +08:00
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u32 table_size);
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int aic_spinand_transfer_message(struct aic_spinand *flash,
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struct spi_nand_cmd_cfg *cfg, u32 addr,
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u8 *sendBuff, u8 *recvBuff, u32 DataCount);
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2025-01-08 19:12:06 +08:00
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/* ooblayout
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* distinguish the ECC protected bytes on the oob region
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*/
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int spinand_ooblayout_map_user(struct aic_spinand *flash, u8 *oobbuf,
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const u8 *spare, int start, int nbytes);
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int spinand_ooblayout_unmap_user(struct aic_spinand *flash, u8 *dst,
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u8 *src, int start, int nbytes);
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2023-08-30 16:21:18 +08:00
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#endif /* __SPINAND_H__ */
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