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<div class=" wh_topic_content body "><main role="main"><article class="- topic/topic topic" role="article" aria-labelledby="ariaid-title1">
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<span class="edit-link" style="font-size:12px; opacity:0.6; text-align:right; vertical-align:middle"><a target="_blank" href="http://aicdocco/taskstopics/sdk/cmu/cmu-design-guide-lite.dita">Edit online</a></span><h1 class="- topic/title title topictitle1" id="ariaid-title1">设计说明</h1>
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<div class="date inPage">9 Apr 2025</div><div style="color: gray;">
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Read time: 2 minute(s)
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<div class="- topic/body body">
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<section class="- topic/section section" id="id__section_ul3_k44_mdc" data-ofbid="id__section_ul3_k44_mdc"><h2 class="- topic/title title sectiontitle">源码说明</h2>
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<div class="- topic/p p" data-ofbid="d196147e33__20250409171053">CMU 相关 <span class="+ topic/ph sw-d/filepath ph filepath">.c</span> 和 <span class="+ topic/ph sw-d/filepath ph filepath">.h</span> 文件分别位于
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<span class="+ topic/ph sw-d/filepath ph filepath">luban-lite\bsp\artinchip\hal\cmu</span> 和
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<span class="+ topic/ph sw-d/filepath ph filepath">luban-lite\bsp\artinchip\include\hal</span> 目录。主要源文件说明如下：<div class="table-container"><table class="- topic/table table frame-all" id="id__table_kkq_yhd_bdc" data-ofbid="id__table_kkq_yhd_bdc" data-cols="2"><caption></caption><colgroup><col style="width:42.19409282700421%"/><col style="width:57.80590717299579%"/></colgroup><thead class="- topic/thead thead">
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<th class="- topic/entry entry colsep-1 rowsep-1" id="id__table_kkq_yhd_bdc__entry__1"><p class="- topic/p p" data-ofbid="d196147e60__20250409171053">文件</p></th>
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<th class="- topic/entry entry colsep-0 rowsep-1" id="id__table_kkq_yhd_bdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e64__20250409171053">说明</p></th>
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<td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><p class="- topic/p p" data-ofbid="d196147e74__20250409171053"><span class="+ topic/ph sw-d/filepath ph filepath">aic_clk_id.h</span></p></td>
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e79__20250409171053">时钟 ID 以及 寄存器设置</p></td>
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<td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><p class="- topic/p p" data-ofbid="d196147e86__20250409171053"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_clk.h</span></p></td>
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e91__20250409171053">hal 层 clk api 的头文件</p></td>
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|
</tr>
|
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|
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|
<tr class="- topic/row">
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<td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><p class="- topic/p p" data-ofbid="d196147e98__20250409171053"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_clk.c</span></p></td>
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|
|
|
|
|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e103__20250409171053">hal 层 clk api 的实现</p></td>
|
|
|
|
|
|
</tr>
|
|
|
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|
<tr class="- topic/row">
|
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<td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><p class="- topic/p p" data-ofbid="d196147e110__20250409171053"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_reset.h</span></p></td>
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|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e115__20250409171053">hal 层 reset api 的头文件</p></td>
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|
|
</tr>
|
|
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<tr class="- topic/row">
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<td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><p class="- topic/p p" data-ofbid="d196147e122__20250409171053"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_reset.c</span></p></td>
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|
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|
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|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e127__20250409171053">hal 层 reset api 的实现</p></td>
|
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|
|
</tr>
|
|
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<tr class="- topic/row">
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<td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><p class="- topic/p p" data-ofbid="d196147e135__20250409171053"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_pll_clk.c</span></p></td>
|
|
|
|
|
|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e140__20250409171053">PLL 时钟的具体实现</p></td>
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|
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|
|
|
</tr>
|
|
|
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<tr class="- topic/row">
|
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<td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><p class="- topic/p p" data-ofbid="d196147e147__20250409171053"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_fixed_rate_clk.c</span></p></td>
|
|
|
|
|
|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e152__20250409171053">固定频率时钟的具体实现</p></td>
|
|
|
|
|
|
</tr>
|
|
|
|
|
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<tr class="- topic/row">
|
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|
<td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><p class="- topic/p p" data-ofbid="d196147e159__20250409171053"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_fixed_parent_clk.c</span></p></td>
|
|
|
|
|
|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e164__20250409171053">单个父时钟的时钟的具体实现</p></td>
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|
|
</tr>
|
|
|
|
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|
<tr class="- topic/row">
|
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<td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><p class="- topic/p p" data-ofbid="d196147e171__20250409171053"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_multi_parent_clk.c</span></p></td>
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|
|
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|
|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e176__20250409171053">多个父时钟的时钟的具体实现</p></td>
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|
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|
</tr>
|
|
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<tr class="- topic/row">
|
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<td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><p class="- topic/p p" data-ofbid="d196147e183__20250409171053"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_disp_clk.c</span></p></td>
|
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|
|
|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e188__20250409171053">DISP 时钟的具体实现</p></td>
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</tr>
|
|
|
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<tr class="- topic/row">
|
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<td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><p class="- topic/p p" data-ofbid="d196147e195__20250409171053"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_fpga_clk_def_v10.</span>c</p></td>
|
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|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e203__20250409171053">CMU V1.0 的 Clock 配置</p></td>
|
|
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|
|
|
</tr>
|
|
|
|
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|
<tr class="- topic/row">
|
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<td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><p class="- topic/p p" data-ofbid="d196147e211__20250409171053"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_fpga_clk_def_v11.c</span></p></td>
|
|
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|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e216__20250409171053">CMU V1.1 的 Clock 配置</p></td>
|
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|
|
|
</tr>
|
|
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|
|
|
<tr class="- topic/row">
|
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<td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><p class="- topic/p p" data-ofbid="d196147e223__20250409171053"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_fpga_clk_def_v12.c</span></p></td>
|
|
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|
|
|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e228__20250409171053">CMU V1.2 的 Clock 配置</p></td>
|
|
|
|
|
|
</tr>
|
|
|
|
|
|
<tr class="- topic/row">
|
|
|
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|
<td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><p class="- topic/p p" data-ofbid="d196147e235__20250409171053"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_reset_def_v10.c</span></p></td>
|
|
|
|
|
|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e240__20250409171053">CMU V1.0 的 Reset 配置</p></td>
|
|
|
|
|
|
</tr>
|
|
|
|
|
|
<tr class="- topic/row">
|
|
|
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|
|
<td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__1"><p class="- topic/p p" data-ofbid="d196147e247__20250409171053"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_reset_def_v11.c</span></p></td>
|
|
|
|
|
|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_kkq_yhd_bdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e252__20250409171053">CMU V1.1 的 Reset 配置</p></td>
|
|
|
|
|
|
</tr>
|
|
|
|
|
|
<tr class="- topic/row">
|
|
|
|
|
|
<td class="- topic/entry entry colsep-1 rowsep-0" headers="id__table_kkq_yhd_bdc__entry__1"><p class="- topic/p p" data-ofbid="d196147e259__20250409171053"><span class="+ topic/ph sw-d/filepath ph filepath">aic_hal_reset_def_v12.c</span></p></td>
|
|
|
|
|
|
<td class="- topic/entry entry colsep-0 rowsep-0" headers="id__table_kkq_yhd_bdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e264__20250409171053">CMU V1.2 的 Reset 配置 </p></td>
|
|
|
|
|
|
</tr>
|
|
|
|
|
|
</tbody></table></div></div>
|
|
|
|
|
|
</section>
|
|
|
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|
|
<section xml:lang="zh-CN" lang="zh-CN" class="- topic/section section" id="id__id3" data-ofbid="id__id3"><h2 class="- topic/title title sectiontitle">Clock
|
2025-01-23 16:37:00 +08:00
|
|
|
|
和 Reset 类型</h2>
|
|
|
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|
|
2025-04-23 17:54:31 +08:00
|
|
|
|
<figure class="- topic/fig fig fignone" data-ofbid="d196147e277__20250409171053">
|
|
|
|
|
|
<br/><div class="imagecenter"><img class="- topic/image image imagecenter" id="id__image_lkq_yhd_bdc" src="../../../images/cmu/cmu_sw_system.png" alt="sw_system10"/></div><br/>
|
|
|
|
|
|
</figure>
|
|
|
|
|
|
<div class="- topic/p p" data-ofbid="d196147e286__20250409171053">CMU
|
2025-01-23 16:37:00 +08:00
|
|
|
|
驱动的逻辑相对简单，目前只在
|
|
|
|
|
|
HAL 层提供了 Clock 和 Reset 的 API 接口。RTOS 驱动和 Baremetal 驱动都可以直接使用。
|
|
|
|
|
|
<div class="- topic/note note note note_note" id="id__note_ocn_5mx_bdc" data-ofbid="id__note_ocn_5mx_bdc"><span class="note__title">注：</span> 相对时钟树来说，仅终端模块才有 Reset 控制的需求。在下列时钟树中，仅 <span class="+ topic/keyword pr-d/parmname keyword parmname">fixed parent
|
|
|
|
|
|
clock</span> 同时拥有 Reset 功能。</div></div>
|
2025-04-23 17:54:31 +08:00
|
|
|
|
</section>
|
|
|
|
|
|
<section class="- topic/section section" id="id__section_itz_c44_mdc" data-ofbid="id__section_itz_c44_mdc"><h2 class="- topic/title title sectiontitle">时钟树</h2>
|
2025-01-23 16:37:00 +08:00
|
|
|
|
|
|
|
|
|
|
<div class="- topic/div div section">
|
2025-04-23 17:54:31 +08:00
|
|
|
|
<figure class="- topic/fig fig fignone" id="id__fig_rxf_3l4_mdc" data-ofbid="id__fig_rxf_3l4_mdc">
|
|
|
|
|
|
|
|
|
|
|
|
<br/><div class="imagecenter"><img class="- topic/image image imagecenter" id="id__image_sxf_3l4_mdc" src="../../../reusables/reused-topics/../../images/cmu/cmu_clock_structure_tree.png" alt="clock_tree"/></div><br/>
|
|
|
|
|
|
<figcaption data-caption-side="bottom" class="- topic/title title figcapcenter"><span class="figtitleprefix fig--title-label">图<span class="fig--title-label-number"> 1</span><span class="fig--title-label-punctuation">. </span></span><span class="fig--title">时钟树</span></figcaption></figure>
|
|
|
|
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|
<div class="- topic/p p" id="id__p_five_type_clock" data-ofbid="id__p_five_type_clock">CMU 驱动将时钟树中的时钟分为五种类型，每种类型的时钟具有不同的特性和功能：<ul class="- topic/ul ul simple" id="id__ul_nkq_yhd_bdc" data-ofbid="id__ul_nkq_yhd_bdc">
|
|
|
|
|
|
<li class="- topic/li li" data-ofbid="d196147e318__20250409171053">
|
|
|
|
|
|
<p class="- topic/p p" data-ofbid="d196147e320__20250409171053"><span class="+ topic/keyword pr-d/parmname keyword parmname">Fixed rate
|
2025-01-23 16:37:00 +08:00
|
|
|
|
clock</span>：具有固定的输出频率，通常用于驱动一些不需要动态调整频率的外设。时钟频率固定，不能调节频率，不能打开或关闭。固定频率时钟包括
|
|
|
|
|
|
OSC24M、RC1M 和 OSC32K。</p>
|
2025-04-23 17:54:31 +08:00
|
|
|
|
</li>
|
|
|
|
|
|
<li class="- topic/li li" data-ofbid="d196147e326__20250409171053">
|
|
|
|
|
|
<p class="- topic/p p" data-ofbid="d196147e328__20250409171053"><span class="+ topic/keyword pr-d/parmname keyword parmname">Fixed parent module
|
2025-01-23 16:37:00 +08:00
|
|
|
|
clock</span>：从另一个时钟信号派生出来的时钟，其输出频率与父时钟信号的频率相同。该类型时钟可以实现只有一个父时钟源的时钟驱动，主要用于各个外设模块的时钟驱动。该类型时钟可以改变时钟频率，打开或关闭时钟，获取父时钟源参数，但不能设置或改变父时钟源。</p>
|
2025-04-23 17:54:31 +08:00
|
|
|
|
</li>
|
|
|
|
|
|
<li class="- topic/li li" data-ofbid="d196147e334__20250409171053">
|
|
|
|
|
|
<p class="- topic/p p" data-ofbid="d196147e336__20250409171053"><span class="+ topic/keyword pr-d/parmname keyword parmname">Multiple parent module
|
|
|
|
|
|
clock</span>：可以从多个父时钟源中选择其中一个作为其输入，并根据需要调整输出频率。
|
2025-01-23 16:37:00 +08:00
|
|
|
|
该类型时钟可以实现有多个父时钟源的时钟驱动，主要用于各种总线时钟驱动，可以打开或关闭时钟，调节频率，获取或改变父时钟源。</p>
|
2025-04-23 17:54:31 +08:00
|
|
|
|
</li>
|
|
|
|
|
|
<li class="- topic/li li" data-ofbid="d196147e342__20250409171053">
|
|
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|
|
<p class="- topic/p p" data-ofbid="d196147e344__20250409171053"><span class="+ topic/keyword pr-d/parmname keyword parmname">Display module clock：</span>
|
2025-01-23 16:37:00 +08:00
|
|
|
|
实现了几个与显示模块相关的时钟驱动，除了自身的模块时钟外，显示模块还有一个像素时钟，相应的底层寄存器的设计也不同，所以显示相关的几个时钟重新设计了底层驱动。</p>
|
2025-04-23 17:54:31 +08:00
|
|
|
|
</li>
|
|
|
|
|
|
<li class="- topic/li li" data-ofbid="d196147e350__20250409171053">
|
|
|
|
|
|
<p class="- topic/p p" data-ofbid="d196147e352__20250409171053"><span class="+ topic/keyword pr-d/parmname keyword parmname">PLL clock</span>：实现了 CMU 的 PLL 时钟驱动。PLL 是一种能够产生高频时钟信号的电路。PLL
|
2025-01-23 16:37:00 +08:00
|
|
|
|
可以将一个低频率的参考时钟信号乘以一个整数倍的频率因子，从而得到一个高频率的时钟信号。</p>
|
2025-04-23 17:54:31 +08:00
|
|
|
|
</li>
|
|
|
|
|
|
</ul></div>
|
|
|
|
|
|
<div class="- topic/p p" data-ofbid="d196147e359__20250409171053">下列表格列出了各种时钟分类对应的时钟树：<div class="table-container"><table class="- topic/table table colwidths-given docutils align-default frame-all" id="id__table_txf_3l4_mdc" data-ofbid="id__table_txf_3l4_mdc" data-cols="2"><caption></caption><colgroup><col style="width:41.32231404958678%"/><col style="width:58.67768595041321%"/></colgroup><thead class="- topic/thead thead">
|
|
|
|
|
|
<tr class="- topic/row">
|
|
|
|
|
|
<th class="- topic/entry entry colsep-1 rowsep-1" id="id__table_txf_3l4_mdc__entry__1"><p class="- topic/p p" data-ofbid="d196147e374__20250409171053">类型</p></th>
|
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|
|
<th class="- topic/entry entry colsep-0 rowsep-1" id="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e378__20250409171053">时钟</p></th>
|
|
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|
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|
</tr>
|
|
|
|
|
|
</thead><tbody class="- topic/tbody tbody">
|
|
|
|
|
|
<tr class="- topic/row">
|
|
|
|
|
|
<td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_txf_3l4_mdc__entry__1" rowspan="3"><p class="- topic/p p" data-ofbid="d196147e388__20250409171053">Fixed rate clock</p></td>
|
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|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e392__20250409171053">OSC24M</p></td>
|
|
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|
|
|
</tr>
|
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|
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|
<tr class="- topic/row">
|
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|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e399__20250409171053">OSC32K</p></td>
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|
</tr>
|
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|
<tr class="- topic/row">
|
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|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e406__20250409171053">RC1M</p></td>
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|
</tr>
|
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|
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|
<tr class="- topic/row">
|
|
|
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|
<td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_txf_3l4_mdc__entry__1" rowspan="31"><p class="- topic/p p" data-ofbid="d196147e413__20250409171053">Fixed parent clock</p></td>
|
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|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e417__20250409171053">CLK_DMA</p></td>
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|
</tr>
|
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|
<tr class="- topic/row">
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|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e424__20250409171053">CLK_CE</p></td>
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</tr>
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<tr class="- topic/row">
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e432__20250409171053">CLK_USBD</p></td>
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</tr>
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<tr class="- topic/row">
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e439__20250409171053">CLK_USBH0-1</p></td>
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</tr>
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<tr class="- topic/row">
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e446__20250409171053">CLK_USB_PHY0-1</p></td>
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</tr>
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<tr class="- topic/row">
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e453__20250409171053">CLK_GMAC0-1</p></td>
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</tr>
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<tr class="- topic/row">
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e460__20250409171053">CLK_SPI0-1</p></td>
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</tr>
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<tr class="- topic/row">
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e467__20250409171053">CLK_SDMMC0-2</p></td>
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</tr>
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<tr class="- topic/row">
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e475__20250409171053">CLK_SYSCON</p></td>
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</tr>
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<tr class="- topic/row">
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e482__20250409171053">CLK_RTC</p></td>
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</tr>
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<tr class="- topic/row">
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e489__20250409171053">CLK_I2S0-1</p></td>
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</tr>
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<tr class="- topic/row">
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e496__20250409171053">CLK_ADDA</p></td>
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</tr>
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<tr class="- topic/row">
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e503__20250409171053">CLK_DE</p></td>
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</tr>
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<tr class="- topic/row">
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e510__20250409171053">CLK_GE</p></td>
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</tr>
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<tr class="- topic/row">
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e518__20250409171053">CLK_VE</p></td>
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</tr>
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<tr class="- topic/row">
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e525__20250409171053">CLK_WDOG</p></td>
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</tr>
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<tr class="- topic/row">
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e532__20250409171053">CLK_SID</p></td>
|
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</tr>
|
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<tr class="- topic/row">
|
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e539__20250409171053">CLK_GTC</p></td>
|
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</tr>
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<tr class="- topic/row">
|
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e546__20250409171053">CLK_GPIO</p></td>
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</tr>
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<tr class="- topic/row">
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e553__20250409171053">CLK_UART0-7</p></td>
|
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</tr>
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<tr class="- topic/row">
|
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e561__20250409171053">CLK_I2C0-3</p></td>
|
|
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</tr>
|
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<tr class="- topic/row">
|
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e568__20250409171053">CLK_CAN0-1</p></td>
|
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</tr>
|
|
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<tr class="- topic/row">
|
|
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e575__20250409171053">CLK_PWM</p></td>
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</tr>
|
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<tr class="- topic/row">
|
|
|
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e582__20250409171053">CLK_ADCIM</p></td>
|
|
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|
</tr>
|
|
|
|
|
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<tr class="- topic/row">
|
|
|
|
|
|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e589__20250409171053">CLK_GPADC</p></td>
|
|
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|
|
</tr>
|
|
|
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<tr class="- topic/row">
|
|
|
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|
|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e596__20250409171053">CLK_RTP</p></td>
|
|
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|
|
|
</tr>
|
|
|
|
|
|
<tr class="- topic/row">
|
|
|
|
|
|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e604__20250409171053">CLK_TSEN</p></td>
|
|
|
|
|
|
</tr>
|
|
|
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|
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<tr class="- topic/row">
|
|
|
|
|
|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e611__20250409171053">CLK_CIR</p></td>
|
|
|
|
|
|
</tr>
|
|
|
|
|
|
<tr class="- topic/row">
|
|
|
|
|
|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e618__20250409171053">CLK_RGB</p></td>
|
|
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|
|
|
</tr>
|
|
|
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|
|
<tr class="- topic/row">
|
|
|
|
|
|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e625__20250409171053">CLK_LVDS</p></td>
|
|
|
|
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|
</tr>
|
|
|
|
|
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<tr class="- topic/row">
|
|
|
|
|
|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e632__20250409171053">CLK_MIPIDSI</p></td>
|
|
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|
|
</tr>
|
|
|
|
|
|
<tr class="- topic/row">
|
|
|
|
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|
<td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_txf_3l4_mdc__entry__1" rowspan="9"><p class="- topic/p p" data-ofbid="d196147e639__20250409171053">Multi parent clock</p></td>
|
|
|
|
|
|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e643__20250409171053">CLK_CPU</p></td>
|
|
|
|
|
|
</tr>
|
|
|
|
|
|
<tr class="- topic/row">
|
|
|
|
|
|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e651__20250409171053">CLK_AHB0</p></td>
|
|
|
|
|
|
</tr>
|
|
|
|
|
|
<tr class="- topic/row">
|
|
|
|
|
|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e658__20250409171053">CLK_APB0</p></td>
|
|
|
|
|
|
</tr>
|
|
|
|
|
|
<tr class="- topic/row">
|
|
|
|
|
|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e665__20250409171053">CLK_APB1</p></td>
|
|
|
|
|
|
</tr>
|
|
|
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|
|
<tr class="- topic/row">
|
|
|
|
|
|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e672__20250409171053">CLK_AXI0</p></td>
|
|
|
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|
|
</tr>
|
|
|
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|
|
<tr class="- topic/row">
|
|
|
|
|
|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e679__20250409171053">CLK_OUT0</p></td>
|
|
|
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|
</tr>
|
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|
<tr class="- topic/row">
|
|
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|
|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e686__20250409171053">CLK_OUT1</p></td>
|
|
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|
|
</tr>
|
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|
<tr class="- topic/row">
|
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|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e694__20250409171053">CLK_OUT2</p></td>
|
|
|
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|
</tr>
|
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<tr class="- topic/row">
|
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e701__20250409171053">CLK_OUT3</p></td>
|
|
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|
</tr>
|
|
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<tr class="- topic/row">
|
|
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|
<td class="- topic/entry entry colsep-1 rowsep-1" headers="id__table_txf_3l4_mdc__entry__1" rowspan="5"><p class="- topic/p p" data-ofbid="d196147e708__20250409171053">PLL clock</p></td>
|
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|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e712__20250409171053">CLK_PLL_INT0</p></td>
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</tr>
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<tr class="- topic/row">
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e719__20250409171053">CLK_PLL_INT1</p></td>
|
|
|
|
|
|
</tr>
|
|
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|
<tr class="- topic/row">
|
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e726__20250409171053">CLK_PLL_FRA0</p></td>
|
|
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|
|
|
</tr>
|
|
|
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<tr class="- topic/row">
|
|
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|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e733__20250409171053">CLK_PLL_FRA1</p></td>
|
|
|
|
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|
</tr>
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<tr class="- topic/row">
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<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e741__20250409171053">CLK_PLL_FRA2</p></td>
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|
|
</tr>
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<tr class="- topic/row">
|
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<td class="- topic/entry entry colsep-1 rowsep-0" headers="id__table_txf_3l4_mdc__entry__1" rowspan="2"><p class="- topic/p p" data-ofbid="d196147e748__20250409171053">Disp clock</p></td>
|
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|
<td class="- topic/entry entry colsep-0 rowsep-1" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e752__20250409171053">CLK_PIX</p></td>
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</tr>
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<tr class="- topic/row">
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<td class="- topic/entry entry colsep-0 rowsep-0" headers="id__table_txf_3l4_mdc__entry__2"><p class="- topic/p p" data-ofbid="d196147e759__20250409171053">CLK_SCLK</p></td>
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|
</tr>
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|
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|
</tbody></table></div></div>
|
2025-01-23 16:37:00 +08:00
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</div>
|
2025-04-23 17:54:31 +08:00
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</section></div>
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</article></main></div>
|
2025-01-23 16:37:00 +08:00
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2025-04-23 17:54:31 +08:00
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<div class=" wh_child_links d-print-none "><nav aria-label="Child Links" role="navigation" class="- topic/related-links related-links"><ul class="ullinks"><li class="- topic/link link ulchildlink"><strong><a href="../../../topics/sdk/cmu/cmu-key-procedures.html">关键流程设计</a></strong></li><li class="- topic/link link ulchildlink"><strong><a href="../../../topics/sdk/cmu/cmu-data-structure-design.html">数据结构设计</a></strong></li><li class="- topic/link link ulchildlink"><strong><a href="../../../topics/sdk/cmu/cmu-interface-design-2.html">接口设计</a></strong></li></ul></nav></div>
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2025-01-23 16:37:00 +08:00
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和 Reset 类型</a></div></li><li class="section-item"><div class="section-title"><a href="#id__section_itz_c44_mdc" data-tocid="id__section_itz_c44_mdc">时钟树</a></div></li></ul></div>
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.p3 {
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font-family: "Lucida Console", "Courier New", monospace;
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}
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2025-04-23 17:54:31 +08:00
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</style>
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2025-01-23 16:37:00 +08:00
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<div class="webhelp.fragment.footer">
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2025-04-23 17:54:31 +08:00
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<p class="p1">Copyright © 2019-2025 广东匠芯创科技有限公司. All rights reserved.</p>
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</div>
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<div>
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2025-01-23 16:37:00 +08:00
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<div class="generation_time">
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2025-04-23 17:54:31 +08:00
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Update Time: 2025-04-09
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2025-01-23 16:37:00 +08:00
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</div>
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2025-04-23 17:54:31 +08:00
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</div>
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2025-01-23 16:37:00 +08:00
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</div>
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</footer>
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<div id="go2top" class="d-print-none">
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<span class="oxy-icon oxy-icon-up"></span>
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</div>
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<div id="modal_img_large" class="modal">
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<span class="close oxy-icon oxy-icon-remove"></span>
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<div id="modal_img_container"></div>
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<div id="caption"></div>
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</div>
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<script src="${pd}/publishing/publishing-styles-AIC-template/js/custom.js" defer="defer"></script>
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</body>
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</html>
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