mirror of
https://gitee.com/Vancouver2017/luban-lite.git
synced 2025-12-24 13:08:55 +00:00
503 lines
15 KiB
C
503 lines
15 KiB
C
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#include "usbd_core.h"
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#include "usb_fsdev_reg.h"
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#ifndef USBD_IRQHandler
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#define USBD_IRQHandler USB_LP_CAN1_RX0_IRQHandler //use actual usb irq name instead
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#endif
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#ifndef USB_BASE
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#define USB_BASE (0x40005C00UL) /*!< USB_IP Peripheral Registers base address */
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#endif
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#ifndef USB_NUM_BIDIR_ENDPOINTS
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#define USB_NUM_BIDIR_ENDPOINTS 8
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#endif
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#ifndef USB_RAM_SIZE
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#define USB_RAM_SIZE 512
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#endif
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#define USB ((USB_TypeDef *)USB_BASE)
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#define USB_BTABLE_SIZE (8 * USB_NUM_BIDIR_ENDPOINTS)
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static void fsdev_write_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
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static void fsdev_read_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
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/* Endpoint state */
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struct fsdev_ep_state {
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/** Endpoint max packet size */
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uint16_t ep_mps;
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/** Endpoint Transfer Type.
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* May be Bulk, Interrupt, Control or Isochronous
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*/
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uint8_t ep_type;
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uint8_t ep_stalled; /** Endpoint stall flag */
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uint16_t ep_pma_buf_len; /** Previously allocated buffer size */
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uint16_t ep_pma_addr; /**ep pmd allocated addr*/
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};
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/* Driver state */
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struct fsdev_udc {
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volatile uint8_t dev_addr; /*!< USB Address */
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volatile uint32_t pma_offset; /*!< pma offset */
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struct fsdev_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters*/
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struct fsdev_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */
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} g_fsdev_udc;
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__WEAK void usb_dc_low_level_init(void)
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{
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}
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__WEAK void usb_dc_low_level_deinit(void)
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{
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}
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int usb_dc_init(void)
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{
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memset(&g_fsdev_udc, 0, sizeof(struct fsdev_udc));
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g_fsdev_udc.pma_offset = USB_BTABLE_SIZE;
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usb_dc_low_level_init();
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/* Init Device */
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/* CNTR_FRES = 1 */
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USB->CNTR = (uint16_t)USB_CNTR_FRES;
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/* CNTR_FRES = 0 */
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USB->CNTR = 0U;
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/* Clear pending interrupts */
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USB->ISTR = 0U;
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/*Set Btable Address*/
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USB->BTABLE = BTABLE_ADDRESS;
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uint32_t winterruptmask;
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/* Set winterruptmask variable */
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winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
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USB_CNTR_SUSPM | USB_CNTR_ERRM |
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USB_CNTR_SOFM | USB_CNTR_ESOFM |
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USB_CNTR_RESETM;
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/* Set interrupt mask */
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USB->CNTR = (uint16_t)winterruptmask;
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return 0;
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}
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int usb_dc_deinit(void)
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{
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/* disable all interrupts and force USB reset */
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USB->CNTR = (uint16_t)USB_CNTR_FRES;
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/* clear interrupt status register */
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USB->ISTR = 0U;
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/* switch-off device */
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USB->CNTR = (uint16_t)(USB_CNTR_FRES | USB_CNTR_PDWN);
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usb_dc_low_level_deinit();
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return 0;
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}
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int usbd_set_address(const uint8_t addr)
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{
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if (addr == 0U) {
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/* set device address and enable function */
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USB->DADDR = (uint16_t)USB_DADDR_EF;
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}
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g_fsdev_udc.dev_addr = addr;
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return 0;
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}
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int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg)
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{
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uint8_t ep_idx = USB_EP_GET_IDX(ep_cfg->ep_addr);
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if (!ep_cfg) {
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return -1;
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}
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uint16_t wEpRegVal;
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/* initialize Endpoint */
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switch (ep_cfg->ep_type) {
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case USB_ENDPOINT_TYPE_CONTROL:
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wEpRegVal = USB_EP_CONTROL;
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break;
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case USB_ENDPOINT_TYPE_BULK:
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wEpRegVal = USB_EP_BULK;
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break;
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case USB_ENDPOINT_TYPE_INTERRUPT:
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wEpRegVal = USB_EP_INTERRUPT;
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break;
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case USB_ENDPOINT_TYPE_ISOCHRONOUS:
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wEpRegVal = USB_EP_ISOCHRONOUS;
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break;
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default:
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break;
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}
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PCD_SET_EPTYPE(USB, ep_idx, wEpRegVal);
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PCD_SET_EP_ADDRESS(USB, ep_idx, ep_idx);
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if (USB_EP_DIR_IS_OUT(ep_cfg->ep_addr)) {
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g_fsdev_udc.out_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
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g_fsdev_udc.out_ep[ep_idx].ep_type = ep_cfg->ep_type;
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if (g_fsdev_udc.out_ep[ep_idx].ep_mps > g_fsdev_udc.out_ep[ep_idx].ep_pma_buf_len) {
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if (g_fsdev_udc.pma_offset + g_fsdev_udc.out_ep[ep_idx].ep_mps > USB_RAM_SIZE) {
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return -1;
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}
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g_fsdev_udc.out_ep[ep_idx].ep_pma_buf_len = ep_cfg->ep_mps;
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g_fsdev_udc.out_ep[ep_idx].ep_pma_addr = g_fsdev_udc.pma_offset;
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/*Set the endpoint Receive buffer address */
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PCD_SET_EP_RX_ADDRESS(USB, ep_idx, g_fsdev_udc.pma_offset);
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g_fsdev_udc.pma_offset += ep_cfg->ep_mps;
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}
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/*Set the endpoint Receive buffer counter*/
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PCD_SET_EP_RX_CNT(USB, ep_idx, ep_cfg->ep_mps);
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PCD_CLEAR_RX_DTOG(USB, ep_idx);
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/* Configure VALID status for the Endpoint*/
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PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID);
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} else {
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g_fsdev_udc.in_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
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g_fsdev_udc.in_ep[ep_idx].ep_type = ep_cfg->ep_type;
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if (g_fsdev_udc.in_ep[ep_idx].ep_mps > g_fsdev_udc.in_ep[ep_idx].ep_pma_buf_len) {
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if (g_fsdev_udc.pma_offset + g_fsdev_udc.in_ep[ep_idx].ep_mps > USB_RAM_SIZE) {
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return -1;
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}
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g_fsdev_udc.in_ep[ep_idx].ep_pma_buf_len = ep_cfg->ep_mps;
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g_fsdev_udc.in_ep[ep_idx].ep_pma_addr = g_fsdev_udc.pma_offset;
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/*Set the endpoint Transmit buffer address */
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PCD_SET_EP_TX_ADDRESS(USB, ep_idx, g_fsdev_udc.pma_offset);
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g_fsdev_udc.pma_offset += ep_cfg->ep_mps;
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}
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PCD_CLEAR_TX_DTOG(USB, ep_idx);
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if (ep_cfg->ep_type != USB_ENDPOINT_TYPE_ISOCHRONOUS) {
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/* Configure NAK status for the Endpoint */
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PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_NAK);
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} else {
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/* Configure TX Endpoint to disabled state */
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PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_DIS);
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}
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}
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return 0;
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}
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int usbd_ep_close(const uint8_t ep)
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{
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uint8_t ep_idx = USB_EP_GET_IDX(ep);
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if (USB_EP_DIR_IS_OUT(ep)) {
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PCD_CLEAR_RX_DTOG(USB, ep_idx);
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/* Configure DISABLE status for the Endpoint*/
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PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_DIS);
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} else {
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PCD_CLEAR_TX_DTOG(USB, ep_idx);
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/* Configure DISABLE status for the Endpoint*/
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PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_DIS);
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}
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return 0;
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}
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int usbd_ep_set_stall(const uint8_t ep)
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{
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uint8_t ep_idx = USB_EP_GET_IDX(ep);
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if (USB_EP_DIR_IS_OUT(ep)) {
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PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_STALL);
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} else {
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PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_STALL);
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}
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return 0;
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}
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int usbd_ep_clear_stall(const uint8_t ep)
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{
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uint8_t ep_idx = USB_EP_GET_IDX(ep);
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if (USB_EP_DIR_IS_OUT(ep)) {
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PCD_CLEAR_RX_DTOG(USB, ep_idx);
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/* Configure VALID status for the Endpoint */
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PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID);
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} else {
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PCD_CLEAR_TX_DTOG(USB, ep_idx);
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if (g_fsdev_udc.in_ep[ep_idx].ep_type != USB_ENDPOINT_TYPE_ISOCHRONOUS) {
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/* Configure NAK status for the Endpoint */
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PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_NAK);
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}
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}
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return 0;
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}
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int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled)
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{
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if (USB_EP_DIR_IS_OUT(ep)) {
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} else {
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}
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return 0;
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}
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int usbd_ep_write(const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes)
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{
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uint8_t ep_idx = USB_EP_GET_IDX(ep);
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if (!data && data_len) {
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return -1;
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}
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while (PCD_GET_EP_TX_STATUS(USB, ep_idx) == USB_EP_TX_VALID) {
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}
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if (!data_len) {
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PCD_SET_EP_TX_CNT(USB, ep_idx, (uint16_t)0);
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PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_VALID);
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return 0;
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}
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if (data_len > g_fsdev_udc.in_ep[ep_idx].ep_mps) {
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data_len = g_fsdev_udc.in_ep[ep_idx].ep_mps;
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}
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fsdev_write_pma(USB, (uint8_t *)data, g_fsdev_udc.in_ep[ep_idx].ep_pma_addr, (uint16_t)data_len);
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PCD_SET_EP_TX_CNT(USB, ep_idx, (uint16_t)data_len);
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PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_VALID);
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if (ret_bytes) {
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*ret_bytes = data_len;
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}
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return 0;
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}
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int usbd_ep_read(const uint8_t ep, uint8_t *data, uint32_t max_data_len, uint32_t *read_bytes)
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{
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uint8_t ep_idx = USB_EP_GET_IDX(ep);
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uint32_t read_count;
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if (!data && max_data_len) {
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return -1;
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}
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if (!max_data_len) {
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if (ep_idx != 0x00) {
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PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID);
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}
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return 0;
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}
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read_count = PCD_GET_EP_RX_CNT(USB, ep_idx);
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read_count = MIN(read_count, max_data_len);
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fsdev_read_pma(USB, (uint8_t *)data, g_fsdev_udc.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count);
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if (read_bytes) {
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*read_bytes = read_count;
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}
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return 0;
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}
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void USBD_IRQHandler(void)
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{
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uint16_t wIstr, wEPVal;
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uint8_t epindex;
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wIstr = USB->ISTR;
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uint16_t store_ep[8];
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if (wIstr & USB_ISTR_CTR) {
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while ((USB->ISTR & USB_ISTR_CTR) != 0U) {
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wIstr = USB->ISTR;
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/* extract highest priority endpoint number */
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epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
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if (epindex == 0U) {
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/* Decode and service control endpoint interrupt */
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/* DIR bit = origin of the interrupt */
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if ((wIstr & USB_ISTR_DIR) == 0U) {
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/* DIR = 0 */
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/* DIR = 0 => IN int */
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/* DIR = 0 implies that (EP_CTR_TX = 1) always */
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PCD_CLEAR_TX_EP_CTR(USB, 0);
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usbd_event_notify_handler(USBD_EVENT_EP0_IN_NOTIFY, NULL);
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if ((g_fsdev_udc.dev_addr > 0U) && (PCD_GET_EP_TX_CNT(USB, 0) == 0U)) {
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USB->DADDR = ((uint16_t)g_fsdev_udc.dev_addr | USB_DADDR_EF);
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g_fsdev_udc.dev_addr = 0U;
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}
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} else {
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/* DIR = 1 */
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/* DIR = 1 & CTR_RX => SETUP or OUT int */
|
||
|
|
/* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
|
||
|
|
|
||
|
|
wEPVal = PCD_GET_ENDPOINT(USB, 0);
|
||
|
|
|
||
|
|
if ((wEPVal & USB_EP_SETUP) != 0U) {
|
||
|
|
/* SETUP bit kept frozen while CTR_RX = 1 */
|
||
|
|
PCD_CLEAR_RX_EP_CTR(USB, 0);
|
||
|
|
|
||
|
|
/* Process SETUP Packet*/
|
||
|
|
usbd_event_notify_handler(USBD_EVENT_SETUP_NOTIFY, NULL);
|
||
|
|
PCD_SET_EP_RX_STATUS(USB, 0, USB_EP_RX_VALID);
|
||
|
|
} else if ((wEPVal & USB_EP_CTR_RX) != 0U) {
|
||
|
|
PCD_CLEAR_RX_EP_CTR(USB, 0);
|
||
|
|
/* Process Control Data OUT Packet */
|
||
|
|
usbd_event_notify_handler(USBD_EVENT_EP0_OUT_NOTIFY, NULL);
|
||
|
|
PCD_SET_EP_RX_STATUS(USB, 0, USB_EP_RX_VALID);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
/* Decode and service non control endpoints interrupt */
|
||
|
|
/* process related endpoint register */
|
||
|
|
wEPVal = PCD_GET_ENDPOINT(USB, epindex);
|
||
|
|
|
||
|
|
if ((wEPVal & USB_EP_CTR_RX) != 0U) {
|
||
|
|
/* clear int flag */
|
||
|
|
PCD_CLEAR_RX_EP_CTR(USB, epindex);
|
||
|
|
usbd_event_notify_handler(USBD_EVENT_EP_OUT_NOTIFY, (void *)(epindex & 0x7f));
|
||
|
|
}
|
||
|
|
|
||
|
|
if ((wEPVal & USB_EP_CTR_TX) != 0U) {
|
||
|
|
/* clear int flag */
|
||
|
|
PCD_CLEAR_TX_EP_CTR(USB, epindex);
|
||
|
|
usbd_event_notify_handler(USBD_EVENT_EP_IN_NOTIFY, (void *)(epindex | 0x80));
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
if (wIstr & USB_ISTR_RESET) {
|
||
|
|
memset(&g_fsdev_udc, 0, sizeof(struct fsdev_udc));
|
||
|
|
g_fsdev_udc.pma_offset = USB_BTABLE_SIZE;
|
||
|
|
usbd_event_notify_handler(USBD_EVENT_RESET, NULL);
|
||
|
|
USB->ISTR &= (uint16_t)(~USB_ISTR_RESET);
|
||
|
|
}
|
||
|
|
if (wIstr & USB_ISTR_PMAOVR) {
|
||
|
|
USB->ISTR &= (uint16_t)(~USB_ISTR_PMAOVR);
|
||
|
|
}
|
||
|
|
if (wIstr & USB_ISTR_ERR) {
|
||
|
|
USB->ISTR &= (uint16_t)(~USB_ISTR_ERR);
|
||
|
|
}
|
||
|
|
if (wIstr & USB_ISTR_WKUP) {
|
||
|
|
USB->CNTR &= (uint16_t) ~(USB_CNTR_LP_MODE);
|
||
|
|
USB->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
|
||
|
|
|
||
|
|
USB->ISTR &= (uint16_t)(~USB_ISTR_WKUP);
|
||
|
|
}
|
||
|
|
if (wIstr & USB_ISTR_SUSP) {
|
||
|
|
/* WA: To Clear Wakeup flag if raised with suspend signal */
|
||
|
|
|
||
|
|
/* Store Endpoint register */
|
||
|
|
for (uint8_t i = 0U; i < 8U; i++) {
|
||
|
|
store_ep[i] = PCD_GET_ENDPOINT(USB, i);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* FORCE RESET */
|
||
|
|
USB->CNTR |= (uint16_t)(USB_CNTR_FRES);
|
||
|
|
|
||
|
|
/* CLEAR RESET */
|
||
|
|
USB->CNTR &= (uint16_t)(~USB_CNTR_FRES);
|
||
|
|
|
||
|
|
/* wait for reset flag in ISTR */
|
||
|
|
while ((USB->ISTR & USB_ISTR_RESET) == 0U) {
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Clear Reset Flag */
|
||
|
|
USB->ISTR &= (uint16_t)(~USB_ISTR_RESET);
|
||
|
|
/* Restore Registre */
|
||
|
|
for (uint8_t i = 0U; i < 8U; i++) {
|
||
|
|
PCD_SET_ENDPOINT(USB, i, store_ep[i]);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Force low-power mode in the macrocell */
|
||
|
|
USB->CNTR |= (uint16_t)USB_CNTR_FSUSP;
|
||
|
|
|
||
|
|
/* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
|
||
|
|
USB->ISTR &= (uint16_t)(~USB_ISTR_SUSP);
|
||
|
|
|
||
|
|
USB->CNTR |= (uint16_t)USB_CNTR_LP_MODE;
|
||
|
|
}
|
||
|
|
if (wIstr & USB_ISTR_SOF) {
|
||
|
|
USB->ISTR &= (uint16_t)(~USB_ISTR_SOF);
|
||
|
|
}
|
||
|
|
if (wIstr & USB_ISTR_ESOF) {
|
||
|
|
USB->ISTR &= (uint16_t)(~USB_ISTR_ESOF);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void fsdev_write_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
|
||
|
|
{
|
||
|
|
uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
|
||
|
|
uint32_t BaseAddr = (uint32_t)USBx;
|
||
|
|
uint32_t i, temp1, temp2;
|
||
|
|
__IO uint16_t *pdwVal;
|
||
|
|
uint8_t *pBuf = pbUsrBuf;
|
||
|
|
|
||
|
|
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
|
||
|
|
|
||
|
|
for (i = n; i != 0U; i--) {
|
||
|
|
temp1 = *pBuf;
|
||
|
|
pBuf++;
|
||
|
|
temp2 = temp1 | ((uint16_t)((uint16_t)*pBuf << 8));
|
||
|
|
*pdwVal = (uint16_t)temp2;
|
||
|
|
pdwVal++;
|
||
|
|
|
||
|
|
#if PMA_ACCESS > 1U
|
||
|
|
pdwVal++;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
pBuf++;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Copy data from packet memory area (PMA) to user memory buffer
|
||
|
|
* @param USBx USB peripheral instance register address.
|
||
|
|
* @param pbUsrBuf pointer to user memory area.
|
||
|
|
* @param wPMABufAddr address into PMA.
|
||
|
|
* @param wNBytes no. of bytes to be copied.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
static void fsdev_read_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
|
||
|
|
{
|
||
|
|
uint32_t n = (uint32_t)wNBytes >> 1;
|
||
|
|
uint32_t BaseAddr = (uint32_t)USBx;
|
||
|
|
uint32_t i, temp;
|
||
|
|
__IO uint16_t *pdwVal;
|
||
|
|
uint8_t *pBuf = pbUsrBuf;
|
||
|
|
|
||
|
|
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
|
||
|
|
|
||
|
|
for (i = n; i != 0U; i--) {
|
||
|
|
temp = *(__IO uint16_t *)pdwVal;
|
||
|
|
pdwVal++;
|
||
|
|
*pBuf = (uint8_t)((temp >> 0) & 0xFFU);
|
||
|
|
pBuf++;
|
||
|
|
*pBuf = (uint8_t)((temp >> 8) & 0xFFU);
|
||
|
|
pBuf++;
|
||
|
|
|
||
|
|
#if PMA_ACCESS > 1U
|
||
|
|
pdwVal++;
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
if ((wNBytes % 2U) != 0U) {
|
||
|
|
temp = *pdwVal;
|
||
|
|
*pBuf = (uint8_t)((temp >> 0) & 0xFFU);
|
||
|
|
}
|
||
|
|
}
|