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V1.0.5

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This commit is contained in:
刘可亮
2024-06-04 19:00:30 +08:00
parent 990c72f5be
commit 0a13af6a1d
1668 changed files with 342810 additions and 37726 deletions
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36
bsp/artinchip/hal/adcim/hal_adcim.c
View File

@@ -37,6 +37,7 @@
#define ADCIM_CAL_ADC_STANDARD_VAL 0x800
#define AIC_ADC_MAX_VAL 0xFFF
#define AIC_VOLTAGE_ACCURACY 10000
#define ADCIM_CALCSR_NUM 6
#ifdef AIC_CHIP_D12X
#define ADCIM_CAL_ADC_OFFSET_MISMATCH 0x8
@@ -119,18 +120,43 @@ int hal_adcim_calibration_set(unsigned int val)
return 0;
}
/*
* The calibration value is taken six times and the average value is obtained
* after removing the maximum and minimum values, in order to ensure the
* stability of calibration
*/
u32 hal_adcim_auto_calibration(void)
{
u32 flag = 1;
u32 data = 0;
int max = 0;
int min = 0;
u32 cal_array[ADCIM_CALCSR_NUM];
adcim_writel(0x08002f03, ADCIM_CALCSR);//auto cal
do {
flag = adcim_readl(ADCIM_CALCSR) & 0x00000001;
} while (flag);
for (int i = 0; i < ADCIM_CALCSR_NUM; i++) {
adcim_writel(0x08002f03, ADCIM_CALCSR);//auto cal
do {
flag = adcim_readl(ADCIM_CALCSR) & 0x00000001;
} while (flag);
data = (adcim_readl(ADCIM_CALCSR) >> 16) & 0xfff;
cal_array[i] = (adcim_readl(ADCIM_CALCSR) >> 16) & 0xfff;
if (cal_array[i] > max)
max = cal_array[i];
if (i == 0) {
min = cal_array[0];
} else if (cal_array[i] < min) {
min = cal_array[i];
}
data += cal_array[i];
pr_debug("[%d]cal_data %d\n", i, cal_array[i]);
}
data = (data - min - max) / (ADCIM_CALCSR_NUM - 2);
pr_debug("max %d min %d, latest_data %d\n", max, min, data);
return data;
}

2
bsp/artinchip/hal/audio/hal_audio.c
View File

@@ -425,6 +425,8 @@ void hal_audio_dmic_start(aic_audio_ctrl *codec)
hal_audio_flush_dmic_fifo(codec);
/* Enable RX global */
hal_audio_enable_rx_global(codec);
/* Enable DMIC ADOUT SHIFT */
hal_audio_enable_dmic_adout_shift(codec);
/* Enable DMIC DRQ */
hal_audio_dmic_enable_drq(codec);
}

46
bsp/artinchip/hal/cmu/aic_hal_clk.c
View File

@@ -15,14 +15,14 @@ int hal_clk_enable_deassertrst(uint32_t clk_id)
{
struct aic_clk_comm_cfg *cfg;
CHECK_PARAM(clk_id < AIC_CLK_END && clk_id > 0, -EINVAL);
CHECK_PARAM(clk_id < AIC_CLK_NUM && clk_id > 0, -EINVAL);
cfg = (struct aic_clk_comm_cfg *)aic_clk_cfgs[clk_id];
CHECK_PARAM(cfg != NULL && cfg->ops != NULL &&
cfg->ops->enable_clk_deassert_rst != NULL,
-EINVAL);
cfg->enable_count = 1;
cfg->enable = 1;
return (cfg->ops->enable_clk_deassert_rst(cfg));
}
@@ -30,14 +30,14 @@ int hal_clk_disable_assertrst(uint32_t clk_id)
{
struct aic_clk_comm_cfg *cfg;
CHECK_PARAM(clk_id < AIC_CLK_END && clk_id > 0, -EINVAL);
CHECK_PARAM(clk_id < AIC_CLK_NUM && clk_id > 0, -EINVAL);
cfg = (struct aic_clk_comm_cfg *)aic_clk_cfgs[clk_id];
CHECK_PARAM(cfg != NULL && cfg->ops != NULL &&
cfg->ops->disable_clk_assert_rst != NULL,
-EINVAL);
cfg->enable_count = 0;
cfg->enable = 0;
cfg->ops->disable_clk_assert_rst(cfg);
return 0;
}
@@ -46,13 +46,13 @@ int hal_clk_enable(uint32_t clk_id)
{
struct aic_clk_comm_cfg *cfg;
CHECK_PARAM(clk_id < AIC_CLK_END && clk_id > 0, -EINVAL);
CHECK_PARAM(clk_id < AIC_CLK_NUM && clk_id > 0, -EINVAL);
cfg = (struct aic_clk_comm_cfg *)aic_clk_cfgs[clk_id];
CHECK_PARAM(cfg != NULL && cfg->ops != NULL && cfg->ops->enable != NULL,
-EINVAL);
cfg->enable_count = 1;
cfg->enable = 1;
return (cfg->ops->enable(cfg));
}
@@ -60,13 +60,13 @@ int hal_clk_disable(uint32_t clk_id)
{
struct aic_clk_comm_cfg *cfg;
CHECK_PARAM(clk_id < AIC_CLK_END && clk_id > 0, -EINVAL);
CHECK_PARAM(clk_id < AIC_CLK_NUM && clk_id > 0, -EINVAL);
cfg = (struct aic_clk_comm_cfg *)aic_clk_cfgs[clk_id];
CHECK_PARAM(cfg != NULL && cfg->ops != NULL && cfg->ops->disable != NULL,
-EINVAL);
cfg->enable_count = 0;
cfg->enable = 0;
cfg->ops->disable(cfg);
return 0;
@@ -77,15 +77,15 @@ int hal_clk_is_enabled(uint32_t clk_id)
uint32_t parent_clk_id;
struct aic_clk_comm_cfg *cfg;
CHECK_PARAM(clk_id < AIC_CLK_END && clk_id > 0, -EINVAL);
CHECK_PARAM(clk_id < AIC_CLK_NUM && clk_id > 0, -EINVAL);
cfg = (struct aic_clk_comm_cfg *)aic_clk_cfgs[clk_id];
CHECK_PARAM(cfg != NULL && cfg->ops != NULL, -EINVAL);
if (cfg->ops->is_enabled == NULL) {
parent_clk_id = hal_clk_get_parent(clk_id);
cfg->enable_count = hal_clk_is_enabled(parent_clk_id);
return cfg->enable_count;
cfg->enable = hal_clk_is_enabled(parent_clk_id);
return cfg->enable;
}
return (cfg->ops->is_enabled(cfg));
}
@@ -95,7 +95,7 @@ int hal_clk_set_rate(uint32_t clk_id, unsigned long rate,
{
struct aic_clk_comm_cfg *cfg;
CHECK_PARAM(clk_id < AIC_CLK_END && clk_id > 0, -EINVAL);
CHECK_PARAM(clk_id < AIC_CLK_NUM && clk_id > 0, -EINVAL);
cfg = (struct aic_clk_comm_cfg *)aic_clk_cfgs[clk_id];
CHECK_PARAM(cfg != NULL && cfg->ops != NULL && cfg->ops->set_rate != NULL,
@@ -108,7 +108,7 @@ unsigned long hal_clk_recalc_rate(uint32_t clk_id, unsigned long parent_rate)
{
struct aic_clk_comm_cfg *cfg;
CHECK_PARAM(clk_id < AIC_CLK_END && clk_id > 0, -EINVAL);
CHECK_PARAM(clk_id < AIC_CLK_NUM && clk_id > 0, -EINVAL);
cfg = (struct aic_clk_comm_cfg *)aic_clk_cfgs[clk_id];
CHECK_PARAM(cfg != NULL && cfg->ops != NULL &&
@@ -123,7 +123,7 @@ long hal_clk_round_rate(uint32_t clk_id, unsigned long rate,
{
struct aic_clk_comm_cfg *cfg;
CHECK_PARAM(clk_id < AIC_CLK_END && clk_id > 0, -EINVAL);
CHECK_PARAM(clk_id < AIC_CLK_NUM && clk_id > 0, -EINVAL);
cfg = (struct aic_clk_comm_cfg *)aic_clk_cfgs[clk_id];
CHECK_PARAM(cfg != NULL && cfg->ops != NULL && cfg->ops->round_rate != NULL,
@@ -136,7 +136,7 @@ int hal_clk_set_parent(uint32_t clk_id, unsigned int parent_clk_id)
{
struct aic_clk_comm_cfg *cfg;
CHECK_PARAM(clk_id < AIC_CLK_END && clk_id > 0, -EINVAL);
CHECK_PARAM(clk_id < AIC_CLK_NUM && clk_id > 0, -EINVAL);
cfg = (struct aic_clk_comm_cfg *)aic_clk_cfgs[clk_id];
CHECK_PARAM(cfg != NULL && cfg->ops != NULL && cfg->ops->set_parent != NULL,
@@ -149,7 +149,7 @@ unsigned int hal_clk_get_parent(uint32_t clk_id)
{
struct aic_clk_comm_cfg *cfg;
CHECK_PARAM(clk_id < AIC_CLK_END && clk_id > 0, -EINVAL);
CHECK_PARAM(clk_id < AIC_CLK_NUM && clk_id > 0, -EINVAL);
cfg = (struct aic_clk_comm_cfg *)aic_clk_cfgs[clk_id];
CHECK_PARAM(cfg != NULL && cfg->ops != NULL && cfg->ops->get_parent != NULL,
@@ -163,7 +163,7 @@ unsigned long hal_clk_get_freq(uint32_t clk_id)
uint32_t parent_clk_id;
unsigned long parent_freq;
CHECK_PARAM(clk_id < AIC_CLK_END && clk_id > 0, 0);
CHECK_PARAM(clk_id < AIC_CLK_NUM && clk_id > 0, 0);
parent_clk_id = hal_clk_get_parent(clk_id);
@@ -181,7 +181,7 @@ int hal_clk_set_freq(uint32_t clk_id, unsigned long freq)
unsigned long parent_freq;
unsigned long old_freq;
CHECK_PARAM(clk_id < AIC_CLK_END && clk_id > 0, 0);
CHECK_PARAM(clk_id < AIC_CLK_NUM && clk_id > 0, 0);
parent_clk_id = hal_clk_get_parent(clk_id);
parent_freq = hal_clk_get_freq(parent_clk_id);
@@ -198,7 +198,7 @@ int hal_clk_enable_iter(uint32_t clk_id)
{
uint32_t parent_clk_id;
CHECK_PARAM(clk_id < AIC_CLK_END && clk_id > 0, 0);
CHECK_PARAM(clk_id < AIC_CLK_NUM && clk_id > 0, 0);
parent_clk_id = hal_clk_get_parent(clk_id);
@@ -216,7 +216,7 @@ int hal_clk_enable_deassertrst_iter(uint32_t clk_id)
uint32_t parent_clk_id;
int ret = 0;
CHECK_PARAM(clk_id < AIC_CLK_END && clk_id > 0, 0);
CHECK_PARAM(clk_id < AIC_CLK_NUM && clk_id > 0, 0);
parent_clk_id = hal_clk_get_parent(clk_id);
@@ -236,7 +236,7 @@ const char *hal_clk_get_name(uint32_t clk_id)
{
struct aic_clk_comm_cfg *cfg;
CHECK_PARAM(clk_id < AIC_CLK_END && clk_id > 0, 0);
CHECK_PARAM(clk_id < AIC_CLK_NUM && clk_id > 0, 0);
cfg = (struct aic_clk_comm_cfg *)aic_clk_cfgs[clk_id];
CHECK_PARAM(cfg != NULL && cfg->name != NULL, NULL);
@@ -248,11 +248,11 @@ int32_t hal_clk_get_id(char *name)
uint32_t clk_id;
struct aic_clk_comm_cfg *cfg;
for (clk_id = 1; clk_id < AIC_CLK_END; clk_id++) {
for (clk_id = 1; clk_id < AIC_CLK_NUM; clk_id++) {
cfg = (struct aic_clk_comm_cfg *)aic_clk_cfgs[clk_id];
if (cfg == NULL && cfg->name == NULL)
continue;
if(strcmp(name, cfg->name) == 0)
if (strcmp(name, cfg->name) == 0)
return clk_id;
}

2
bsp/artinchip/hal/cmu/aic_hal_clk_def_v10.c
View File

@@ -213,7 +213,7 @@ DISPCLK(CLK_SCLK, "sclk", CLK_PLL_FRA2, PARENT("pll_fra2"), CLK_DISP_REG, 0, 3,
/* Clock cfg array */
const struct aic_clk_comm_cfg *aic_clk_cfgs[AIC_CLK_END] = {
const struct aic_clk_comm_cfg *aic_clk_cfgs[AIC_CLK_NUM] = {
/* Fixed rate clock */
DUMMY_CFG(CLK_DUMMY),
AIC_CLK_CFG(CLK_OSC24M),

2
bsp/artinchip/hal/cmu/aic_hal_clk_def_v11.c
View File

@@ -185,7 +185,7 @@ DISPCLK(CLK_SCLK, "sclk", CLK_PLL_FRA2, PARENT("pll_fra2"), CLK_DISP_REG, 0, 3,
/* Clock cfg array */
const struct aic_clk_comm_cfg *aic_clk_cfgs[AIC_CLK_END] = {
const struct aic_clk_comm_cfg *aic_clk_cfgs[AIC_CLK_NUM] = {
/* Fixed rate clock */
DUMMY_CFG(CLK_DUMMY),
AIC_CLK_CFG(CLK_OSC24M),

2
bsp/artinchip/hal/cmu/aic_hal_clk_def_v12.c
View File

@@ -144,7 +144,7 @@ DISPCLK(CLK_SCLK, "sclk", CLK_PLL_FRA2, PARENT("pll_fra2"), CLK_DISP_REG, 0, 3,
/* Clock cfg array */
const struct aic_clk_comm_cfg *aic_clk_cfgs[AIC_CLK_END] = {
const struct aic_clk_comm_cfg *aic_clk_cfgs[AIC_CLK_NUM] = {
/* Fixed rate clock */
DUMMY_CFG(CLK_DUMMY),
AIC_CLK_CFG(CLK_OSC24M),

57
bsp/artinchip/hal/cmu/aic_hal_pll_clk.c
View File

@@ -10,12 +10,38 @@
#define to_clk_pll(_hw) container_of(_hw, struct aic_clk_pll_cfg, comm)
/* ALL chips:
* Other vco of clock not change
* The vco of pll_fra2 range from (768M-1560M) to (360M~1584M)
*/
static const struct aic_pll_vco vco_arr[] = {
{360000000, 1584000000, "pll_fra2"},
{768000000, 1560000000, "other"},
};
static int clk_pll_wait_lock(void)
{
aic_udelay(200);
return 0;
}
static void clk_vco_select(struct aic_clk_pll_cfg *pll,
unsigned long *min, unsigned long *max)
{
const struct aic_pll_vco *vco;
for (int i = 0; i < (ARRAY_SIZE(vco_arr) - 1); i++) {
vco = &vco_arr[i];
if (pll->id == hal_clk_get_id(vco->name)) {
*min = vco->vco_min;
*max = vco->vco_max;
return;
}
}
*max = vco_arr[ARRAY_SIZE(vco_arr) - 1].vco_max;
*min = vco_arr[ARRAY_SIZE(vco_arr) - 1].vco_min;
}
static inline void clk_pll_bypass(struct aic_clk_pll_cfg *pll, unsigned int bypass)
{
u32 val;
@@ -121,14 +147,19 @@ static long clk_pll_round_rate(struct aic_clk_comm_cfg *comm_cfg,
struct aic_clk_pll_cfg *pll = to_clk_pll(comm_cfg);
u32 factor_n, factor_m, factor_p;
long rrate, vco_rate;
unsigned long pll_vco_min, pll_vco_max;
unsigned long parent_rate = *prate;
if (pll->type == AIC_PLL_FRA)
return rate;
/* The frequency constraint of PLL_VCO is between 768M and 1560M */
if (rate < PLL_VCO_MIN)
factor_m = DIV_ROUND_UP(PLL_VCO_MIN, rate) - 1;
clk_vco_select(pll, &pll_vco_min, &pll_vco_max);
/* The frequency constraint of PLL_VCO is between 768M and 1560M
* But the PLL_VCO of pll_fra2 is between 360M and 1584M
*/
if (rate < pll_vco_min)
factor_m = DIV_ROUND_UP(pll_vco_min, rate) - 1;
else
factor_m = 0;
@@ -136,8 +167,8 @@ static long clk_pll_round_rate(struct aic_clk_comm_cfg *comm_cfg,
factor_m = PLL_FACTORM_MASK;
vco_rate = (factor_m + 1) * rate;
if (vco_rate > PLL_VCO_MAX)
vco_rate = PLL_VCO_MAX;
if (vco_rate > pll_vco_max)
vco_rate = pll_vco_max;
factor_p = (vco_rate % parent_rate) ? 1 : 0;
if (!factor_p)
@@ -161,7 +192,7 @@ static int clk_pll_set_rate(struct aic_clk_comm_cfg *comm_cfg,
u32 factor_n, factor_m, factor_p, reg_val;
u64 val, fra_in = 0;
u8 fra_en, factor_m_en;
unsigned long vco_rate;
unsigned long vco_rate, pll_vco_min, pll_vco_max;
u32 ppm_max, sdm_amp, sdm_en = 0;
u64 sdm_step;
struct aic_clk_pll_cfg *pll = to_clk_pll(comm_cfg);
@@ -169,6 +200,8 @@ static int clk_pll_set_rate(struct aic_clk_comm_cfg *comm_cfg,
if (pll->flag & CLK_NO_CHANGE)
return 0;
clk_vco_select(pll, &pll_vco_min, &pll_vco_max);
if (rate == CLOCK_24M) {
val = readl(cmu_reg(pll->offset_gen));
val &= ~(1 << PLL_OUT_MUX);
@@ -180,11 +213,11 @@ static int clk_pll_set_rate(struct aic_clk_comm_cfg *comm_cfg,
clk_pll_bypass(pll, 1);
/* Calculate PLL parameters.
* The frequency constraint of PLL_VCO
* is between 768M and 1560M
* The frequency constraint of PLL_VCO is between 768M and 1560M
* But the PLL_VCO of pll_fra2 is between 360M and 1584M
*/
if (rate < PLL_VCO_MIN)
factor_m = DIV_ROUND_UP(PLL_VCO_MIN, rate) - 1;
if (rate < pll_vco_min)
factor_m = DIV_ROUND_UP(pll_vco_min, rate) - 1;
else
factor_m = 0;
@@ -201,8 +234,8 @@ static int clk_pll_set_rate(struct aic_clk_comm_cfg *comm_cfg,
factor_m_en = 0;
vco_rate = (factor_m + 1) * rate;
if (vco_rate > PLL_VCO_MAX)
vco_rate = PLL_VCO_MAX;
if (vco_rate > pll_vco_max)
vco_rate = pll_vco_max;
factor_p = (vco_rate % parent_rate) ? 1 : 0;
factor_n = vco_rate * (factor_p + 1) / parent_rate - 1;

5
bsp/artinchip/hal/display/aic_hal_de.c
View File

@@ -617,7 +617,8 @@ void de_config_timing(void *base_addr,
u32 active_w, u32 active_h,
u32 hfp, u32 hbp,
u32 vfp, u32 vbp,
u32 hsync, u32 vsync)
u32 hsync, u32 vsync,
u32 h_pol, u32 v_pol)
{
reg_write(base_addr + TIMING_ACTIVE_SIZE,
TIMING_ACTIVE_SIZE_SET(active_w, active_h));
@@ -625,6 +626,8 @@ void de_config_timing(void *base_addr,
reg_write(base_addr + TIMING_V_PORCH, TIMING_V_PORCH_SET(vfp, vbp));
reg_write(base_addr + TIMING_SYNC_PLUSE,
TIMING_SYNC_PLUSE_SET_H_V(hsync, vsync));
reg_write(base_addr + TIMING_POL_SET,
TIMING_POL_SET_H_V(h_pol, v_pol));
}
void de_set_blending_size(void *base_addr, u32 active_w, u32 active_h)

262
bsp/artinchip/hal/display/aic_hal_dsi.c
View File

@@ -105,133 +105,133 @@ static void dsi_dphy_cfg_hsfreq(void *base, ulong mclk)
u32 freq_rdata = mclk / 1000000;
u32 freq_wdata;
switch (freq_rdata) {
case 80 ... 89:
freq_wdata = 0x00 << 1;
break;
case 90 ... 99:
freq_wdata = 0x10 << 1;
break;
case 100 ... 109:
freq_wdata = 0x20 << 1;
break;
case 110 ... 129:
freq_wdata = 0x01 << 1;
break;
case 130 ... 139:
freq_wdata = 0x11 << 1;
break;
case 140 ... 149:
freq_wdata = 0x21 << 1;
break;
case 150 ... 169:
freq_wdata = 0x02 << 1;
break;
case 170 ... 179:
freq_wdata = 0x12 << 1;
break;
case 180 ... 199:
freq_wdata = 0x22 << 1;
break;
case 200 ... 219:
freq_wdata = 0x03 << 1;
break;
case 220 ... 239:
freq_wdata = 0x13 << 1;
break;
case 240 ... 249:
freq_wdata = 0x23 << 1;
break;
case 250 ... 269:
freq_wdata = 0x04 << 1;
break;
case 270 ... 299:
freq_wdata = 0x14 << 1;
break;
case 300 ... 329:
freq_wdata = 0x05 << 1;
break;
case 330 ... 359:
freq_wdata = 0x15 << 1;
break;
case 360 ... 399:
freq_wdata = 0x25 << 1;
break;
case 400 ... 449:
freq_wdata = 0x06 << 1;
break;
case 450 ... 499:
freq_wdata = 0x16 << 1;
break;
case 500 ... 549:
freq_wdata = 0x07 << 1;
break;
case 550 ... 599:
freq_wdata = 0x17 << 1;
break;
case 600 ... 649:
freq_wdata = 0x08 << 1;
break;
case 650 ... 699:
freq_wdata = 0x18 << 1;
break;
case 700 ... 749:
freq_wdata = 0x09 << 1;
break;
case 750 ... 799:
freq_wdata = 0x19 << 1;
break;
case 800 ... 849:
freq_wdata = 0x29 << 1;
break;
case 850 ... 899:
freq_wdata = 0x39 << 1;
break;
case 900 ... 949:
freq_wdata = 0x0a << 1;
break;
case 950 ... 999:
freq_wdata = 0x1a << 1;
break;
case 1000 ... 1049:
freq_wdata = 0x2a << 1;
break;
case 1050 ... 1099:
freq_wdata = 0x3a << 1;
break;
case 1100 ... 1149:
freq_wdata = 0x0b << 1;
break;
case 1150 ... 1199:
freq_wdata = 0x1b << 1;
break;
case 1200 ... 1249:
freq_wdata = 0x2b << 1;
break;
case 1250 ... 1299:
freq_wdata = 0x3b << 1;
break;
case 1300 ... 1349:
freq_wdata = 0x0c << 1;
break;
case 1350 ... 1399:
freq_wdata = 0x1c << 1;
break;
case 1400 ... 1449:
freq_wdata = 0x2c << 1;
break;
case 1450 ... 1499:
freq_wdata = 0x3c << 1;
break;
default:
freq_wdata = 0x00;
break;
}
switch (freq_rdata) {
case 80 ... 89:
freq_wdata = 0x00 << 1;
break;
case 90 ... 99:
freq_wdata = 0x10 << 1;
break;
case 100 ... 109:
freq_wdata = 0x20 << 1;
break;
case 110 ... 129:
freq_wdata = 0x01 << 1;
break;
case 130 ... 139:
freq_wdata = 0x11 << 1;
break;
case 140 ... 149:
freq_wdata = 0x21 << 1;
break;
case 150 ... 169:
freq_wdata = 0x02 << 1;
break;
case 170 ... 179:
freq_wdata = 0x12 << 1;
break;
case 180 ... 199:
freq_wdata = 0x22 << 1;
break;
case 200 ... 219:
freq_wdata = 0x03 << 1;
break;
case 220 ... 239:
freq_wdata = 0x13 << 1;
break;
case 240 ... 249:
freq_wdata = 0x23 << 1;
break;
case 250 ... 269:
freq_wdata = 0x04 << 1;
break;
case 270 ... 299:
freq_wdata = 0x14 << 1;
break;
case 300 ... 329:
freq_wdata = 0x05 << 1;
break;
case 330 ... 359:
freq_wdata = 0x15 << 1;
break;
case 360 ... 399:
freq_wdata = 0x25 << 1;
break;
case 400 ... 449:
freq_wdata = 0x06 << 1;
break;
case 450 ... 499:
freq_wdata = 0x16 << 1;
break;
case 500 ... 549:
freq_wdata = 0x07 << 1;
break;
case 550 ... 599:
freq_wdata = 0x17 << 1;
break;
case 600 ... 649:
freq_wdata = 0x08 << 1;
break;
case 650 ... 699:
freq_wdata = 0x18 << 1;
break;
case 700 ... 749:
freq_wdata = 0x09 << 1;
break;
case 750 ... 799:
freq_wdata = 0x19 << 1;
break;
case 800 ... 849:
freq_wdata = 0x29 << 1;
break;
case 850 ... 899:
freq_wdata = 0x39 << 1;
break;
case 900 ... 949:
freq_wdata = 0x0a << 1;
break;
case 950 ... 999:
freq_wdata = 0x1a << 1;
break;
case 1000 ... 1049:
freq_wdata = 0x2a << 1;
break;
case 1050 ... 1099:
freq_wdata = 0x3a << 1;
break;
case 1100 ... 1149:
freq_wdata = 0x0b << 1;
break;
case 1150 ... 1199:
freq_wdata = 0x1b << 1;
break;
case 1200 ... 1249:
freq_wdata = 0x2b << 1;
break;
case 1250 ... 1299:
freq_wdata = 0x3b << 1;
break;
case 1300 ... 1349:
freq_wdata = 0x0c << 1;
break;
case 1350 ... 1399:
freq_wdata = 0x1c << 1;
break;
case 1400 ... 1449:
freq_wdata = 0x2c << 1;
break;
case 1450 ... 1499:
freq_wdata = 0x3c << 1;
break;
default:
freq_wdata = 0x00;
break;
}
dsi_dphy_cfg(base, 0x44, &freq_wdata, &freq_rdata);
}
void dsi_phy_init(void *base, ulong mclk, u32 lane)
void dsi_phy_init(void *base, ulong mclk, u32 lane, enum dsi_mode mode)
{
void *ANA2 = base + DSI_ANA_CFG2;
void *CFG = base + DSI_PHY_CFG;
@@ -284,6 +284,14 @@ void dsi_phy_init(void *base, ulong mclk, u32 lane)
reg_set_bits(CFG, DSI_PHY_CFG_DATA_LANE_MASK,
DSI_PHY_CFG_DATA_LANE(lane - 1));
aic_udelay(5);
if (mode & DSI_CLOCK_NON_CONTINUOUS) {
reg_clr_bit(CFG, DSI_PHY_CFG_HSCLK_REQ);
aic_udelay(5);
reg_set_bit(CFG, DSI_PHY_CFG_AUTO_CLK_EN);
aic_udelay(5);
}
reg_set_bit(CFG, DSI_PHY_CFG_RST_CLK_EN);
}
@@ -329,8 +337,6 @@ void dsi_set_vm(void *base, enum dsi_mode mode, enum dsi_format format,
if (unlikely(format >= DSI_FMT_MAX))
BUG();
if (unlikely(mode >= DSI_MOD_MAX))
BUG();
reg_clr_bit(IFCFG, DSI_DPI_IF_CFG_SHUTD);
reg_clr_bit(IFCFG, DSI_DPI_IF_CFG_COLORM);
@@ -351,7 +357,7 @@ void dsi_set_vm(void *base, enum dsi_mode mode, enum dsi_format format,
reg_clr_bit(INPOL, DSI_DPI_IN_POL_SHUTDOWN);
reg_clr_bit(INPOL, DSI_DPI_IN_POL_COLORM);
if (mode == DSI_MOD_CMD_MODE) {
if (mode & DSI_MOD_CMD_MODE) {
reg_set_bit(base + DSI_CTL, DSI_CTL_DSI_MODE);
reg_write(base + DSI_EDPI_CMD_SIZE, timing->hactive);
reg_clr_bit(CMDCFG, DSI_CMD_MODE_CFG_ACK_REQ_EN);
@@ -368,7 +374,7 @@ void dsi_set_vm(void *base, enum dsi_mode mode, enum dsi_format format,
reg_set_bit(VIDCFG, DSI_VID_MODE_CFG_LP_EN_VFP);
reg_set_bit(VIDCFG, DSI_VID_MODE_CFG_LP_EN_VACT);
reg_set_bit(VIDCFG, DSI_VID_MODE_CFG_LP_EN_HBP);
if (mode == DSI_MOD_VID_BURST)
if (mode & DSI_MOD_VID_BURST)
reg_set_bit(VIDCFG, DSI_VID_MODE_CFG_LP_EN_HFP);
else
reg_clr_bit(VIDCFG, DSI_VID_MODE_CFG_LP_EN_HFP);
@@ -478,7 +484,7 @@ void dsi_cmd_wr(void *base, u32 dt, u32 vc, const u8 *data, u32 len)
if (dt == DSI_DT_GEN_RD_P0 || dt == DSI_DT_GEN_RD_P1 ||
dt == DSI_DT_GEN_RD_P2 || dt == DSI_DT_DCS_RD_P0) {
reg_set_bit(CMDCFG, DSI_CMD_MODE_CFG_ACK_REQ_EN);
reg_clr_bit(CMDCFG, DSI_CMD_MODE_CFG_ACK_REQ_EN);
reg_set_bit(base + DSI_CTL, DSI_CTL_PKG_CFG_BTA_EN);
} else {
reg_clr_bit(CMDCFG, DSI_CMD_MODE_CFG_ACK_REQ_EN);

20
bsp/artinchip/hal/dma/hal_dma_reg_v1x.h
View File

@@ -143,10 +143,10 @@ static const u32 dma_burst_1_8[] = {1, 8};
/* ID burst witdh(byte) */
DMA_SLAVE_DEF(DMA_ID_PSADC_Q1, dma_burst_1, dma_width_4_bytes);
DMA_SLAVE_DEF(DMA_ID_PSADC_Q2, dma_burst_1, dma_width_4_bytes);
DMA_SLAVE_DEF(DMA_ID_SPI2, dma_burst_1_8, dma_width_4_bytes);
DMA_SLAVE_DEF(DMA_ID_SPI3, dma_burst_1_8, dma_width_4_bytes);
DMA_SLAVE_DEF(DMA_ID_SPI0, dma_burst_1_8, dma_width_4_bytes);
DMA_SLAVE_DEF(DMA_ID_SPI1, dma_burst_1_8, dma_width_4_bytes);
DMA_SLAVE_DEF(DMA_ID_SPI2, dma_burst_1, dma_width_1_byte);
DMA_SLAVE_DEF(DMA_ID_SPI3, dma_burst_1, dma_width_1_byte);
DMA_SLAVE_DEF(DMA_ID_SPI0, dma_burst_1, dma_width_1_byte);
DMA_SLAVE_DEF(DMA_ID_SPI1, dma_burst_1, dma_width_1_byte);
DMA_SLAVE_DEF(DMA_ID_I2S0, dma_burst_1, dma_width_2_4_bytes);
DMA_SLAVE_DEF(DMA_ID_I2S1, dma_burst_1, dma_width_2_4_bytes);
DMA_SLAVE_DEF(DMA_ID_AUDIO_DMIC, dma_burst_1, dma_width_2_4_bytes);
@@ -183,10 +183,10 @@ static const struct dma_slave_table *aic_dma_slave_table[AIC_DMA_PORTS] = {
/* ID burst witdh(byte)*/
DMA_SLAVE_DEF(DMA_ID_PSADC_Q1, dma_burst_1, dma_width_4_bytes);
DMA_SLAVE_DEF(DMA_ID_PSADC_Q2, dma_burst_1, dma_width_4_bytes);
DMA_SLAVE_DEF(DMA_ID_SPI2, dma_burst_8, dma_width_4_bytes);
DMA_SLAVE_DEF(DMA_ID_SPI3, dma_burst_8, dma_width_4_bytes);
DMA_SLAVE_DEF(DMA_ID_SPI0, dma_burst_8, dma_width_4_bytes);
DMA_SLAVE_DEF(DMA_ID_SPI1, dma_burst_8, dma_width_4_bytes);
DMA_SLAVE_DEF(DMA_ID_SPI2, dma_burst_8, dma_width_1_4_bytes);
DMA_SLAVE_DEF(DMA_ID_SPI3, dma_burst_8, dma_width_1_4_bytes);
DMA_SLAVE_DEF(DMA_ID_SPI0, dma_burst_8, dma_width_1_4_bytes);
DMA_SLAVE_DEF(DMA_ID_SPI1, dma_burst_8, dma_width_1_4_bytes);
DMA_SLAVE_DEF(DMA_ID_I2S0, dma_burst_1, dma_width_2_4_bytes);
DMA_SLAVE_DEF(DMA_ID_I2S1, dma_burst_1, dma_width_2_4_bytes);
DMA_SLAVE_DEF(DMA_ID_AUDIO_DMIC, dma_burst_1, dma_width_2_4_bytes);
@@ -221,8 +221,8 @@ static const struct dma_slave_table *aic_dma_slave_table[AIC_DMA_PORTS] = {
};
#elif defined(AIC_DMA_DRV_V12)
/* ID burst witdh(byte)*/
DMA_SLAVE_DEF(DMA_ID_SPI0, dma_burst_8, dma_width_4_bytes);
DMA_SLAVE_DEF(DMA_ID_SPI1, dma_burst_8, dma_width_4_bytes);
DMA_SLAVE_DEF(DMA_ID_SPI0, dma_burst_8, dma_width_1_4_bytes);
DMA_SLAVE_DEF(DMA_ID_SPI1, dma_burst_8, dma_width_1_4_bytes);
DMA_SLAVE_DEF(DMA_ID_AUDIO_DMIC, dma_burst_1, dma_width_2_4_bytes);
DMA_SLAVE_DEF(DMA_ID_UART0, dma_burst_1, dma_width_1_byte);
DMA_SLAVE_DEF(DMA_ID_UART1, dma_burst_1, dma_width_1_byte);

6
bsp/artinchip/hal/efuse/hal_efuse.c
View File

@@ -21,6 +21,7 @@
#define EFUSE_REG_WFRID (SID_BASE + 0x0018)
#define EFUSE_REG_PKGID (SID_BASE + 0x001C)
#define EFUSE_REG_JTAG (SID_BASE + 0x0080)
#define EFUSE_REG_VER (SID_BASE + 0x00FC)
#define EFUSE_REG_SRAM (SID_BASE + 0x200)
#define EFUSE_CTL_BROM_PRIV_LOCK (0x1 << 28)
@@ -61,6 +62,11 @@ int hal_efuse_deinit(void)
return 0;
}
int hal_efuse_get_version(void)
{
return readl(EFUSE_REG_VER);
}
int hal_efuse_wait_ready(void)
{
u32 val, msk;

38
bsp/artinchip/hal/gpai/hal_gpai.c
View File

@@ -123,7 +123,6 @@
#define GPAI_SRC_RX_MAXBURST 1
#define GPAI_DST_RX_MAXBURST 16
// TODO: irq_handle() should get 'struct aic_gpai_ch *' from 'void *arg'
extern struct aic_gpai_ch aic_gpai_chs[];
static u32 aic_gpai_ch_num = 0; // the number of available channel
@@ -137,12 +136,6 @@ static inline u32 gpai_readl(int reg)
return readl(GPAI_BASE + reg);
}
// TODO: Add the transform algorithm, offered by SD later
static s32 gpai_data2vol(u16 data)
{
return data;
}
static u16 gpai_vol2data(s32 vol)
{
return vol;
@@ -333,7 +326,7 @@ int aich_gpai_ch_init(struct aic_gpai_ch *chan, u32 pclk)
return 0;
}
int aich_gpai_read(struct aic_gpai_ch *chan, u32 *val, u32 timeout)
int aich_gpai_read(struct aic_gpai_ch *chan, u16 *val, u32 timeout)
{
int ret = 0;
u32 ch = chan->id;
@@ -343,26 +336,25 @@ int aich_gpai_read(struct aic_gpai_ch *chan, u32 *val, u32 timeout)
return -ENODATA;
}
#ifndef CONFIG_ARTINCHIP_ADCIM_DM
if (chan->mode == AIC_GPAI_MODE_PERIOD) {
*val = gpai_data2vol(chan->latest_data);
for (int i = 0; i < chan->fifo_valid_cnt; i++) {
val[i] = chan->fifo_data[i];
pr_debug("[%d]ADC val :%d\n", i, chan->fifo_data[i]);
}
return 0;
}
#endif
aich_gpai_ch_enable(ch, 1);
gpai_single_mode(ch);
ret = aicos_sem_take(chan->complete, timeout);
if (ret < 0) {
hal_log_err("Ch%d read timeout!\n", ch);
aich_gpai_ch_enable(ch, 0);
return -ETIMEDOUT;
}
// aich_gpai_ch_enable(ch, 0);
if (val)
*val = gpai_data2vol(chan->latest_data);
for (int i = 0; i < chan->fifo_valid_cnt; i++)
val[i] = chan->fifo_data[i];
return 0;
}
@@ -407,13 +399,13 @@ static int aic_gpai_read_ch(struct aic_gpai_ch *chan)
return -1;
}
/* Just record the last data as to now */
for (i = 0; i < cnt; i++) {
chan->latest_data = gpai_readl(GPAI_CHnDATA(ch));
// pr_debug("ch%d data%d %d\n", ch, i, chan->latest_data);
}
pr_debug("There are %d data ready in ch%d, last %d\n", cnt,
ch, chan->latest_data);
for (i = 0; i < cnt; i++)
chan->fifo_data[i] = gpai_readl(GPAI_CHnDATA(ch));
chan->fifo_valid_cnt = cnt;
chan->latest_data = chan->fifo_data[cnt];
pr_debug("There are %d data ready in ch%d, last %d\n", cnt, ch,
chan->latest_data);
return 0;
}
@@ -474,6 +466,8 @@ irqreturn_t aich_gpai_isr(int irq, void *arg)
chan->irq_count++;
if (chan->mode == AIC_GPAI_MODE_SINGLE)
aicos_sem_give(chan->complete);
if (chan->irq_info.callback)
chan->irq_info.callback(chan->irq_info.callback_param);
}
if (ch_int & GPAI_CHnINT_LLA_VALID_FLAG)

15
bsp/artinchip/hal/gpio/aic_hal_gpio.c
View File

@@ -102,6 +102,21 @@ int hal_gpio_get_value(unsigned int group, unsigned int pin,
return 0;
}
int hal_gpio_get_outcfg(unsigned int group, unsigned int pin,
unsigned int *pvalue)
{
unsigned int val = 0;
CHECK_PARAM(group < GPIO_GROUP_MAX && group >= 0 && pin < 32 && pin >= 0,
-EINVAL);
val = readl(gen_reg(group, GEN_OUT_CFG_REG));
*pvalue = !!(val & (1 << pin));
return 0;
}
int hal_gpio_set_value(unsigned int group, unsigned int pin, unsigned int value)
{
unsigned int val = 0;

213
bsp/artinchip/hal/i2c/hal_i2c.c
View File

@@ -5,7 +5,6 @@
*
* Authors: geo <guojun.dong@artinchip.com>
*/
#include <rtconfig.h>
#include <stdbool.h>
#include <string.h>
@@ -15,72 +14,77 @@
#define gen_reg(val) (volatile void *)(val)
#define USEC_PER_SEC (1000000)
int aic_i2c_init(int32_t i2c_idx)
int hal_i2c_clk_init(aic_i2c_ctrl *i2c_dev)
{
int ret = 0;
ret = hal_clk_enable_deassertrst(CLK_I2C0 + i2c_idx);
ret = hal_clk_enable_deassertrst(CLK_I2C0 + i2c_dev->index);
if (ret < 0)
pr_err("I2C clock and reset init error\n");
return ret;
}
void hal_i2c_set_hold(ptr_t reg_base, u32 val)
void hal_i2c_set_hold(aic_i2c_ctrl *i2c_dev, u32 val)
{
writel(val, reg_base + I2C_SDA_HOLD);
writel(val, i2c_dev->reg_base + I2C_SDA_HOLD);
}
int aic_i2c_set_master_slave_mode(unsigned long reg_base, uint8_t mode)
int hal_i2c_set_master_slave_mode(aic_i2c_ctrl *i2c_dev)
{
uint32_t reg_val;
uint8_t mode;
CHECK_PARAM(reg_base, -EINVAL);
CHECK_PARAM(i2c_dev, -EINVAL);
reg_val = readl(gen_reg(reg_base + I2C_CTL));
mode = i2c_dev->bus_mode;
reg_val = readl(gen_reg(i2c_dev->reg_base + I2C_CTL));
reg_val &= ~I2C_CTL_MASTER_SLAVE_SELECT_MASK;
if (mode)
if (!mode)
reg_val |= I2C_ENABLE_MASTER_DISABLE_SLAVE;
else
/* slave mode, and will detect stop signal only if addressed */
reg_val |= I2C_CTL_STOP_DET_IFADDR;
writel(reg_val, gen_reg(reg_base + I2C_CTL));
writel(reg_val, gen_reg(i2c_dev->reg_base + I2C_CTL));
return 0;
}
int aic_i2c_master_10bit_addr(unsigned long reg_base, uint8_t enable)
int hal_i2c_master_10bit_addr(aic_i2c_ctrl *i2c_dev)
{
uint32_t reg_val;
uint8_t enable;
CHECK_PARAM(reg_base, -EINVAL);
CHECK_PARAM(i2c_dev, -EINVAL);
reg_val = readl(gen_reg(reg_base + I2C_CTL));
enable = i2c_dev->addr_bit;
reg_val = readl(gen_reg(i2c_dev->reg_base + I2C_CTL));
reg_val &= ~I2C_CTL_10BIT_SELECT_MASTER;
if (enable)
reg_val |= I2C_CTL_10BIT_SELECT_MASTER;
writel(reg_val, gen_reg(reg_base + I2C_CTL));
writel(reg_val, gen_reg(i2c_dev->reg_base + I2C_CTL));
return 0;
}
int aic_i2c_slave_10bit_addr(unsigned long reg_base, uint8_t enable)
int hal_i2c_slave_10bit_addr(aic_i2c_ctrl *i2c_dev)
{
uint32_t reg_val;
uint8_t enable;
CHECK_PARAM(i2c_dev, -EINVAL);
CHECK_PARAM(reg_base, -EINVAL);
reg_val = readl(gen_reg(reg_base + I2C_CTL));
enable = i2c_dev->addr_bit;
reg_val = readl(gen_reg(i2c_dev->reg_base + I2C_CTL));
reg_val &= ~I2C_CTL_10BIT_SELECT_SLAVE;
if (enable)
reg_val |= I2C_CTL_10BIT_SELECT_SLAVE;
writel(reg_val, gen_reg(reg_base + I2C_CTL));
writel(reg_val, gen_reg(i2c_dev->reg_base + I2C_CTL));
return 0;
}
static int i2c_scl_cnt(uint32_t clk_freq, uint8_t isStandardSpeed,
static int hal_i2c_scl_cnt(uint32_t clk_freq, uint8_t is_standard_speed,
uint16_t *hcnt, uint16_t *lcnt)
{
uint16_t hcnt_tmp, lcnt_tmp;
@@ -88,7 +92,7 @@ static int i2c_scl_cnt(uint32_t clk_freq, uint8_t isStandardSpeed,
CHECK_PARAM(hcnt, -EINVAL);
CHECK_PARAM(lcnt, -EINVAL);
if (isStandardSpeed) {
if (is_standard_speed) {
/* Minimum value of tHIGH in standard mode is 4000ns
* Plus 2 is just to increase the time of tHIGH, appropriately.
* SS_MIN_SCL_HIGH * (clk_freq / 1000) is just to prevent 32bits
@@ -112,105 +116,104 @@ static int i2c_scl_cnt(uint32_t clk_freq, uint8_t isStandardSpeed,
return 0;
}
int aic_i2c_speed_mode_select(unsigned long reg_base, uint32_t clk_freq,
uint8_t mode)
int hal_i2c_speed_mode_select(aic_i2c_ctrl *i2c_dev, uint32_t clk_freq, uint8_t mode)
{
uint32_t reg_val;
uint16_t hcnt, lcnt;
int ret;
CHECK_PARAM(reg_base, -EINVAL);
CHECK_PARAM(i2c_dev, -EINVAL);
reg_val = readl(gen_reg(reg_base + I2C_CTL));
reg_val = readl(gen_reg(i2c_dev->reg_base + I2C_CTL));
reg_val &= ~I2C_CTL_SPEED_MODE_SELECT_MASK;
if (mode) {
if (!mode) {
reg_val |= I2C_CTL_SPEED_MODE_FS;
/* Calculate fast speed HCNT and LCNT */
ret = i2c_scl_cnt(clk_freq, false, &hcnt, &lcnt);
ret = hal_i2c_scl_cnt(clk_freq, false, &hcnt, &lcnt);
if (ret)
return ret;
writel(hcnt, gen_reg(reg_base + I2C_FS_SCL_HCNT));
writel(lcnt, gen_reg(reg_base + I2C_FS_SCL_LCNT));
writel(hcnt, gen_reg(i2c_dev->reg_base + I2C_FS_SCL_HCNT));
writel(lcnt, gen_reg(i2c_dev->reg_base + I2C_FS_SCL_LCNT));
} else {
reg_val |= I2C_CTL_SPEED_MODE_SS;
/* Calculate standard speed HCNT and LCNT */
ret = i2c_scl_cnt(clk_freq, true, &hcnt, &lcnt);
ret = hal_i2c_scl_cnt(clk_freq, true, &hcnt, &lcnt);
if (ret)
return ret;
writel(hcnt, gen_reg(reg_base + I2C_SS_SCL_HCNT));
writel(lcnt, gen_reg(reg_base + I2C_SS_SCL_LCNT));
writel(hcnt, gen_reg(i2c_dev->reg_base + I2C_SS_SCL_HCNT));
writel(lcnt, gen_reg(i2c_dev->reg_base + I2C_SS_SCL_LCNT));
}
writel(reg_val, gen_reg(reg_base + I2C_CTL));
writel(reg_val, gen_reg(i2c_dev->reg_base + I2C_CTL));
return 0;
}
/*
* Set the target address when i2c worked as master mode
*/
void aic_i2c_target_addr(unsigned long reg_base, uint32_t addr)
void hal_i2c_target_addr(aic_i2c_ctrl *i2c_dev, uint32_t addr)
{
uint32_t reg_val;
reg_val = readl(gen_reg(reg_base + I2C_TAR));
reg_val = readl(gen_reg(i2c_dev->reg_base + I2C_TAR));
reg_val &= ~I2C_TAR_ADDR_MASK;
reg_val |= addr;
writel(reg_val, gen_reg(reg_base + I2C_TAR));
writel(reg_val, gen_reg(i2c_dev->reg_base + I2C_TAR));
}
int aic_i2c_slave_own_addr(unsigned long reg_base, uint32_t addr)
int hal_i2c_slave_own_addr(aic_i2c_ctrl *i2c_dev, uint32_t addr)
{
CHECK_PARAM(reg_base, -EINVAL);
CHECK_PARAM(i2c_dev, -EINVAL);
CHECK_PARAM(!(addr > I2C_TAR_ADDR_MASK), -EINVAL);
writel(addr, gen_reg(reg_base + I2C_SAR));
writel(addr, gen_reg(i2c_dev->reg_base + I2C_SAR));
return 0;
}
/**
\brief Start sending data as IIC Master.
This function is non-blocking,\ref csi_iic_event_e is signaled when transfer completes or error happens.
\param[in] iic handle to operate.
\param[in] devaddr iic addrress of slave device. |_BIT[7:1]devaddr_|_BIT[0]R/W_|
eg: BIT[7:0] = 0xA0, devaddr = 0x50.
\param[in] data data to send to IIC Slave
\param[in] num size of data items to send
\return \ref csi_error_t
*/
int aic_i2c_master_send_msg_async(unsigned long reg_base, uint32_t devaddr,
const void *data, uint32_t size)
int hal_i2c_init(aic_i2c_ctrl *i2c_dev)
{
// CSI_PARAM_CHK(iic, CSI_ERROR);
// CSI_PARAM_CHK(data, CSI_ERROR);
// CSI_PARAM_CHK(size, CSI_ERROR);
int ret = EOK;
int32_t ret = I2C_OK;
// csi_irq_attach((uint32_t)iic->dev.irq_num, &aich_twi_master_tx_handler, &iic->dev);
// csi_irq_enable((uint32_t)iic->dev.irq_num);
// iic_master_send_intr(iic, devaddr, data, size);
ret = hal_i2c_clk_init(i2c_dev);
if (ret)
return ret;
hal_i2c_set_master_slave_mode(i2c_dev);
hal_i2c_set_hold(i2c_dev, 10);
hal_i2c_master_10bit_addr(i2c_dev);
hal_i2c_slave_10bit_addr(i2c_dev);
#ifdef AIC_I2C_INTERRUPT_MODE
hal_i2c_disable_all_irq(i2c_dev);
hal_i2c_set_transmit_fifo_threshold(i2c_dev);
#else
hal_i2c_master_enable_irq(i2c_dev);
#endif
ret = hal_i2c_speed_mode_select(i2c_dev, I2C_DEFALT_CLOCK, i2c_dev->speed_mode);
if (ret)
return ret;
if (i2c_dev->bus_mode) {
hal_i2c_config_fifo_slave(i2c_dev);
hal_i2c_clear_all_irq_flags(i2c_dev);
hal_i2c_slave_enable_irq(i2c_dev);
hal_i2c_module_disable(i2c_dev);
hal_i2c_slave_own_addr(i2c_dev, i2c_dev->slave_addr);
hal_i2c_module_enable(i2c_dev);
}
return ret;
}
/**
\brief wait_iic_transmit
\param[in] reg_base: i2c
\return \ref csi_error_t
*/
static int32_t aic_i2c_wait_iic_transmit(unsigned long reg_base,
uint32_t timeout)
static int32_t hal_i2c_wait_transmit(aic_i2c_ctrl *i2c_dev, uint32_t timeout)
{
int32_t ret = I2C_OK;
do {
uint64_t timecount = timeout + aic_get_time_ms();
while ((aic_i2c_get_transmit_fifo_num(reg_base) != 0U) &&
while ((hal_i2c_get_transmit_fifo_num(i2c_dev) != 0U) &&
(ret == EOK)) {
if (aic_get_time_ms() >= timecount) {
ret = I2C_TIMEOUT;
@@ -222,13 +225,7 @@ static int32_t aic_i2c_wait_iic_transmit(unsigned long reg_base,
return ret;
}
/**
\brief wait_iic_receive
\param[in] iic handle of iic instance
\param[in] wait receive data num
\return \ref csi_error_t
*/
static int32_t aic_i2c_wait_receive(unsigned long reg_base,
static int32_t hal_i2c_wait_receive(aic_i2c_ctrl *i2c_dev,
uint32_t wait_data_num, uint32_t timeout)
{
int32_t ret = I2C_OK;
@@ -236,7 +233,7 @@ static int32_t aic_i2c_wait_receive(unsigned long reg_base,
do {
uint64_t timecount = timeout + aic_get_time_ms();
while ((aic_i2c_get_receive_fifo_num(reg_base) < wait_data_num) &&
while ((hal_i2c_get_receive_fifo_num(i2c_dev) < wait_data_num) &&
(ret == I2C_OK)) {
if (aic_get_time_ms() >= timecount) {
ret = I2C_TIMEOUT;
@@ -247,13 +244,29 @@ static int32_t aic_i2c_wait_receive(unsigned long reg_base,
return ret;
}
int32_t hal_i2c_wait_bus_free(aic_i2c_ctrl *i2c_dev, uint32_t timeout)
{
int32_t ret = I2C_OK;
uint64_t timecount = timeout + aic_get_time_ms();
while (hal_i2c_bus_status(i2c_dev)) {
if (aic_get_time_ms() >= timecount) {
ret = I2C_TIMEOUT;
return ret;
}
}
return ret;
}
/**
\brief aic_i2c_master_send_msg
\brief hal_i2c_master_send_msg
\param[in] reg_base
\param[in]
\return bytes of sent msg
*/
int32_t aic_i2c_master_send_msg(unsigned long reg_base,
int32_t hal_i2c_master_send_msg(aic_i2c_ctrl *i2c_dev,
struct aic_i2c_msg *msg, uint8_t is_last_message)
{
CHECK_PARAM(msg, -EINVAL);
@@ -266,16 +279,16 @@ int32_t aic_i2c_master_send_msg(unsigned long reg_base,
uint32_t reg_val;
uint16_t idx = 0;
aic_i2c_module_disable(reg_base);
aic_i2c_target_addr(reg_base, msg->addr);
aic_i2c_module_enable(reg_base);
hal_i2c_module_disable(i2c_dev);
hal_i2c_target_addr(i2c_dev, msg->addr);
hal_i2c_module_enable(i2c_dev);
if (!size)
{
aic_i2c_transmit_data_with_stop_bit(reg_base, 0);
hal_i2c_transmit_data_with_stop_bit(i2c_dev, 0);
while (1)
{
reg_val = readl(reg_base + I2C_INTR_RAW_STAT);
reg_val = readl(i2c_dev->reg_base + I2C_INTR_RAW_STAT);
if (reg_val & I2C_INTR_STOP_DET)
{
if (reg_val & I2C_INTR_TX_ABRT)
@@ -294,26 +307,25 @@ int32_t aic_i2c_master_send_msg(unsigned long reg_base,
uint16_t send_num = size > I2C_FIFO_DEPTH ? I2C_FIFO_DEPTH : size;
for (uint16_t i = 0; i < send_num; i++) {
if (is_last_message && (idx == msg->len -1))
aic_i2c_transmit_data_with_stop_bit(reg_base, msg->buf[idx]);
hal_i2c_transmit_data_with_stop_bit(i2c_dev, msg->buf[idx]);
else if (!is_last_message && (idx == 0))
aic_i2c_set_restart_bit_with_data(reg_base, msg->buf[idx]);
hal_i2c_set_restart_bit_with_data(i2c_dev, msg->buf[idx]);
else
aic_i2c_transmit_data(reg_base, msg->buf[idx]);
hal_i2c_transmit_data(i2c_dev, msg->buf[idx]);
idx++;
}
size -= send_num;
send_count += send_num;
ret = aic_i2c_wait_iic_transmit(reg_base, timeout);
ret = hal_i2c_wait_transmit(i2c_dev, timeout);
if (ret != I2C_OK) {
send_count = ret;
return I2C_TIMEOUT;
}
}
while (!(aic_i2c_get_raw_interrupt_state(reg_base)
while (!(hal_i2c_get_raw_interrupt_state(i2c_dev)
& (I2C_INTR_STOP_DET | I2C_INTR_START_DET))) {
stop_time++;
if (stop_time > I2C_TIMEOUT_DEF_VAL) {
return I2C_TIMEOUT;
@@ -324,12 +336,12 @@ int32_t aic_i2c_master_send_msg(unsigned long reg_base,
}
/**
\brief aic_i2c_master_receive_msg
\brief hal_i2c_master_receive_msg
\param[in] reg_base
\param[in]
\return bytes of read msg
*/
int32_t aic_i2c_master_receive_msg(unsigned long reg_base,
int32_t hal_i2c_master_receive_msg(aic_i2c_ctrl *i2c_dev,
struct aic_i2c_msg *msg, uint8_t is_last_message)
{
CHECK_PARAM(msg, -EINVAL);
@@ -342,26 +354,26 @@ int32_t aic_i2c_master_receive_msg(unsigned long reg_base,
int idx = 0, count = 0;
CHECK_PARAM(receive_data, -EINVAL);
aic_i2c_module_disable(reg_base);
aic_i2c_target_addr(reg_base, msg->addr);
aic_i2c_module_enable(reg_base);
hal_i2c_module_disable(i2c_dev);
hal_i2c_target_addr(i2c_dev, msg->addr);
hal_i2c_module_enable(i2c_dev);
while (size > 0) {
int32_t recv_num = size > I2C_FIFO_DEPTH ? I2C_FIFO_DEPTH : size;
for (uint16_t len = 0; len < recv_num; len++) {
if (is_last_message && (count == msg->len - 1))
aic_i2c_read_data_cmd_with_stop_bit(reg_base);
hal_i2c_read_data_cmd_with_stop_bit(i2c_dev);
else
aic_i2c_read_data_cmd(reg_base);
hal_i2c_read_data_cmd(i2c_dev);
count++;
}
size -= recv_num;
read_count += recv_num;
ret = aic_i2c_wait_receive(reg_base, recv_num, timeout);
ret = hal_i2c_wait_receive(i2c_dev, recv_num, timeout);
if (ret == I2C_OK) {
for (uint16_t i = 0; i < recv_num; i++) {
receive_data[idx] = aic_i2c_get_receive_data(reg_base);
receive_data[idx] = hal_i2c_get_receive_data(i2c_dev);
idx++;
}
} else {
@@ -372,9 +384,8 @@ int32_t aic_i2c_master_receive_msg(unsigned long reg_base,
uint32_t timecount = timeout + aic_get_time_ms();
while (!(aic_i2c_get_raw_interrupt_state(reg_base)
while (!(hal_i2c_get_raw_interrupt_state(i2c_dev)
& (I2C_INTR_STOP_DET | I2C_INTR_START_DET))) {
if (aic_get_time_ms() >= timecount) {
return I2C_TIMEOUT;
break;

8
bsp/artinchip/hal/psadc/hal_psadc.c
View File

@@ -163,7 +163,7 @@ void aich_psadc_status_show(void)
int version = psadc_readl(PSADC_VERSION);
printf("In PSADC V%d.%02d\n"
"enabled %d chans: ",
"enabled %d channels: ",
version >> 8, version & 0xff,
aic_psadc_ch_num);
@@ -216,7 +216,7 @@ int hal_psadc_read(u32 *val, u32 timeout)
psadc_reg_enable(PSADC_MCR, PSADC_MCR_Q1_TRIGS, 1);
ret = aicos_sem_take(queue->complete, timeout);
if (ret < 0) {
hal_log_err("Queue%d read timeout!\n");
hal_log_err("Queue%d read timeout!\n", queue->id);
hal_psadc_qc_irq_enable(0);
return -ETIMEDOUT;
@@ -224,7 +224,7 @@ int hal_psadc_read(u32 *val, u32 timeout)
if (val)
memcpy(val, aic_psadc_ch_data, sizeof(aic_psadc_ch_data));
return RT_EOK;
return 0;
}
int hal_psadc_read_poll(u32 *val, u32 timeout)
@@ -262,7 +262,7 @@ int hal_psadc_read_poll(u32 *val, u32 timeout)
memcpy(val, aic_psadc_ch_data,
sizeof(aic_psadc_ch_data[0]) * queue->nodes_num);
return RT_EOK;
return 0;
}
irqreturn_t hal_psadc_isr(int irq, void *arg)

452
bsp/artinchip/hal/qspi/hal_qspi_slave.c
View File

@@ -1,452 +0,0 @@
/*
* Copyright (c) 2022, Artinchip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <rtconfig.h>
#include <stdbool.h>
#include <string.h>
#include <stdint.h>
#include <aic_common.h>
#include <aic_core.h>
#include <aic_hal.h>
#include <hal_dma.h>
#include <hal_qspi.h>
#include "qspi_internal.h"
#ifdef AIC_QSPI_DRV_V11
#include "qspi_hw_v1.1.h"
int hal_qspi_slave_init(qspi_slave_handle *h, struct qspi_slave_config *cfg)
{
struct qspi_slave_state *qspi;
u32 base, sclk;
int ret;
CHECK_PARAM(h, -EINVAL);
CHECK_PARAM(cfg, -EINVAL);
qspi = (struct qspi_slave_state *)h;
base = qspi_hw_index_to_base(cfg->idx);
if (base == QSPI_INVALID_BASE) {
hal_log_err("invalid spi controller index %d\n", cfg->idx);
return -ENODEV;
}
sclk = cfg->clk_in_hz;
if (sclk > HAL_QSPI_MAX_FREQ_HZ)
sclk = HAL_QSPI_MAX_FREQ_HZ;
else if (sclk < HAL_QSPI_MIN_FREQ_HZ)
sclk = HAL_QSPI_MIN_FREQ_HZ;
qspi->idx = cfg->idx;
show_freq("freq (input)", qspi->idx, sclk);
hal_clk_set_freq(cfg->clk_id, sclk);
ret = hal_clk_enable(cfg->clk_id);
if (ret < 0) {
hal_log_err("QSPI %d clk enable failed!\n", cfg->idx);
return -EFAULT;
}
ret = hal_clk_enable_deassertrst(cfg->clk_id);
if (ret < 0) {
hal_log_err("QSPI %d reset deassert failed!\n", cfg->idx);
return -EFAULT;
}
qspi_hw_init_default(base);
qspi_hw_set_ctrl_mode(base, QSPI_CTRL_MODE_SLAVE);
qspi_hw_interrupt_disable(base, ICR_BIT_ALL_MSK);
qspi_hw_set_cpol(base, cfg->cpol);
qspi_hw_set_cpha(base, cfg->cpha);
qspi_hw_set_lsb_en(base, cfg->lsb_en);
qspi_hw_set_cs_polarity(base, cfg->cs_polarity);
if (cfg->cs_polarity == QSPI_CS_POL_VALID_LOW)
qspi_hw_set_cs_level(base, QSPI_CS_LEVEL_HIGH);
else
qspi_hw_set_cs_level(base, QSPI_CS_LEVEL_LOW);
if (cfg->cs_auto)
qspi_hw_set_cs_owner(base, QSPI_CS_CTL_BY_HW);
else
qspi_hw_set_cs_owner(base, QSPI_CS_CTL_BY_SW);
qspi_hw_drop_invalid_data(base, QSPI_DROP_INVALID_DATA);
qspi_hw_reset_fifo(base);
qspi_hw_set_fifo_watermark(base, QSPI_TX_WATERMARK, QSPI_RX_WATERMARK);
qspi->clk_id = cfg->clk_id;
qspi->cb = NULL;
qspi->cb_priv = NULL;
return 0;
}
void hal_qspi_slave_fifo_reset(qspi_slave_handle *h, u32 fifo)
{
struct qspi_slave_state *qspi;
u32 base;
CHECK_PARAM_RET(h);
qspi = (struct qspi_slave_state *)h;
base = qspi_hw_index_to_base(qspi->idx);
hal_qspi_fifo_reset(base, fifo);
}
int hal_qspi_slave_deinit(qspi_slave_handle *h)
{
struct qspi_slave_state *qspi;
CHECK_PARAM(h, -EINVAL);
qspi = (struct qspi_slave_state *)h;
qspi->cb = NULL;
qspi->cb_priv = NULL;
qspi->async_tx = NULL;
qspi->async_rx = NULL;
qspi->async_tx_remain = 0;
qspi->async_rx_remain = 0;
return 0;
}
int hal_qspi_slave_set_bus_width(qspi_slave_handle *h, u32 bus_width)
{
struct qspi_slave_state *qspi;
u32 base;
CHECK_PARAM(h, -EINVAL);
qspi = (struct qspi_slave_state *)h;
base = qspi_hw_index_to_base(qspi->idx);
qspi_hw_set_bus_width(base, bus_width);
qspi->bus_width = bus_width;
if (qspi->bus_width == 0)
qspi->bus_width = QSPI_BUS_WIDTH_SINGLE;
return 0;
}
int hal_qspi_slave_register_cb(qspi_slave_handle *h, qspi_slave_async_cb cb, void *priv)
{
struct qspi_slave_state *qspi;
CHECK_PARAM(h, -EINVAL);
CHECK_PARAM(cb, -EINVAL);
qspi = (struct qspi_slave_state *)h;
qspi->cb = cb;
qspi->cb_priv = priv;
return 0;
}
int hal_qspi_slave_get_status(qspi_slave_handle *h)
{
struct qspi_slave_state *qspi;
CHECK_PARAM(h, -EINVAL);
qspi = (struct qspi_slave_state *)h;
return (qspi->status) & (~HAL_QSPI_STATUS_INTERNAL_MSK);
}
void hal_qspi_show_ists(u32 id, u32 sts)
{
if (sts) {
printf("QSPI%d:\n", id);
}
if (sts & ISTS_BIT_RF_RDY)
printf(" ISTS_BIT_RF_RDY\n");
if (sts & ISTS_BIT_RF_EMP)
printf(" ISTS_BIT_RF_EMP\n");
if (sts & ISTS_BIT_RF_FUL)
printf(" ISTS_BIT_RF_FUL\n");
if (sts & ISTS_BIT_TF_RDY)
printf(" ISTS_BIT_TF_RDY\n");
if (sts & ISTS_BIT_TF_EMP)
printf(" ISTS_BIT_TF_EMP\n");
if (sts & ISTS_BIT_TF_FUL)
printf(" ISTS_BIT_TF_FUL\n");
if (sts & ISTS_BIT_RF_OVF)
printf(" ISTS_BIT_RF_OVF\n");
if (sts & ISTS_BIT_RF_UDR)
printf(" ISTS_BIT_RF_UDR\n");
if (sts & ISTS_BIT_TF_OVF)
printf(" ISTS_BIT_TF_OVF\n");
if (sts & ISTS_BIT_TF_UDR)
printf(" ISTS_BIT_TF_UDR\n");
if (sts & ISTS_BIT_CS_INV)
printf(" ISTS_BIT_CS_INV\n");
if (sts & ISTS_BIT_TDONE)
printf(" ISTS_BIT_TDONE\n");
}
void hal_qspi_slave_irq_handler(qspi_slave_handle *h)
{
struct qspi_slave_state *qspi;
u32 base, sts, imsk;
CHECK_PARAM_RET(h);
qspi = (struct qspi_slave_state *)h;
base = qspi_hw_index_to_base(qspi->idx);
qspi_hw_get_interrupt_status(base, &sts);
if (sts & ISTS_BIT_TF_OVF)
qspi->status |= HAL_QSPI_STATUS_TX_OVER_FLOW;
if ((sts & ISTS_BIT_TF_EMP) || (sts & ISTS_BIT_TF_RDY)) {
u32 dolen, free_len;
if ((qspi->work_mode == QSPI_WORK_MODE_ASYNC_TX_CPU) &&
qspi->async_tx) {
u32 total;
free_len = QSPI_FIFO_DEPTH - qspi_hw_get_tx_fifo_cnt(base);
if (qspi->async_tx_remain) {
dolen = min(free_len, qspi->async_tx_remain);
qspi_hw_write_fifo(base, qspi->async_tx, dolen);
qspi->async_tx += dolen;
qspi->async_tx_wcnt += dolen;
qspi->async_tx_remain -= dolen;
} else {
imsk = ISTS_BIT_TF_EMP | ISTS_BIT_TF_RDY;
qspi_hw_interrupt_disable(base, imsk);
}
total = qspi->async_tx_remain + qspi->async_tx_wcnt;
qspi->async_tx_count = total - qspi_hw_get_tx_fifo_cnt(base);
}
}
if (sts & ISTS_BIT_RF_UDR)
qspi->status |= HAL_QSPI_STATUS_RX_UNDER_RUN;
if (sts & ISTS_BIT_RF_OVF)
qspi->status |= HAL_QSPI_STATUS_RX_OVER_FLOW;
if ((sts & ISTS_BIT_RF_FUL) || (sts & ISTS_BIT_RF_RDY) || (sts & ISTS_BIT_TDONE)) {
u32 dolen;
if ((qspi->work_mode == QSPI_WORK_MODE_ASYNC_RX_CPU) && qspi->async_rx &&
qspi->async_rx_remain) {
dolen = qspi_hw_get_rx_fifo_cnt(base);
if (dolen > qspi->async_rx_remain)
dolen = qspi->async_rx_remain;
qspi_hw_read_fifo(base, qspi->async_rx, dolen);
qspi->async_rx += dolen;
qspi->async_rx_count += dolen;
qspi->async_rx_remain -= dolen;
}
}
if ((sts & ISTS_BIT_TF_EMP) && (sts & ISTS_BIT_TDONE)) {
/* Write 4 bytes 0 to clear TX Buffer,
* Note:
* Every time user send new data, please reset TX FIFO
*/
u32 zeros = 0;
qspi_hw_write_fifo(base, (void *)&zeros, 4);
}
if (sts & ISTS_BIT_TDONE) {
if (qspi->status == HAL_QSPI_STATUS_IN_PROGRESS)
qspi->status = HAL_QSPI_STATUS_OK;
else
qspi->status &= ~HAL_QSPI_STATUS_IN_PROGRESS;
imsk = ICR_BIT_ALL_MSK;
imsk &= ~ICR_BIT_TDONE_INTE;
imsk &= ~ICR_BIT_CS_INV_INTE;
qspi_hw_interrupt_disable(base, imsk);
qspi->status |= HAL_QSPI_STATUS_ASYNC_TDONE;
if (QSPI_IS_ASYNC_ALL_DONE(qspi->status, qspi->done_mask)) {
if (qspi->work_mode == QSPI_WORK_MODE_ASYNC_RX_DMA) {
qspi->async_rx_count =
qspi->async_rx_remain - qspi_hw_get_idma_rx_len(base);
aicos_dcache_invalid_range(qspi->async_rx, qspi->async_rx_count);
}
if (qspi->work_mode == QSPI_WORK_MODE_ASYNC_TX_DMA) {
qspi->async_tx_count =
qspi->async_tx_remain - qspi_hw_get_tx_fifo_cnt(base);
}
if (qspi->cb)
qspi->cb(h, qspi->cb_priv);
}
}
qspi_hw_clear_interrupt_status(base, sts);
}
int qspi_slave_transfer_cpu_async(struct qspi_slave_state *qspi,
struct qspi_transfer *t)
{
u32 base, txlen, rxlen;
int ret = 0;
base = qspi_hw_index_to_base(qspi->idx);
if ((t->tx_data == NULL) && (t->rx_data == NULL))
return -EINVAL;
if (t->data_len == 0)
return -EINVAL;
qspi_hw_interrupt_disable(base, ICR_BIT_ALL_MSK);
qspi->status = HAL_QSPI_STATUS_IN_PROGRESS;
if (t->tx_data) {
txlen = t->data_len;
qspi->work_mode = QSPI_WORK_MODE_ASYNC_TX_CPU;
qspi->done_mask = HAL_QSPI_STATUS_ASYNC_TDONE;
qspi->async_rx = NULL;
qspi->async_rx_count = 0;
qspi->async_rx_remain = 0;
qspi->async_tx = t->tx_data;
qspi->async_tx_count = 0;
qspi->async_tx_wcnt = 0;
qspi->async_tx_remain = txlen;
if (qspi->bus_width > 1)
qspi_hw_set_slave_output_en(base, 1);
else
qspi_hw_set_slave_output_en(base, 0);
qspi_hw_interrupt_enable(base, ICR_BIT_ERRS | ICR_BIT_TDONE_INTE |
ISTS_BIT_TF_RDY | ISTS_BIT_TF_EMP |
ICR_BIT_CS_INV_INTE);
qspi_hw_clear_interrupt_status(base, ISTS_BIT_ALL_MSK);
} else if (t->rx_data) {
rxlen = t->data_len;
qspi->work_mode = QSPI_WORK_MODE_ASYNC_RX_CPU;
qspi->done_mask = HAL_QSPI_STATUS_ASYNC_TDONE;
qspi->async_tx = NULL;
qspi->async_tx_count = 0;
qspi->async_tx_remain = 0;
qspi->async_rx = t->rx_data;
qspi->async_rx_count = 0;
qspi->async_rx_remain = rxlen;
qspi_hw_set_slave_output_en(base, 0);
qspi_hw_interrupt_enable(base, ICR_BIT_ERRS | ICR_BIT_TDONE_INTE |
ICR_BIT_CS_INV_INTE);
qspi_hw_clear_interrupt_status(base, ISTS_BIT_ALL_MSK);
}
return ret;
}
static int qspi_slave_transfer_dma_async(struct qspi_slave_state *qspi, struct qspi_transfer *t)
{
u32 base, txlen, rxlen, imsk;
int ret = 0;
base = qspi_hw_index_to_base(qspi->idx);
if ((t->tx_data == NULL) && (t->rx_data == NULL))
return -EINVAL;
if (t->data_len == 0)
return -EINVAL;
qspi_hw_set_idma_busrt_auto_len_en(base, 1);
qspi_hw_interrupt_disable(base, ICR_BIT_ALL_MSK);
qspi->status = HAL_QSPI_STATUS_IN_PROGRESS;
if (t->tx_data) {
qspi->work_mode = QSPI_WORK_MODE_ASYNC_TX_DMA;
qspi->done_mask = HAL_QSPI_STATUS_ASYNC_TDONE;
txlen = t->data_len;
qspi->async_tx_remain = txlen;
qspi->async_tx = t->tx_data;
aicos_dcache_clean_range(qspi->async_tx, txlen);
if (qspi->bus_width > 1)
qspi_hw_set_slave_output_en(base, 1);
qspi_hw_set_idma_tx_addr(base, (u32)t->tx_data);
qspi_hw_set_idma_tx_len(base, (u32)txlen);
qspi_hw_set_idma_tx_en(base, 1);
qspi_hw_interrupt_enable(base, ICR_BIT_IDMA_MSK | ICR_BIT_CS_INV_INTE);
} else if (t->rx_data) {
qspi->work_mode = QSPI_WORK_MODE_ASYNC_RX_DMA;
qspi->done_mask = HAL_QSPI_STATUS_ASYNC_TDONE;
rxlen = t->data_len;
qspi->async_rx_remain = rxlen;
qspi->async_rx = t->rx_data;
qspi_hw_set_slave_output_en(base, 0);
qspi_hw_set_idma_rx_addr(base, (u32)t->rx_data);
qspi_hw_set_idma_rx_len(base, (u32)rxlen);
qspi_hw_set_idma_rx_en(base, 1);
imsk = ICR_BIT_IDMA_MSK | ICR_BIT_CS_INV_INTE;
imsk &= ~ISTS_BIT_TF_UDR;
qspi_hw_interrupt_enable(base, imsk);
}
qspi_hw_clear_interrupt_status(base, ISTS_BIT_ALL_MSK);
return ret;
}
static int qspi_slave_can_dma(struct qspi_slave_state *qspi, struct qspi_transfer *t)
{
#ifdef AIC_DMA_DRV
if (t->tx_data) {
/* Meet DMA's address align requirement */
if (((unsigned long)t->tx_data) & (AIC_DMA_ALIGN_SIZE - 1))
return 0;
}
if (t->rx_data) {
/* RX: date length require 4 bytes alignment */
if (t->data_len & 0x3)
return 0;
/* Meet DMA's address align requirement */
if (((unsigned long)t->rx_data) & (AIC_DMA_ALIGN_SIZE - 1))
return 0;
}
return 1;
#else
return 0;
#endif
}
int hal_qspi_slave_transfer_async(qspi_slave_handle *h, struct qspi_transfer *t)
{
struct qspi_slave_state *qspi;
CHECK_PARAM(h, -EINVAL);
CHECK_PARAM(t, -EINVAL);
qspi = (struct qspi_slave_state *)h;
if (qspi_slave_can_dma(qspi, t))
return qspi_slave_transfer_dma_async(qspi, t);
return qspi_slave_transfer_cpu_async(qspi, t);
}
int hal_qspi_slave_transfer_abort(qspi_slave_handle *h)
{
struct qspi_slave_state *qspi;
u32 base;
qspi = (struct qspi_slave_state *)h;
base = qspi_hw_index_to_base(qspi->idx);
if (qspi->work_mode == QSPI_WORK_MODE_ASYNC_RX_CPU) {
qspi_hw_clear_interrupt_status(base, ISTS_BIT_ALL_MSK);
qspi_hw_interrupt_disable(base, ICR_BIT_ALL_MSK);
}
if (qspi->work_mode == QSPI_WORK_MODE_ASYNC_TX_CPU) {
qspi_hw_clear_interrupt_status(base, ISTS_BIT_ALL_MSK);
qspi_hw_interrupt_disable(base, ICR_BIT_ALL_MSK);
}
if (qspi->work_mode == QSPI_WORK_MODE_ASYNC_RX_DMA) {
qspi_hw_clear_interrupt_status(base, ISTS_BIT_ALL_MSK);
qspi_hw_interrupt_disable(base, ICR_BIT_ALL_MSK);
qspi_hw_set_idma_rx_en(base, 0);
qspi_hw_set_idma_rx_len(base, 0);
}
if (qspi->work_mode == QSPI_WORK_MODE_ASYNC_TX_DMA) {
qspi_hw_clear_interrupt_status(base, ISTS_BIT_ALL_MSK);
qspi_hw_interrupt_disable(base, ICR_BIT_ALL_MSK);
qspi_hw_set_idma_tx_en(base, 0);
qspi_hw_set_idma_tx_len(base, 0);
}
return 0;
}
int hal_qspi_slave_transfer_count(qspi_slave_handle *h)
{
struct qspi_slave_state *qspi;
qspi = (struct qspi_slave_state *)h;
if ((qspi->work_mode == QSPI_WORK_MODE_ASYNC_RX_CPU) ||
(qspi->work_mode == QSPI_WORK_MODE_ASYNC_RX_DMA)) {
return qspi->async_rx_count;
}
if ((qspi->work_mode == QSPI_WORK_MODE_ASYNC_TX_CPU) ||
(qspi->work_mode == QSPI_WORK_MODE_ASYNC_TX_DMA)) {
return qspi->async_tx_count;
}
return -1;
}
#endif

59
bsp/artinchip/hal/qspi/hal_qspi_v1x.c
View File

@@ -68,6 +68,7 @@ int hal_qspi_master_transfer_bit_mode(qspi_master_handle *h, struct qspi_bm_tran
if (!t->rx_bits_len && !t->tx_bits_len)
return -EINVAL;
qspi_hw_reset_fifo(base);
if (t->tx_data && t->rx_data) {
ret = qspi_hw_bit_mode_send_then_recv(base, t->tx_data, t->tx_bits_len,
t->rx_data, t->rx_bits_len);
@@ -392,7 +393,7 @@ int qspi_wait_transfer_done(u32 base, u32 tmo)
u32 cnt = 0;
while (qspi_hw_check_transfer_done(base) == false) {
aic_udelay(HAL_QSPI_WAIT_30_US);
aic_udelay(HAL_QSPI_WAIT_DELAY_US);
cnt++;
if (cnt > tmo)
return -ETIMEDOUT;
@@ -408,7 +409,7 @@ int qspi_fifo_write_data(u32 base, u8 *data, u32 len, u32 tmo)
while (len) {
free_len = QSPI_FIFO_DEPTH - qspi_hw_get_tx_fifo_cnt(base);
if (free_len <= (QSPI_FIFO_DEPTH >> 3)) {
aic_udelay(HAL_QSPI_WAIT_30_US);
aic_udelay(HAL_QSPI_WAIT_DELAY_US);
cnt++;
if (cnt > tmo)
return -ETIMEDOUT;
@@ -418,13 +419,13 @@ int qspi_fifo_write_data(u32 base, u8 *data, u32 len, u32 tmo)
qspi_hw_write_fifo(base, data, dolen);
data += dolen;
len -= dolen;
aic_udelay(HAL_QSPI_WAIT_30_US);
aic_udelay(HAL_QSPI_WAIT_DELAY_US);
cnt++;
}
/* Data are written to FIFO, waiting all data are sent out */
while (qspi_hw_get_tx_fifo_cnt(base)) {
aic_udelay(HAL_QSPI_WAIT_30_US);
aic_udelay(HAL_QSPI_WAIT_DELAY_US);
cnt++;
if (cnt > tmo)
return -ETIMEDOUT;
@@ -439,7 +440,7 @@ int qspi_fifo_read_data(u32 base, u8 *data, u32 len, u32 tmo)
while (len) {
dolen = qspi_hw_get_rx_fifo_cnt(base);
if (dolen == 0) {
aic_udelay(HAL_QSPI_WAIT_30_US);
aic_udelay(HAL_QSPI_WAIT_DELAY_US);
cnt++;
if (cnt > tmo)
return -ETIMEDOUT;
@@ -450,29 +451,35 @@ int qspi_fifo_read_data(u32 base, u8 *data, u32 len, u32 tmo)
qspi_hw_read_fifo(base, data, dolen);
data += dolen;
len -= dolen;
aic_udelay(HAL_QSPI_WAIT_30_US);
aic_udelay(HAL_QSPI_WAIT_DELAY_US);
cnt++;
}
return 0;
}
u32 qspi_calc_timeout(u32 bus_hz, u32 bw, u32 len)
u32 qspi_calc_timeout(u32 bus_hz, u32 len)
{
u32 tmo_cnt, tmo_us;
u32 tmo_speed = 100;
if (bus_hz < HAL_QSPI_MIN_FREQ_HZ)
tmo_us = (1000000 * (len * 8 / bw)) / bus_hz;
tmo_us = (1000000 * len * 8) / bus_hz;
else if (bus_hz < 1000000)
tmo_us = (1000 * (len * 8 / bw)) / (bus_hz / 1000);
tmo_us = (1000 * len * 8) / (bus_hz / 1000);
else
tmo_us = (len * 8 / bw) / (bus_hz / 1000000);
tmo_us = (len * 8) / (bus_hz / 1000000);
/* Add 100ms time padding */
tmo_us += 100000;
tmo_cnt = tmo_us / HAL_QSPI_WAIT_PER_CYCLE;
return tmo_cnt;
/* Consider the speed limit of DMA or CPU copy.
*/
if (len >= QSPI_TRANSFER_DATA_LEN_1M)
tmo_speed = ((len / QSPI_CPU_DMA_MIN_SPEED_MS) + 1) * 1000;
return max(tmo_cnt, tmo_speed);
}
static int qspi_master_transfer_cpu_sync(qspi_master_handle *h,
@@ -493,9 +500,10 @@ static int qspi_master_transfer_cpu_sync(qspi_master_handle *h,
if (t->data_len == 0)
return -EINVAL;
tmo_cnt = qspi_calc_timeout(qspi->bus_hz, qspi->bus_width, t->data_len);
tmo_cnt = qspi_calc_timeout(qspi->bus_hz, t->data_len);
/* CPU mode, spend more time */
tmo_cnt *= 10;
qspi_hw_reset_fifo(base);
if (t->tx_data) {
txlen = t->data_len;
@@ -539,7 +547,7 @@ static int qspi_master_wait_dma_done(struct aic_dma_chan *ch, u32 tmo)
u32 left, cnt = 0;
while (hal_dma_chan_tx_status(ch, &left) != DMA_COMPLETE && left) {
aic_udelay(HAL_QSPI_WAIT_30_US);
aic_udelay(HAL_QSPI_WAIT_DELAY_US);
cnt++;
if (cnt > tmo) {
return -ETIMEDOUT;
@@ -569,7 +577,8 @@ static int qspi_master_transfer_dma_sync(qspi_master_handle *h,
if (t->data_len == 0)
return -EINVAL;
tmo_cnt = qspi_calc_timeout(qspi->bus_hz, qspi->bus_width, t->data_len);
tmo_cnt = qspi_calc_timeout(qspi->bus_hz, t->data_len);
qspi_hw_reset_fifo(base);
if (t->tx_data) {
txlen = t->data_len;
@@ -588,7 +597,10 @@ static int qspi_master_transfer_dma_sync(qspi_master_handle *h,
dmacfg.src_addr_width = qspi->dma_cfg.mem_bus_width;
dmacfg.src_maxburst = qspi->dma_cfg.mem_max_burst;
dmacfg.dst_addr_width = qspi->dma_cfg.dev_bus_width;
if (!(txlen % HAL_QSPI_DMA_4BYTES_LINE))
dmacfg.dst_addr_width = qspi->dma_cfg.dev_bus_width;
else
dmacfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
dmacfg.dst_maxburst = qspi->dma_cfg.dev_max_burst;
ret = hal_dma_chan_config(dma_tx, &dmacfg);
@@ -609,16 +621,16 @@ static int qspi_master_transfer_dma_sync(qspi_master_handle *h,
goto out;
}
qspi_hw_start_transfer(base);
ret = qspi_wait_transfer_done(base, tmo_cnt);
if (ret < 0) {
hal_log_err("TX wait transfer done timeout.\n");
goto tx_stop;
}
ret = qspi_master_wait_dma_done(dma_tx, tmo_cnt);
if (ret < 0) {
hal_log_err("TX wait dma done timeout.\n");
goto tx_stop;
}
ret = qspi_wait_transfer_done(base, tmo_cnt);
if (ret < 0) {
hal_log_err("TX wait transfer done timeout.\n");
goto tx_stop;
}
tx_stop:
qspi_hw_tx_dma_disable(base);
hal_dma_chan_stop(dma_tx);
@@ -634,7 +646,10 @@ static int qspi_master_transfer_dma_sync(qspi_master_handle *h,
dmacfg.src_addr = (unsigned long)QSPI_REG_RXD(base);
dmacfg.dst_addr = (unsigned long)t->rx_data;
dmacfg.src_addr_width = qspi->dma_cfg.mem_bus_width;
if (!(rxlen % HAL_QSPI_DMA_4BYTES_LINE))
dmacfg.src_addr_width = qspi->dma_cfg.dev_bus_width;
else
dmacfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
dmacfg.src_maxburst = qspi->dma_cfg.mem_max_burst;
dmacfg.dst_addr_width = qspi->dma_cfg.dev_bus_width;
dmacfg.dst_maxburst = qspi->dma_cfg.dev_max_burst;
@@ -743,6 +758,7 @@ static int qspi_master_transfer_cpu_async(struct qspi_master_state *qspi,
if (t->data_len == 0)
return -EINVAL;
qspi_hw_reset_fifo(base);
qspi_hw_interrupt_disable(base, ICR_BIT_CPU_MSK);
qspi->status = HAL_QSPI_STATUS_IN_PROGRESS;
if (t->tx_data) {
@@ -822,6 +838,7 @@ static int qspi_master_transfer_dma_async(struct qspi_master_state *qspi,
if (t->data_len == 0)
return -EINVAL;
qspi_hw_reset_fifo(base);
qspi_hw_interrupt_disable(base, ICR_BIT_DMA_MSK);
qspi->status = HAL_QSPI_STATUS_IN_PROGRESS;
if (t->tx_data) {

71
bsp/artinchip/hal/qspi/hal_qspi_v2x.c
View File

@@ -64,6 +64,7 @@ int hal_qspi_master_transfer_bit_mode(qspi_master_handle *h, struct qspi_bm_tran
if (!t->rx_bits_len && !t->tx_bits_len)
return -EINVAL;
qspi_hw_reset_fifo(base);
if (t->tx_data && t->rx_data) {
ret = qspi_hw_bit_mode_send_then_recv(base, t->tx_data, t->tx_bits_len,
t->rx_data, t->rx_bits_len);
@@ -382,7 +383,7 @@ int qspi_wait_transfer_done(u32 base, u32 tmo)
u32 cnt = 0;
while (qspi_hw_check_transfer_done(base) == false) {
aic_udelay(HAL_QSPI_WAIT_30_US);
aic_udelay(HAL_QSPI_WAIT_DELAY_US);
cnt++;
if (cnt > tmo)
return -ETIMEDOUT;
@@ -396,7 +397,7 @@ int qspi_wait_gpdma_tx_done(u32 base, u32 tmo)
u32 cnt = 0;
while (qspi_hw_check_gpdma_tx_done(base) == false) {
aic_udelay(HAL_QSPI_WAIT_30_US);
aic_udelay(HAL_QSPI_WAIT_DELAY_US);
cnt++;
if (cnt > tmo)
return -ETIMEDOUT;
@@ -409,7 +410,7 @@ int qspi_wait_gpdma_rx_done(u32 base, u32 tmo)
u32 cnt = 0;
while (qspi_hw_check_gpdma_rx_done(base) == false) {
aic_udelay(HAL_QSPI_WAIT_30_US);
aic_udelay(HAL_QSPI_WAIT_DELAY_US);
cnt++;
if (cnt > tmo)
return -ETIMEDOUT;
@@ -425,7 +426,7 @@ int qspi_fifo_write_data(u32 base, u8 *data, u32 len, u32 tmo)
while (len) {
free_len = QSPI_FIFO_DEPTH - qspi_hw_get_tx_fifo_cnt(base);
if (free_len <= (QSPI_FIFO_DEPTH >> 3)) {
aic_udelay(HAL_QSPI_WAIT_30_US);
aic_udelay(HAL_QSPI_WAIT_DELAY_US);
cnt++;
if (cnt > tmo)
return -ETIMEDOUT;
@@ -435,13 +436,13 @@ int qspi_fifo_write_data(u32 base, u8 *data, u32 len, u32 tmo)
qspi_hw_write_fifo(base, data, dolen);
data += dolen;
len -= dolen;
aic_udelay(HAL_QSPI_WAIT_30_US);
aic_udelay(HAL_QSPI_WAIT_DELAY_US);
cnt++;
}
/* Data are written to FIFO, waiting all data are sent out */
while (qspi_hw_get_tx_fifo_cnt(base)) {
aic_udelay(HAL_QSPI_WAIT_30_US);
aic_udelay(HAL_QSPI_WAIT_DELAY_US);
cnt++;
if (cnt > tmo)
return -ETIMEDOUT;
@@ -456,7 +457,7 @@ int qspi_fifo_read_data(u32 base, u8 *data, u32 len, u32 tmo)
while (len) {
dolen = qspi_hw_get_rx_fifo_cnt(base);
if (dolen == 0) {
aic_udelay(HAL_QSPI_WAIT_30_US);
aic_udelay(HAL_QSPI_WAIT_DELAY_US);
cnt++;
if (cnt > tmo)
return -ETIMEDOUT;
@@ -467,29 +468,35 @@ int qspi_fifo_read_data(u32 base, u8 *data, u32 len, u32 tmo)
qspi_hw_read_fifo(base, data, dolen);
data += dolen;
len -= dolen;
aic_udelay(HAL_QSPI_WAIT_30_US);
aic_udelay(HAL_QSPI_WAIT_DELAY_US);
cnt++;
}
return 0;
}
u32 qspi_calc_timeout(u32 bus_hz, u32 bw, u32 len)
u32 qspi_calc_timeout(u32 bus_hz, u32 len)
{
u32 tmo_cnt, tmo_us;
u32 tmo_speed = 100;
if (bus_hz < HAL_QSPI_MIN_FREQ_HZ)
tmo_us = (1000000 * (len * 8 / bw)) / bus_hz;
tmo_us = (1000000 * len * 8) / bus_hz;
else if (bus_hz < 1000000)
tmo_us = (1000 * (len * 8 / bw)) / (bus_hz / 1000);
tmo_us = (1000 * len * 8) / (bus_hz / 1000);
else
tmo_us = (len * 8 / bw) / (bus_hz / 1000000);
tmo_us = (len * 8) / (bus_hz / 1000000);
/* Add 100ms time padding */
tmo_us += 100000;
tmo_cnt = tmo_us / HAL_QSPI_WAIT_PER_CYCLE;
return tmo_cnt;
/* Consider the speed limit of DMA or CPU copy.
*/
if (len >= QSPI_TRANSFER_DATA_LEN_1M)
tmo_speed = ((len / QSPI_CPU_DMA_MIN_SPEED_MS) + 1) * 1000;
return max(tmo_cnt, tmo_speed);
}
static int qspi_master_transfer_cpu_sync(qspi_master_handle *h,
@@ -510,9 +517,10 @@ static int qspi_master_transfer_cpu_sync(qspi_master_handle *h,
if (t->data_len == 0)
return -EINVAL;
tmo_cnt = qspi_calc_timeout(qspi->bus_hz, qspi->bus_width, t->data_len);
tmo_cnt = qspi_calc_timeout(qspi->bus_hz, t->data_len);
/* CPU mode, spend more time */
tmo_cnt *= 10;
qspi_hw_reset_fifo(base);
if (t->tx_data) {
txlen = t->data_len;
@@ -556,7 +564,7 @@ static int qspi_master_wait_dma_done(struct aic_dma_chan *ch, u32 tmo)
u32 left, cnt = 0;
while (hal_dma_chan_tx_status(ch, &left) != DMA_COMPLETE && left) {
aic_udelay(HAL_QSPI_WAIT_30_US);
aic_udelay(HAL_QSPI_WAIT_DELAY_US);
cnt++;
if (cnt > tmo) {
return -ETIMEDOUT;
@@ -586,7 +594,8 @@ static int qspi_master_transfer_dma_sync(qspi_master_handle *h,
if (t->data_len == 0)
return -EINVAL;
tmo_cnt = qspi_calc_timeout(qspi->bus_hz, qspi->bus_width, t->data_len);
tmo_cnt = qspi_calc_timeout(qspi->bus_hz, t->data_len);
qspi_hw_reset_fifo(base);
if (t->tx_data) {
txlen = t->data_len;
@@ -616,9 +625,9 @@ static int qspi_master_transfer_dma_sync(qspi_master_handle *h,
hal_log_err("TX dma chan config failure.\n");
goto out;
}
ret = hal_dma_chan_prep_device(dma_tx, PTR2U32(QSPI_REG_TXD(base)),
ret = hal_dma_prep_mode_device(dma_tx, PTR2U32(QSPI_REG_TXD(base)),
PTR2U32(t->tx_data), txlen,
DMA_MEM_TO_DEV);
DMA_MEM_TO_DEV, TYPE_IO_FAST);
if (ret < 0) {
hal_log_err("TX dma chan prepare failure.\n");
goto out;
@@ -629,16 +638,16 @@ static int qspi_master_transfer_dma_sync(qspi_master_handle *h,
goto out;
}
qspi_hw_start_transfer(base);
ret = qspi_wait_gpdma_tx_done(base, tmo_cnt);
if (ret < 0) {
hal_log_err("TX wait transfer done timeout.\n");
goto tx_stop;
}
ret = qspi_master_wait_dma_done(dma_tx, tmo_cnt);
if (ret < 0) {
hal_log_err("TX wait dma done timeout.\n");
goto tx_stop;
}
ret = qspi_wait_transfer_done(base, tmo_cnt);
if (ret < 0) {
hal_log_err("TX wait transfer done timeout.\n");
goto tx_stop;
}
tx_stop:
qspi_hw_tx_dma_disable(base);
hal_dma_chan_stop(dma_tx);
@@ -670,9 +679,9 @@ static int qspi_master_transfer_dma_sync(qspi_master_handle *h,
qspi_hw_dma_word_enable(base, false);
else
qspi_hw_dma_word_enable(base, true);
ret = hal_dma_chan_prep_device(dma_rx, PTR2U32(t->rx_data),
ret = hal_dma_prep_mode_device(dma_rx, PTR2U32(t->rx_data),
PTR2U32(QSPI_REG_RXD(base)), rxlen,
DMA_DEV_TO_MEM);
DMA_DEV_TO_MEM, TYPE_IO_FAST);
if (ret < 0) {
hal_log_err("RX dma chan prepare failure.\n");
goto out;
@@ -683,7 +692,7 @@ static int qspi_master_transfer_dma_sync(qspi_master_handle *h,
goto out;
}
qspi_hw_start_transfer(base);
ret = qspi_wait_gpdma_rx_done(base, tmo_cnt);
ret = qspi_wait_transfer_done(base, tmo_cnt);
if (ret < 0) {
hal_log_err("RX wait transfer done timeout.\n");
goto rx_stop;
@@ -769,6 +778,7 @@ static int qspi_master_transfer_cpu_async(struct qspi_master_state *qspi,
if (t->data_len == 0)
return -EINVAL;
qspi_hw_reset_fifo(base);
qspi_hw_interrupt_disable(base, ICR_BIT_CPU_MSK);
qspi->status = HAL_QSPI_STATUS_IN_PROGRESS;
if (t->tx_data) {
@@ -848,6 +858,7 @@ static int qspi_master_transfer_dma_async(struct qspi_master_state *qspi,
if (t->data_len == 0)
return -EINVAL;
qspi_hw_reset_fifo(base);
qspi_hw_interrupt_disable(base, ICR_BIT_DMA_MSK);
qspi->status = HAL_QSPI_STATUS_IN_PROGRESS;
if (t->tx_data) {
@@ -874,9 +885,9 @@ static int qspi_master_transfer_dma_async(struct qspi_master_state *qspi,
if (ret)
goto out;
hal_dma_chan_register_cb(dma_tx, qspi_master_dma_tx_callback, qspi);
ret = hal_dma_chan_prep_device(dma_tx, PTR2U32(QSPI_REG_TXD(base)),
ret = hal_dma_prep_mode_device(dma_tx, PTR2U32(QSPI_REG_TXD(base)),
PTR2U32(t->tx_data), txlen,
DMA_MEM_TO_DEV);
DMA_MEM_TO_DEV, TYPE_IO_FAST);
if (ret)
goto out;
ret = hal_dma_chan_start(dma_tx);
@@ -909,9 +920,9 @@ static int qspi_master_transfer_dma_async(struct qspi_master_state *qspi,
else
qspi_hw_dma_word_enable(base, true);
hal_dma_chan_register_cb(dma_rx, qspi_master_dma_rx_callback, qspi);
ret = hal_dma_chan_prep_device(dma_rx, PTR2U32(t->rx_data),
ret = hal_dma_prep_mode_device(dma_rx, PTR2U32(t->rx_data),
PTR2U32(QSPI_REG_RXD(base)), rxlen,
DMA_DEV_TO_MEM);
DMA_DEV_TO_MEM, TYPE_IO_FAST);
if (ret)
goto out;
ret = hal_dma_chan_start(dma_rx);

5
bsp/artinchip/hal/qspi/qspi_internal.h
View File

@@ -27,13 +27,16 @@ extern "C" {
#define QSPI_IS_ASYNC_ALL_DONE(sts, msk) ((sts & msk) == msk)
#define PTR2U32(p) ((u32)(unsigned long)(p))
#define QSPI_TRANSFER_DATA_LEN_1M 0x100000
#define QSPI_CPU_DMA_MIN_SPEED_MS (0x800000 >> 10)
void show_freq(char *msg, u32 id, u32 hz);
void hal_qspi_fifo_reset(u32 base, u32 fifo);
void hal_qspi_show_ists(u32 id, u32 sts);
int qspi_fifo_write_data(u32 base, u8 *data, u32 len, u32 tmo);
int qspi_fifo_read_data(u32 base, u8 *data, u32 len, u32 tmo_us);
int qspi_wait_transfer_done(u32 base, u32 tmo);
u32 qspi_calc_timeout(u32 bus_hz, u32 bw, u32 len);
u32 qspi_calc_timeout(u32 bus_hz, u32 len);
#ifdef __cplusplus
}

18
bsp/artinchip/hal/rtc/hal_rtc.c
View File

@@ -194,6 +194,19 @@ void aic_set_reboot_reason(enum aic_reboot_reason r)
pr_debug("Set reboot reason %d\n", r);
}
void aic_clr_reboot_reason_rtc(void)
{
u32 cur = 0;
cur = RTC_READB(RTC_REG_SYSBAK);
g_prev_reason = getbits(RTC_REBOOT_REASON_MASK, RTC_REBOOT_REASON_SHIFT,
cur);
if (g_prev_reason) {
/* Clear the previous state */
clrbits(RTC_REBOOT_REASON_MASK, cur);
RTC_WRITEB(cur, RTC_REG_SYSBAK);
}
}
enum aic_reboot_reason aic_get_reboot_reason(void)
{
u32 cur = 0;
@@ -203,11 +216,6 @@ enum aic_reboot_reason aic_get_reboot_reason(void)
cur = RTC_READB(RTC_REG_SYSBAK);
g_prev_reason = getbits(RTC_REBOOT_REASON_MASK,
RTC_REBOOT_REASON_SHIFT, cur);
if (g_prev_reason) {
/* Clear the previous state */
clrbits(RTC_REBOOT_REASON_MASK, cur);
RTC_WRITEB(cur, RTC_REG_SYSBAK);
}
}
return aic_judge_reboot_reason(wr, g_prev_reason);

30
bsp/artinchip/hal/syscfg/hal_syscfg.c
View File

@@ -137,7 +137,7 @@ enum syscfg_ldo18_cfg_ldo18_en_t {
#if defined(AIC_SYSCFG_DRV_V11) || defined(AIC_SYSCFG_DRV_V12)
#define SYSCFG_LDO1X_CFG 0x28
#define SYSCFG_LDO1X_CFG_LDO1X_VAL_SHIFT 0
#define SYSCFG_LDO1X_CFG_LDO1X_VAL_MASK GENMASK(2, 0)
#define SYSCFG_LDO1X_CFG_LDO1X_VAL_MASK GENMASK(3, 0)
#define SYSCFG_LDO1X_CFG_LDO1X_EN_SHIFT 4
#define SYSCFG_LDO1X_CFG_LDO1X_EN_MASK BIT(4)
#define SYSCFG_LDO1X_CFG_LDO1X_PD_FAST_SHIFT 5
@@ -352,20 +352,19 @@ static s32 syscfg_usb_init(void)
#endif
#if defined(AIC_USING_USB0_HOST) || defined(AIC_USING_USB0_OTG)
cfg_reg = SYSCFG_USB0_REXT;
cfg_reg = SYSCFG_USB0_REXT;
cfg = syscfg_readl(cfg_reg);
cfg &= SYSCFG_USB_RES_CAL_VAL_MASK;
cfg += SYSCFG_USB_RES_CAL_BIAS_DEF;
cfg &= SYSCFG_USB_RES_CAL_VAL_MASK;
cfg &= ~SYSCFG_USB_RES_CAL_VAL_MASK;
cfg |= SYSCFG_USB_RES_CAL_VAL_DEF;
cfg |= (1 << SYSCFG_USB_RES_CAL_EN_SHIFT);
syscfg_writel(cfg, cfg_reg);
#endif
#if defined(AIC_USING_USB1_HOST) || defined(AIC_USING_USB1_OTG)
cfg_reg = SYSCFG_USB1_REXT;
cfg &= SYSCFG_USB_RES_CAL_VAL_MASK;
cfg += SYSCFG_USB_RES_CAL_BIAS_DEF;
cfg &= SYSCFG_USB_RES_CAL_VAL_MASK;
cfg_reg = SYSCFG_USB1_REXT;
cfg = syscfg_readl(cfg_reg);
cfg &= ~SYSCFG_USB_RES_CAL_VAL_MASK;
cfg |= SYSCFG_USB_RES_CAL_VAL_DEF;
cfg |= (1 << SYSCFG_USB_RES_CAL_EN_SHIFT);
syscfg_writel(cfg, cfg_reg);
#endif
@@ -479,10 +478,9 @@ static void syscfg_ldo25_xspi_init(void)
#endif
#if defined(AIC_SYSCFG_DRV_V11) || defined(AIC_SYSCFG_DRV_V12)
#define LDO1X_DISABLE_BIT4_6_VAL_STEP1 0x30
#define LDO1X_DISABLE_BIT4_6_VAL_STEP2 0x70
#define LDO1X_DISABLE_BIT4_6_VAL_STEP3 0x60
#define LDO1X_DISABLE_BIT4_6_VAL_STEP4 0x40
#define LDO1X_DISABLE_BIT4_6_VAL_STEP1 0x00
#define LDO1X_DISABLE_BIT4_6_VAL_STEP2 0x50
#define LDO1X_DISABLE_BIT4_6_VAL_STEP3 0x40
static void syscfg_ldo1x_init(u8 status, u8 v_level)
{
u32 val = 0;
@@ -506,12 +504,8 @@ static void syscfg_ldo1x_init(u8 status, u8 v_level)
val = 0;
val |= (LDO1X_DISABLE_BIT4_6_VAL_STEP3 | v_level);
syscfg_writel(val, SYSCFG_LDO1X_CFG);
val = 0;
val |= (LDO1X_DISABLE_BIT4_6_VAL_STEP4 | v_level);
syscfg_writel(val, SYSCFG_LDO1X_CFG);
}
aicos_udelay(10);
aicos_udelay(100);
}
#endif

63
bsp/artinchip/hal/tsen/hal_tsen.c
View File

@@ -43,6 +43,9 @@
#define TSENn_CFG_DIFF_MODE_SELECT BIT(31)
#define TSENn_CFG_INVERTED_SELECT BIT(27)
#define TSENn_CFG_ADC_ACQ_VAL 0xff
#define TSENn_CFG_ADC_ACQ_SHIFT 8
#define TSENn_CFG_ADC_ACQ_MASK GENMASK(15, 8)
#define TSENn_CFG_HIGH_ADC_PRIORITY BIT(4)
#define TSENn_CFG_PERIOD_SAMPLE_EN BIT(1)
#define TSENn_CFG_SINGLE_SAMPLE_EN BIT(0)
@@ -102,6 +105,9 @@
#define TSEN_CP_VERSION_SHIFT 20
#define TSEN_SINGLE_POINT_CALI_K -1151
#elif defined(AIC_SID_DRV_V11)
#define TSEN_CP_VERSION_OFFSET 0x1C
#define TSEN_CP_VERSION_MASK 0x3f
#define TSEN_CP_VERSION_SHIFT 20
#define TSEN_THS0_ADC_VAL_LOW_OFFSET 0x2c
#define TSEN_THS_ENV_TEMP_LOW_OFFSET 0x2c
#define TSEN_THS0_ADC_VAL_HIGH_OFFSET 0x34
@@ -113,6 +119,9 @@
#define TSEN_THS_ENV_TEMP_HIGH_SHIFT 24
#define TSEN_SINGLE_POINT_CALI_K 940
#elif defined(AIC_SID_DRV_V12)
#define TSEN_CP_VERSION_OFFSET 0x1C
#define TSEN_CP_VERSION_MASK 0x3f
#define TSEN_CP_VERSION_SHIFT 20
#define TSEN_THS0_ADC_VAL_LOW_OFFSET 0x0c
#define TSEN_THS_ENV_TEMP_LOW_OFFSET 0x0c
#define TSEN_THS0_ADC_VAL_LOW_MASK 0xfff
@@ -130,6 +139,8 @@
#define TSEN_ENV_TEMP_HIGH_SIGN_MASK BIT(7)
#define TSEN_CP_VERSION_DIFF_TYPE 0xA
static u32 aic_tsen_ch_num = 0; // the number of available sensor
extern struct aic_tsen_ch aic_tsen_chs[AIC_TSEN_CH_NUM];
static inline void tsen_writel(u32 val, int reg)
{
@@ -183,6 +194,32 @@ u16 hal_tsen_temp2data(struct aic_tsen_ch *chan, s32 temp)
return (u16)data;
}
void hal_tsen_set_ch_num(u32 num)
{
aic_tsen_ch_num = num;
}
struct aic_tsen_ch *hal_tsen_get_valid_ch(u32 ch)
{
s32 i;
if (ch >= AIC_TSEN_CH_NUM) {
pr_err("Invalid channel %d\n", ch);
return NULL;
}
for (i = 0; i < aic_tsen_ch_num; i++) {
if (!aic_tsen_chs[i].available)
continue;
if (aic_tsen_chs[i].id == ch)
return &aic_tsen_chs[i];
}
pr_warn("Ch%d is unavailable!\n", ch);
return NULL;
}
#ifdef AIC_SID_DRV
int hal_tsen_efuse_read(u32 addr, u32 *data, u32 size)
{
@@ -355,15 +392,18 @@ void hal_tsen_double_point_cali(struct aic_tsen_ch *chan)
#ifdef AIC_SID_DRV
void hal_tsen_curve_fitting(struct aic_tsen_ch *chan)
{
#ifdef AIC_TSEN_DRV_V10
int cp_version;
u32 data = 0;
hal_tsen_efuse_read(TSEN_CP_VERSION_OFFSET, &data,
TSEN_EFUSE_STANDARD_LENGTH);
cp_version = data >> TSEN_CP_VERSION_SHIFT & TSEN_CP_VERSION_MASK;
if (!cp_version)
return;
hal_log_debug("CP version:%d\n", cp_version);
#ifdef AIC_TSEN_DRV_V10
if (cp_version >= TSEN_CP_VERSION_DIFF_TYPE) {
hal_tsen_single_point_cali(chan);
} else {
@@ -432,7 +472,15 @@ static void tsen_int_enable(u32 ch, u32 enable, u32 detail)
static void tsen_single_mode(u32 ch)
{
u32 val = 0;
tsen_writel(TSENn_FIL_8_POINTS, TSENn_FIL(ch));
val = tsen_readl(TSENn_CFG(ch));
val &= ~TSENn_CFG_ADC_ACQ_MASK;
val |= TSENn_CFG_ADC_ACQ_VAL << TSENn_CFG_ADC_ACQ_SHIFT;
tsen_writel(val, TSENn_CFG(ch));
tsen_writel(TSENn_CFG_SINGLE_SAMPLE_EN | tsen_readl(TSENn_CFG(ch)),
TSENn_CFG(ch));
@@ -474,6 +522,11 @@ static void tsen_period_mode(struct aic_tsen_ch *chan, u32 pclk)
val = tsen_sec2itv(pclk, chan->smp_period);
tsen_writel(val << TSENn_ITV_SHIFT | 0xFFFF, TSENn_ITV(chan->id));
val = tsen_readl(TSENn_CFG(chan->id));
val &= ~TSENn_CFG_ADC_ACQ_MASK;
val |= TSENn_CFG_ADC_ACQ_VAL << TSENn_CFG_ADC_ACQ_SHIFT;
tsen_writel(val, TSENn_CFG(chan->id));
tsen_writel(tsen_readl(TSENn_CFG(chan->id)) | TSENn_CFG_PERIOD_SAMPLE_EN,
TSENn_CFG(chan->id));
@@ -556,21 +609,22 @@ void hal_tsen_status_show(struct aic_tsen_ch *chan)
}
// TODO: irq_handle() should get 'struct aic_tsen_ch *' from 'void *arg'
extern struct aic_tsen_ch aic_tsen_chs[AIC_TSEN_CH_NUM];
irqreturn_t hal_tsen_irq_handle(int irq, void *arg)
{
int i, status, detail = 0;
struct aic_tsen_ch *chan = NULL;
aicos_irq_disable(TSEN_IRQn);
status = tsen_readl(TSEN_INTR);
hal_log_debug("Module IRQ status: %#x\n", status);
for (i = 0; i < AIC_TSEN_CH_NUM; i++) {
if (!(status & TSEN_INTR_CH_INT_FLAG(i)))
continue;
chan = &aic_tsen_chs[i];
chan = hal_tsen_get_valid_ch(i);
if (!chan)
continue;
detail = tsen_readl(TSENn_INT(i));
tsen_writel(detail, TSENn_INT(i));
hal_log_debug("ch%d IRQ status: %#x\n", i, detail);
@@ -602,7 +656,6 @@ irqreturn_t hal_tsen_irq_handle(int irq, void *arg)
hal_tsen_data2temp(chan), chan->latest_data);
}
aicos_irq_enable(TSEN_IRQn);
hal_log_debug("IRQ status %#x, detail %#x\n", status, detail);
return IRQ_HANDLED;

44
bsp/artinchip/hal/uart/aic_hal_uart.c
View File

@@ -356,16 +356,21 @@ int32_t hal_usart_config_func(usart_handle_t handle, usart_func_e func)
aic_usart_reg_t *addr = (aic_usart_reg_t *)(usart_priv->base);
aic_usart_exreg_t *exaddr = (aic_usart_exreg_t *)(usart_priv->base + AIC_UART_EXREG);
if (func == USART_FUNC_RS485 || func == USART_FUNC_RS485_COMACT_IO)
if (func == USART_FUNC_RS485 || func == USART_FUNC_RS485_COMACT_IO ||
func == USART_FUNC_RS485_SIMULATION)
{
addr->MCR &= AIC_UART_MCR_FUNC_MASK;
if(func == USART_FUNC_RS485_COMACT_IO)
addr->MCR |= AIC_UART_MCR_RS485S;
else
if (func == USART_FUNC_RS485 || func == USART_FUNC_RS485_SIMULATION)
addr->MCR |= AIC_UART_MCR_RS485;
else
addr->MCR |= AIC_UART_MCR_RS485S;
exaddr->RS485CTL |= AIC_UART_RS485_RXBFA;
exaddr->RS485CTL |= AIC_UART_RS485_RXAFA;
exaddr->RS485CTL &= ~AIC_UART_RS485_CTL_MODE;
if (func == USART_FUNC_RS485_SIMULATION)
exaddr->RS485CTL |= AIC_UART_RS485_CTL_MODE;
}
else if (func == USART_MODE_RS232_AUTO_FLOW_CTRL)
{
@@ -495,16 +500,15 @@ int32_t hal_usart_halt_tx_enable(usart_handle_t handle, uint8_t halt_tx_enable)
aic_usart_priv_t *usart_priv = handle;
aic_usart_reg_t *addr = (aic_usart_reg_t *)(usart_priv->base);
if (halt_tx_enable == HALT_HALT_TX_ENABLE) {
addr->HALT |= HALT_HALT_TX_ENABLE;
if (halt_tx_enable == HALT_TX_ENABLE) {
addr->HALT |= HALT_TX_ENABLE;
} else {
addr->HALT &= (~HALT_HALT_TX_ENABLE);
addr->HALT &= (~HALT_TX_ENABLE);
}
return 0;
}
/**
\brief interrupt service function for transmitter holding register empty.
\param[in] usart_priv usart private to operate.
@@ -1302,9 +1306,11 @@ inline int32_t hal_usart_rts_ctl_soft_mode_set(usart_handle_t handle)
{
USART_NULL_PARAM_CHK(handle);
aic_usart_priv_t *usart_priv = handle;
aic_usart_reg_t *addr = (aic_usart_reg_t *)(usart_priv->base);
while (addr->USR & USR_UART_BUSY) {};
addr->MCR &= ~AIC_UART_MCR_RTS_CTRL;
aic_usart_exreg_t *exaddr = (aic_usart_exreg_t *)(usart_priv->base + AIC_UART_EXREG);
exaddr->RS485CTL |= AIC_UART_RS485_CTL_MODE;
return 0;
}
@@ -1312,13 +1318,15 @@ inline int32_t hal_usart_rts_ctl_soft_mode_clr(usart_handle_t handle)
{
USART_NULL_PARAM_CHK(handle);
aic_usart_priv_t *usart_priv = handle;
aic_usart_reg_t *addr = (aic_usart_reg_t *)(usart_priv->base);
while (addr->USR & USR_UART_BUSY) {};
addr->MCR |= AIC_UART_MCR_RTS_CTRL;
aic_usart_exreg_t *exaddr = (aic_usart_exreg_t *)(usart_priv->base + AIC_UART_EXREG);
exaddr->RS485CTL &= ~AIC_UART_RS485_CTL_MODE;
return 0;
}
#if defined (RT_SERIAL_USING_DMA)
#if defined (AIC_SERIAL_USING_DMA)
int32_t hal_uart_set_fifo(usart_handle_t handle)
{
USART_NULL_PARAM_CHK(handle);
@@ -1455,14 +1463,15 @@ int32_t hal_uart_rx_dma_config(usart_handle_t handle, uint8_t *buf, uint32_t siz
usart_priv->dma_rx_info.buf = buf;
usart_priv->dma_rx_info.buf_size = size;
config.direction = DMA_DEV_TO_MEM;
config.slave_id = DMA_ID_UART0 + usart_priv->idx;
config.direction = DMA_DEV_TO_MEM;
config.src_maxburst = 1;
config.dst_maxburst = 1;
config.src_addr = (UART0_BASE + usart_priv->idx * AIC_UART_BASE_OFFSET);
config.dst_addr = (unsigned long)usart_priv->dma_rx_info.buf;
config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
config.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
info = &usart_priv->dma_rx_info;
info->dma_chan = hal_request_dma_chan();
@@ -1497,13 +1506,14 @@ int32_t hal_uart_send_by_dma(usart_handle_t handle, uint8_t *buf, uint32_t size)
hal_usart_set_hsk(usart_priv);
usart_priv->dma_tx_info.buf = buf;
usart_priv->dma_tx_info.buf_size = transfer_size;
config.direction = DMA_MEM_TO_DEV;
config.slave_id = DMA_ID_UART0 + usart_priv->idx;
config.direction = DMA_MEM_TO_DEV;
config.src_maxburst = 1;
config.dst_maxburst = 1;
config.src_addr = (unsigned long)usart_priv->dma_tx_info.buf;
config.dst_addr = (UART0_BASE + usart_priv->idx * AIC_UART_BASE_OFFSET);
config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
config.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
info = &usart_priv->dma_tx_info;

41
bsp/artinchip/hal/wri/hal_wri.c
View File

@@ -45,7 +45,8 @@
#define WRI_FLAG_SP_WDOG_SYS_RST BIT(16)
#define WRI_FLAG_THS_RST BIT(9)
#define WRI_FLAG_PIN_RST BIT(8)
#define WRI_FLAG_RTC_POR BIT(2)
#define WRI_FLAG_RTC_POR BIT(3)
#define WRI_FLAG_VDD11_C908_POR BIT(2)
#define WRI_FLAG_VDD11_SW_POR BIT(1)
#define WRI_FLAG_VDD11_SP_POR BIT(0)
#endif
@@ -78,7 +79,6 @@ enum aic_warm_reset_type aic_wr_type_get(void)
if (!val)
return WRI_TYPE_POR;
writel(val, WRI_RST_FLAG); /* clear the flag */
for (i = WRI_TYPE_MAX - 1; i >= 0; i--) {
if (val & wr_bit[i]) {
g_last_reboot.hw_reason = (enum aic_warm_reset_type)i;
@@ -100,8 +100,11 @@ enum aic_reboot_reason aic_judge_reboot_reason(enum aic_warm_reset_type hw,
printf("Reboot action: Watchdog-Reset, reason: ");
switch (sw) {
case REBOOT_REASON_BL_UPGRADE:
printf("Bootloader Upgrade-Mode\n");
break;
case REBOOT_REASON_UPGRADE:
printf("Upgrade-Mode\n");
printf("BROM Upgrade-Mode\n");
break;
case REBOOT_REASON_CMD_REBOOT:
printf("Command-Reboot\n");
@@ -182,6 +185,7 @@ enum aic_warm_reset_type aic_wr_type_get(void)
u32 val = 0;
u32 wr_bit[WRI_TYPE_MAX] = {WRI_FLAG_VDD11_SP_POR,
WRI_FLAG_VDD11_SW_POR,
WRI_FLAG_VDD11_C908_POR,
WRI_FLAG_RTC_POR,
WRI_FLAG_PIN_RST,
WRI_FLAG_THS_RST,
@@ -210,7 +214,6 @@ enum aic_warm_reset_type aic_wr_type_get(void)
if (!val)
return WRI_TYPE_VDD11_SP_POR;
writel(val, WRI_RST_FLAG); /* clear the flag */
for (i = WRI_TYPE_MAX - 1; i >= 0; i--) {
if (val & wr_bit[i]) {
g_last_reboot.hw_reason = (enum aic_warm_reset_type)i;
@@ -316,6 +319,11 @@ enum aic_reboot_reason aic_judge_reboot_reason(enum aic_warm_reset_type hw,
return (enum aic_reboot_reason)sw;
}
if (hw == WRI_TYPE_VDD11_C908_POR) {
printf("Startup reason: C908 Power-On-Reset\n");
return (enum aic_reboot_reason)sw;
}
printf("Reboot action: Warm-Reset, reason: ");
switch (hw) {
case WRI_TYPE_RTC_POR:
@@ -370,6 +378,26 @@ enum aic_reboot_reason aic_judge_reboot_reason(enum aic_warm_reset_type hw,
}
#endif
void aic_clr_reboot_reason()
{
u32 val = 0;
val = readl(WRI_RST_FLAG);
writel(val, WRI_RST_FLAG); /* clear the flag */
#if defined(AIC_WRI_DRV_V12)
val = readl_bits(WRI_REBOOT_REASON_MASK, WRI_REBOOT_REASON_SHIFT,
WRI_BOOT_INFO);
if (val) {
clrbits(WRI_BOOT_INFO, val);
writel(val, WRI_BOOT_INFO);
}
#else
aic_clr_reboot_reason_rtc();
#endif
return;
}
#if defined(AIC_WRI_DRV_V12)
void aic_set_reboot_reason(enum aic_reboot_reason r)
@@ -404,11 +432,6 @@ enum aic_reboot_reason aic_get_reboot_reason(void)
g_last_reboot.reason = aic_judge_reboot_reason(hw, val);
g_last_reboot.inited = 1;
if (val) {
clrbits(WRI_BOOT_INFO, val);
writel(val, WRI_BOOT_INFO);
}
return g_last_reboot.reason;
}