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V1.0.5

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刘可亮
2024-06-04 19:00:30 +08:00
parent 990c72f5be
commit 0a13af6a1d
1668 changed files with 342810 additions and 37726 deletions
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2
bsp/artinchip/hal/cmu/aic_hal_clk_def_v10.c
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@@ -213,7 +213,7 @@ DISPCLK(CLK_SCLK, "sclk", CLK_PLL_FRA2, PARENT("pll_fra2"), CLK_DISP_REG, 0, 3,
/* Clock cfg array */
const struct aic_clk_comm_cfg *aic_clk_cfgs[AIC_CLK_END] = {
const struct aic_clk_comm_cfg *aic_clk_cfgs[AIC_CLK_NUM] = {
/* Fixed rate clock */
DUMMY_CFG(CLK_DUMMY),
AIC_CLK_CFG(CLK_OSC24M),