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V1.0.5

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刘可亮
2024-06-04 19:00:30 +08:00
parent 990c72f5be
commit 0a13af6a1d
1668 changed files with 342810 additions and 37726 deletions
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2
bsp/artinchip/sys/d13x/Kconfig.chip
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@@ -491,7 +491,7 @@ config AIC_TSEN_DRV_VER
config AIC_TSEN_CH_NUM
int
default 1 if AIC_TSEN_DRV_V20
default 2 if AIC_TSEN_DRV_V20
#--------------------------------------------
# GPAI driver global option

BIN
bsp/artinchip/sys/d13x/d13x.pbp
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170
bsp/artinchip/sys/d13x/include/aic_clk_id.h
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@@ -11,90 +11,92 @@
extern "C" {
#endif
/* Fixed rate clock */
#define CLK_DUMMY 0
#define CLK_OSC24M 1
#define CLK_OSC32K 2
/* PLL clock */
#define CLK_PLL_INT0 3
#define CLK_PLL_INT1 4
#define CLK_PLL_FRA0 5
#define CLK_PLL_FRA2 6
/* fixed factor clock */
#define CLK_AXI_AHB_SRC1 7
#define CLK_APB0_SRC1 8
#define CLK_CPU_SRC1 9
/* system clock */
#define CLK_AXI0 10
#define CLK_AHB0 11
#define CLK_APB0 12
#define CLK_APB1 13
#define CLK_CPU 14
/* Peripheral clock */
#define CLK_WDT 15
#define CLK_DMA 16
#define CLK_CE 17
#define CLK_USBD 18
#define CLK_USBH0 19
#define CLK_USB_PHY0 20
#define CLK_GMAC0 21
#define CLK_XSPI 22
#define CLK_QSPI0 23
#define CLK_QSPI1 24
#define CLK_QSPI2 25
#define CLK_QSPI3 26
#define CLK_SDMC0 27
#define CLK_SDMC1 28
#define CLK_PBUS 29
#define CLK_SYSCFG 30
#define CLK_SPIENC 31
#define CLK_MTOP 32
#define CLK_I2S0 33
#define CLK_AUDIO_SCLK 34
#define CLK_CODEC 35
#define CLK_GPIO 36
#define CLK_UART0 37
#define CLK_UART1 38
#define CLK_UART2 39
#define CLK_UART3 40
#define CLK_UART4 41
#define CLK_UART5 42
#define CLK_UART6 43
#define CLK_UART7 44
#define CLK_RGB 45
#define CLK_LVDS 46
#define CLK_MIPIDSI 47
#define CLK_DVP 48
#define CLK_DE 49
#define CLK_GE 50
#define CLK_VE 51
#define CLK_SID 52
#define CLK_RTC 53
#define CLK_GTC 54
#define CLK_I2C0 55
#define CLK_I2C1 56
#define CLK_I2C2 57
#define CLK_CAN0 58
#define CLK_CAN1 59
#define CLK_PWM 60
#define CLK_ADCIM 61
#define CLK_GPAI 62
#define CLK_RTP 63
#define CLK_TSEN 64
#define CLK_CIR 65
#define CLK_PSADC 66
#define CLK_CMP
#define CLK_PWMCS 67
#define CLK_PWMCS_SDFM 68
/* Display clock */
#define CLK_PIX 69
#define CLK_SCLK 70
/* Output clock */
#define CLK_OUT0 71
#define CLK_OUT1 72
#define CLK_OUT2 73
#define CLK_OUT3 74
#define AIC_CLK_END 75
enum clk_id {
/* Fixed rate clock */
CLK_DUMMY,
CLK_OSC24M,
CLK_OSC32K,
/* PLL clock */
CLK_PLL_INT0,
CLK_PLL_INT1,
CLK_PLL_FRA0,
CLK_PLL_FRA2,
/* fixed factor clock */
CLK_AXI_AHB_SRC1,
CLK_APB0_SRC1,
CLK_CPU_SRC1,
/* system clock */
CLK_AXI0,
CLK_AHB0,
CLK_APB0,
CLK_APB1,
CLK_CPU,
/* Peripheral clock */
CLK_WDT,
CLK_DMA,
CLK_CE,
CLK_USBD,
CLK_USBH0,
CLK_USB_PHY0,
CLK_GMAC0,
CLK_XSPI,
CLK_QSPI0,
CLK_QSPI1,
CLK_QSPI2,
CLK_QSPI3,
CLK_SDMC0,
CLK_SDMC1,
CLK_PBUS,
CLK_SYSCFG,
CLK_SPIENC,
CLK_MTOP,
CLK_I2S0,
CLK_AUDIO_SCLK,
CLK_CODEC,
CLK_GPIO,
CLK_UART0,
CLK_UART1,
CLK_UART2,
CLK_UART3,
CLK_UART4,
CLK_UART5,
CLK_UART6,
CLK_UART7,
CLK_RGB,
CLK_LVDS,
CLK_MIPIDSI,
CLK_DVP,
CLK_DE,
CLK_GE,
CLK_VE,
CLK_SID,
CLK_RTC,
CLK_GTC,
CLK_I2C0,
CLK_I2C1,
CLK_I2C2,
CLK_CAN0,
CLK_CAN1,
CLK_PWM,
CLK_ADCIM,
CLK_GPAI,
CLK_RTP,
CLK_TSEN,
CLK_CIR,
CLK_PSADC,
CLK_CMP,
CLK_PWMCS,
CLK_PWMCS_SDFM,
/* Display clock */
CLK_PIX,
CLK_SCLK,
/* Output clock */
CLK_OUT0,
CLK_OUT1,
CLK_OUT2,
CLK_OUT3,
AIC_CLK_NUM,
};
/* frequence */

11
bsp/artinchip/sys/d13x/include/ram_param.h Normal file
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@@ -0,0 +1,11 @@
/*
* Copyright (C) 2024 ArtInChip Technology Co.,Ltd
* Author: Xiong Hao <hao.xiong@artinchip.com>
*/
#ifndef __RAM_PARAM_H__
#define __RAM_PARAM_H__
u32 aic_get_ram_size(void);
#endif /* __RAM_PARAM_H__ */

104
bsp/artinchip/sys/d13x/ram_param.c Normal file
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@@ -0,0 +1,104 @@
/*
* Copyright (C) 2024 ArtInChip Technology Co.,Ltd
* Author: Xiong Hao <hao.xiong@artinchip.com>
*/
#include <stdio.h>
#include <aic_core.h>
#include <aic_common.h>
#include <ram_param.h>
#define PSRAM_SINGLE 0
#define PSRAM_PARALLEL 1
enum PSRAM_FUSE_ID {
APS3208K = 0x00,
SCKW18_12816O = 0x01,
APS12816O = 0x02,
};
struct _psram_id {
u8 psram_fuse_id;
u32 psram_chip_id;
};
struct _psram_info {
u8 mark_id;
u8 psram_num;
u32 psram_size;
struct _psram_id psram_id;
};
#define PSRAM_TABLE_INFO \
{ \
/* force use the cfg0 */ \
{0x0, 0, 0, {0, 0}}, \
/* D131BAS 4M */ \
{0x01, PSRAM_SINGLE, 0x400000, {APS3208K, 0x80c980c9}}, \
/* D131BBS 8M */ \
{0x02, PSRAM_PARALLEL, 0x800000, {APS3208K, 0x80c980c9}}, \
/* D131CBS 8M */ \
{0x03, PSRAM_PARALLEL, 0x800000, {APS3208K, 0x80c980c9}}, \
/* D131EBS 8M */ \
{0x04, PSRAM_PARALLEL, 0x800000, {APS3208K, 0x80c980c9}}, \
/* D132ENS 8M */ \
{0x05, PSRAM_PARALLEL, 0x800000, {APS3208K, 0x80c980c9}}, \
/* D131CCS1 16M SCKW18X128160AAE1 */ \
{0x06, PSRAM_PARALLEL, 0x1000000, {SCKW18_12816O, 0xc59ac59a}}, \
/* D131CCS2 16M AP12816*/ \
{0x06, PSRAM_PARALLEL, 0x1000000, {APS12816O, 0xdd8ddd8d}}, \
/* D133ECS1 16M SCKW18X128160AAE1*/ \
{0x07, PSRAM_PARALLEL, 0x1000000, {SCKW18_12816O, 0xc59ac59a}}, \
/* D133ECS2 16M AP12816*/ \
{0x07, PSRAM_PARALLEL, 0x1000000, {APS12816O, 0xdd8ddd8d}}, \
/* M6801SPDS NON PSRAM*/ \
{0x31, 0, 0, {0, 0}}, \
/* M6806SPES NON PSRAM*/ \
{0x32, 0, 0, {0, 0}}, \
}
struct _psram_info psram_table_info[] = PSRAM_TABLE_INFO;
u8 psram_get_mark_id(void)
{
u32 fuse_218 = readl(0x19010218);
u8 mark_id = fuse_218 & 0xff;
pr_info("fuse_218(0x19010218)=0x%x, mark_id=0x%x\n", fuse_218, mark_id);
return mark_id;
}
u8 psram_get_psram_id(void)
{
u32 fuse_224 = readl(0x19010224);
u8 psram_id = (fuse_224 & 0xff0000) >> 20;
pr_info("fuse_224(0x19010224)=0x%x, psram_id=0x%x\n", fuse_224, psram_id);
return psram_id;
}
struct _psram_info *psram_get_info(u8 mark_id, u8 psram_fuse_id)
{
u32 len = ARRAY_SIZE(psram_table_info);
for (int i = 0; i < len; i++) {
if (((mark_id == psram_table_info[i].mark_id) &&
(psram_fuse_id == psram_table_info[i].psram_id.psram_fuse_id))) {
return &psram_table_info[i];
}
}
pr_info("can't get the psram table, return the default info.\n");
return &psram_table_info[0]; //if not find anyone, return the default info.
}
u32 aic_get_ram_size(void)
{
struct _psram_info *psram_info;
u8 mark_id, psram_id;
mark_id = psram_get_mark_id();
psram_id = psram_get_psram_id();
psram_info = psram_get_info(mark_id, psram_id);
return psram_info->psram_size;
}