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v1.2.1

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This commit is contained in:
刘可亮
2025-07-22 11:15:46 +08:00
parent d164b333ed
commit 11c97ef399
2870 changed files with 951307 additions and 26675 deletions
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18
bsp/artinchip/include/drv/aic_drv_de.h Normal file
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@@ -0,0 +1,18 @@
/*
* Copyright (C) 2025, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: Huahui <huahui.mai@artinchip.com>
*/
#ifndef _UAPI_ARTINCHIP_DE_H_
#define _UAPI_ARTINCHIP_DE_H_
typedef void (*de_vsync_cb)(void *data);
/* Atomic callback, will called from DE VSYNC INTERRUPT context */
void de_register_vsync_cb(de_vsync_cb cb, void *data);
void de_unregister_vsync_cb(void);
#endif /* _UAPI_ARTINCHIP_DE_H_ */

3
bsp/artinchip/include/drv/drv_dvp.h
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@@ -23,7 +23,8 @@
#define AIC_DVP_QOS_HIGH 0xB
#define AIC_DVP_QOS_LOW 0x7
#ifdef AIC_USING_BARCODE_DEMO
#if defined(AIC_USING_BARCODE_DEMO) || defined(AIC_MPP_RECORDER_INTERFACE) \
|| defined(LPKG_CHERRYUSB_DEVICE_VIDEO_DVP_TEMPLATE)
#define AIC_DVP_IGNORE_LOSS
#endif

4
bsp/artinchip/include/drv/drv_spienc.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2023, ArtInChip Technology Co., Ltd
* Copyright (c) 2023-2025, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -13,6 +13,8 @@
int drv_spienc_init(void);
void drv_spienc_set_cfg(u32 spi_bus, u32 addr, u32 cpos, u32 clen);
void drv_spienc_xip_enable(void);
void drv_spienc_xip_disable(void);
void drv_spienc_start(void);
void drv_spienc_stop(void);
int drv_spienc_check_empty(void);

6
bsp/artinchip/include/drv/pm_cfg.h
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@@ -38,9 +38,15 @@ enum pm_module_id {
PM_DE_ID,
PM_GE_ID,
PM_VE_ID,
PM_USB_HOST_ID,
PM_USB_DEV_ID,
PM_MODULE_MAX_ID, /* enum must! */
};
#ifdef AIC_PM_INDEPENDENT_POWER_KEY
#define PM_BUSY_SLEEP_MODE PM_SLEEP_MODE_NONE
#endif
#ifdef AIC_USING_PM
void rt_pm_set_pin_wakeup_source(rt_base_t pin);
void rt_pm_clear_pin_wakeup_source(rt_base_t pin);

5
bsp/artinchip/include/drv_bare/mmc.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
* Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -349,6 +349,9 @@ int mmc_block_init(struct aic_sdmc *host);
int mmc_block_refresh(struct aic_sdmc *host);
int mmc_block_deinit(struct aic_sdmc *host);
void mmc_set_rx_phase(void *priv, u32 phase);
void mmc_set_rx_delay(void *priv, u32 delay);
int mmc_rpmb_get_counter(struct aic_sdmc *host, unsigned long *pcounter);
int mmc_rpmb_set_key(struct aic_sdmc *host, void *key);

4
bsp/artinchip/include/drv_bare/mtd.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
* Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -33,6 +33,7 @@ struct nftl_mtd {
enum part_attr {
PART_ATTR_MTD = 0,
PART_ATTR_NFTL,
PART_ATTR_LEVELX,
};
#define MAX_MTD_NAME 64
@@ -97,6 +98,7 @@ int mtd_map_oob_user_region(struct mtd_dev *mtd, u8 *oobbuf, u8 *buf, int start,
struct nftl_mtd *build_nftl_list(char *nftlvols);
void free_nftl_list(struct nftl_mtd *nftl);
u8 partition_nftl_is_exist(char *mtd_name, struct nftl_mtd *nftl_list);
u8 partition_levelx_is_exist(char *mtd_name, char *levelx_partstr);
#ifdef __cplusplus
}

7
bsp/artinchip/include/hal/aic_hal_clk.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022, Artinchip Technology Co., Ltd
* Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -10,8 +10,11 @@
#ifdef __cplusplus
extern "C" {
#endif
#ifndef AIC_CMU_FRAMEWORK_V2
#include "aic_hal_clk_cmu.h"
#else
#include "aic_hal_clk_cmu_v2.h"
#endif
#include "aic_clk_id.h"
int hal_clk_enable(uint32_t clk_id);

298
bsp/artinchip/include/hal/aic_hal_clk_cmu_v2.h Normal file
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@@ -0,0 +1,298 @@
/*
* Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __AIC_HAL_CMU_CLK_V2_H__
#define __AIC_HAL_CMU_CLK_V2_H__
#ifdef __cplusplus
extern "C" {
#endif
struct aic_clk_comm_cfg {
struct aic_clk_ops *ops;
const char *name;
bool enable;
};
struct aic_clk_fixed_rate_cfg {
struct aic_clk_comm_cfg comm;
unsigned long rate;
u8 id;
u8 type;
u8 parent_id;
u8 flag;
};
/* Define types of pll */
enum aic_pll_type {
AIC_PLL_INT, /* integer pll */
AIC_PLL_FRA, /* fractional pll */
AIC_PLL_SDM, /* spread spectrum pll */
};
struct aic_clk_pll_cfg {
struct aic_clk_comm_cfg comm;
u32 offset_gen;
u32 offset_fra;
u32 offset_sdm;
u8 id;
u8 type;
u8 parent_id;
u8 flag;
};
enum aic_fixed_parent_type {
AIC_FPCLK_NORMAL,
AIC_FPCLK_FIXED_FACTOR,
};
/*
* This structure is designed for compatible with multiple dividers.
* For example, CPU has three parent clocks: CLK_24M, PLL_INT0, PLL_INT1,
* with corresponding frequency division coefficients of 1, (DIV + 1), 2, respectively.
* If shift < 0, wd.div represents the frequency division.
* If shift >= 0, wd.width represents the width of frequency division in register.
*/
struct table_div {
s16 shift;
union {
u16 width;
u16 div;
} wd;
};
struct aic_clk_fixed_parent_cfg {
struct aic_clk_comm_cfg comm;
u32 offset_reg;
s8 *table_gates;
u8 num_gates;
struct table_div *table_div;
u8 num_div;
u8 id;
u8 parent_id;
u8 flag;
};
struct aic_clk_multi_parent_cfg {
struct aic_clk_comm_cfg comm;
u32 offset_reg;
s8 *table_gates;
u8 num_gates;
u8 mux_bit;
u8 mux_mask;
struct table_div *table_div;
u8 num_div;
u8 id;
u8 num_parents;
const u8 *parent_ids;
};
struct aic_clk_auth_cfg {
struct aic_clk_comm_cfg comm;
u32 offset_reg;
u32 offset_wr_auth_reg;
u32 key_code;
u8 key_bit;
u16 key_mask;
u8 wr_auth_bit;
s8 *table_gates;
u8 num_gates;
u8 mux_bit;
u8 mux_mask;
struct table_div *table_div;
u8 num_div;
u8 id;
u8 num_parents;
const u8 *parent_ids;
};
struct aic_clk {
const struct aic_clk_comm_cfg *comm_cfg;
unsigned long rate;
u8 count;
u8 parent_id;
u8 flag;
};
struct aic_pll_vco {
unsigned long vco_min;
unsigned long vco_max;
char *name;
};
struct aic_clk_ops {
int (*enable)(struct aic_clk_comm_cfg *comm_cfg);
void (*disable)(struct aic_clk_comm_cfg *comm_cfg);
int (*is_enabled)(struct aic_clk_comm_cfg *comm_cfg);
int (*set_rate)(struct aic_clk_comm_cfg *comm_cfg, unsigned long rate,
unsigned long parent_rate);
unsigned long (*recalc_rate)(struct aic_clk_comm_cfg *comm_cfg,
unsigned long parent_rate);
long (*round_rate)(struct aic_clk_comm_cfg *comm_cfg, unsigned long rate,
unsigned long *parent_rate);
int (*set_parent)(struct aic_clk_comm_cfg *comm_cfg, unsigned int index);
unsigned int (*get_parent)(struct aic_clk_comm_cfg *comm_cfg);
int (*enable_clk_deassert_rst)(struct aic_clk_comm_cfg *comm_cfg);
void (*disable_clk_assert_rst)(struct aic_clk_comm_cfg *comm_cfg);
};
#define cmu_reg(x) (volatile void *)(x + CMU_BASE)
#ifdef AIC_CMU_CROSS_ZONE_CTL
#define zc_cmu_reg(x) (volatile void *)(x + CMU_BASE1)
#endif
#define PARENT(x) (x)
#define AIC_CLK_CFG_ADDR(_id) [_id] = &(aic_clk_cfg_##_id.comm)
#define AIC_CLK_CFG(_id) AIC_CLK_CFG_ADDR(_id)
#define DUMMY_CFG(_id) [_id] = NULL
/* For clocks fixed rate */
#define FRCLK_DEF(_id, _name, _rate) \
static const struct aic_clk_fixed_rate_cfg aic_clk_cfg_##_id = { \
.id = _id, \
.parent_id = 0, \
.rate = _rate, \
.comm.enable = 1, \
.comm.ops = &aic_clk_fixed_rate_ops, \
.comm.name = _name, \
}
#define FRCLK(_id, _name, _rate) FRCLK_DEF(_id, _name, _rate)
/* For PLL clock */
#define PLL_DEF(_id, _name, _type, _parent_id, _gen, _fra, _sdm, _flag) \
static const struct aic_clk_pll_cfg aic_clk_cfg_##_id = { \
.id = _id, \
.parent_id = _parent_id, \
.type = _type, \
.offset_gen = _gen, \
.offset_fra = _fra, \
.offset_sdm = _sdm, \
.flag = _flag, \
.comm.ops = &aic_clk_pll_ops, \
.comm.name = _name, \
}
#define PLL_INT(_id, _name, _parent_id, _parent_name, _gen, _flag) \
PLL_DEF(_id, _name, AIC_PLL_INT, _parent_id, _gen, 0, 0, _flag)
#define PLL_FRA(_id, _name, _parent_id, _parent_name, _gen, _fra, _sdm, _flag) \
PLL_DEF(_id, _name, AIC_PLL_FRA, _parent_id, _gen, _fra, _sdm, _flag)
#define PLL_SDM(_id, _name, _parent_id, _parent_name, _gen, _fra, _sdm, _flag) \
PLL_DEF(_id, _name, AIC_PLL_SDM, _parent_id, _gen, _fra, _sdm, _flag)
/* For clocks fixed parent */
#define FPCLK(_id, _name, _parent_id, _parent_name, _reg, _table_gates, \
_table_div, _flag) \
static const struct aic_clk_fixed_parent_cfg aic_clk_cfg_##_id = { \
.id = _id, \
.parent_id = _parent_id, \
.offset_reg = _reg, \
.table_gates = _table_gates,\
.num_gates = ARRAY_SIZE(_table_gates),\
.table_div = _table_div,\
.num_div = ARRAY_SIZE(_table_div),\
.flag = _flag, \
.comm.ops = &aic_clk_fixed_parent_ops, \
.comm.name = _name, \
}
/* For clocks that has multi-parent source */
#define MPCLK(_id, _name, _parent, _reg, _table_gates, _mux, _muxw, _table_div) \
static const struct aic_clk_multi_parent_cfg aic_clk_cfg_##_id = { \
.id = _id, \
.parent_ids = _parent, \
.num_parents = ARRAY_SIZE(_parent), \
.offset_reg = _reg, \
.table_gates = _table_gates,\
.num_gates = ARRAY_SIZE(_table_gates),\
.mux_bit = _mux, \
.mux_mask = ((1 << _muxw) - 1), \
.table_div = _table_div,\
.num_div = ARRAY_SIZE(_table_div),\
.comm.ops = &aic_clk_multi_parent_ops, \
.comm.name = _name, \
}
#define AUTHCLK(_id, _name, _parent, _reg, _wr_auth_reg, _key_code, _key, _keyw, _wr_auth_bit, _table_gates, _mux, _muxw, _table_div) \
static const struct aic_clk_auth_cfg aic_clk_cfg_##_id = { \
.id = _id, \
.parent_ids = _parent, \
.num_parents = ARRAY_SIZE(_parent), \
.offset_reg = _reg, \
.offset_wr_auth_reg = _wr_auth_reg,\
.key_code = _key_code, \
.key_bit = _key, \
.key_mask = ((1 << _keyw) - 1), \
.wr_auth_bit = _wr_auth_bit,\
.table_gates = _table_gates,\
.num_gates = ARRAY_SIZE(_table_gates),\
.mux_bit = _mux, \
.mux_mask = ((1 << _muxw) - 1), \
.table_div = _table_div,\
.num_div = ARRAY_SIZE(_table_div),\
.comm.ops = &aic_clk_auth_ops, \
.comm.name = _name, \
}
/* For display clock */
#define DISPCLK_DEF(_id, _name, _parent_id, _parent_name, _reg, _divn, \
_nwidth, _divm, _mwidth, _divl, _lwidth, _pix_divsel, \
_pix_divsel_width) \
static const struct aic_clk_disp_cfg aic_clk_cfg_##_id = { \
.id = _id, \
.parent_id = _parent_id, \
.offset_reg = _reg, \
.divn_bit = _divn, \
.divn_mask = ((1 << _nwidth) - 1), \
.divm_bit = _divm, \
.divm_mask = ((1 << _mwidth) - 1), \
.divl_bit = _divl, \
.divl_mask = ((1 << _lwidth) - 1), \
.pix_divsel_bit = _pix_divsel, \
.pix_divsel_mask = ((1 << _pix_divsel_width) - 1), \
.comm.ops = &aic_clk_disp_ops, \
.comm.name = _name, \
}
#define DISPCLK(_id, _name, _parent_id, _parent_name, _reg, _divn, _nwidth, \
_divm, _mwidth, _divl, _lwidth, _pix_divsel, \
_pix_divsel_width) \
DISPCLK_DEF(_id, _name, _parent_id, _parent_name, _reg, _divn, _nwidth, \
_divm, _mwidth, _divl, _lwidth, _pix_divsel, \
_pix_divsel_width)
/*
* flags used across common struct clk. these flags should only affect the
* top-level framework. custom flags for dealing with hardware specifics
* belong in struct clk_foo
*
* Please update clk_flags[] in drivers/clk/clk.c when making changes here!
*/
#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
#define CLK_CROSS_ZONE_CTL BIT(4) /* Control clk of other zone */
#define CLK_NO_CHANGE BIT(5) /* don't change rate and parent */
#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
#define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
#define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
#define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
/* parents need enable during gate/ungate, set rate and re-parent */
#define CLK_OPS_PARENT_ENABLE BIT(12)
/* duty cycle call may be forwarded to the parent clock */
#define CLK_DUTY_CYCLE_PARENT BIT(13)
#define CLK_DONT_HOLD_STATE BIT(14) /* Don't hold state */
extern const unsigned long fpga_board_rate[];
#ifdef __cplusplus
}
#endif
#endif /* __AIC_HAL_CMU_CLK_V2_H__ */

5
bsp/artinchip/include/hal/aic_hal_dsi.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2023, Artinchip Technology Co., Ltd
* Copyright (c) 2023-2025, Artinchip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -18,6 +18,7 @@ enum dsi_mode {
DSI_MOD_CMD_MODE = BIT(3),
DSI_CLOCK_NON_CONTINUOUS = BIT(4),
DSI_MOD_NO_EOT_PACKET = BIT(5),
};
enum dsi_format {
@@ -319,7 +320,7 @@ void dsi_set_lane_polrs(void *base, u32 ln_polrs);
void dsi_set_data_clk_polrs(void *base, u32 dc_inv);
void dsi_set_clk_div(void *base, ulong mclk, ulong lp_rate);
void dsi_pkg_init(void *base);
void dsi_pkg_init(void *base, enum dsi_mode mode);
void dsi_phy_init(void *base, ulong mclk, u32 lane, enum dsi_mode mode);
void dsi_hs_clk(void *base, u32 enable);
void dsi_set_vm(void *base, enum dsi_mode mode, enum dsi_format format,

4
bsp/artinchip/include/hal/hal_cap.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
* Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -11,7 +11,7 @@
#include "aic_common.h"
#ifdef CONFIG_FPGA_BOARD_ARTINCHIP
#ifdef FPGA_BOARD_ARTINCHIP
#define PWMCS_CLK_RATE 24000000 /* 24 MHz */
#else
#define PWMCS_CLK_RATE 200000000 /* 200 MHz */

2
bsp/artinchip/include/hal/hal_epwm.h
View File

@@ -13,7 +13,7 @@
#define AIC_EPWM_NAME "aic-epwm"
#ifdef CONFIG_FPGA_BOARD_ARTINCHIP
#ifdef FPGA_BOARD_ARTINCHIP
#define EPWM_CLK_RATE 24000000 /* 24 MHz */
#else
#define EPWM_CLK_RATE 200000000 /* 200 MHz */

18
bsp/artinchip/include/hal/hal_gpai.h
View File

@@ -27,12 +27,6 @@ enum aic_gpai_obtain_data_mode {
AIC_GPAI_OBTAIN_DATA_BY_DO = 4
};
#if defined(AIC_GPAI_DRV_V21)
enum adc_acc_sel_type_t {
AIC_GPAI_ADC_12BIT = 0,
AIC_GPAI_ADC_14BIT = 1
};
#endif
typedef void (*dma_callback)(void *dma_param);
typedef void (*irq_callback)(void *cb_param);
@@ -108,16 +102,4 @@ void aich_gpai_status_show(struct aic_gpai_ch *chan);
s32 hal_gpai_init(void);
s32 hal_gpai_deinit(void);
void hal_gpai_clk_get(struct aic_gpai_ch *chan);
#ifdef AIC_GPAI_DRV_DMA
void hal_gpai_config_dma(struct aic_gpai_ch *chan);
void hal_gpai_start_dma(struct aic_gpai_ch *chan);
void hal_gpai_stop_dma(struct aic_gpai_ch *chan);
#endif
#if defined(AIC_GPAI_DRV_V21)
void aich_gpai_adc_sel_enable(int adc_type);
#endif
#ifdef AIC_GPAI_DRV_DO
int hal_gpai_do_set_ch(u8 do_ch, u8 ad_ch);
void hal_gpai_do_enable(u8 do_ch);
#endif
#endif // end of _ARTINCHIP_HAL_GPAI_H_

4
bsp/artinchip/include/hal/hal_pwm.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
* Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -13,7 +13,7 @@
#define AIC_PWM_NAME "aic-pwm"
#ifdef CONFIG_FPGA_BOARD_ARTINCHIP
#ifdef FPGA_BOARD_ARTINCHIP
#define PWM_CLK_RATE 24000000 /* 24 MHz */
#else
#define PWM_CLK_RATE 48000000 /* 48 MHz */

2
bsp/artinchip/include/hal/hal_qep.h
View File

@@ -11,7 +11,7 @@
#include "aic_common.h"
#ifdef CONFIG_FPGA_BOARD_ARTINCHIP
#ifdef FPGA_BOARD_ARTINCHIP
#define QEP_CLK_RATE 24000000 /* 24 MHz */
#else
#define QEP_CLK_RATE 200000000 /* 200 MHz */

9
bsp/artinchip/include/hal/hal_qspi.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
* Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -60,6 +60,8 @@ struct qspi_master_config {
u8 cpha;
u32 rx_dlymode;
u32 tx_dlymode;
u32 max_hz;
bool slave_en;
};
struct qspi_master_dma_config {
@@ -81,6 +83,10 @@ struct qspi_slave_config {
u8 cs_polarity;
u8 cpol;
u8 cpha;
u32 rx_dlymode;
u32 tx_dlymode;
u32 max_hz;
bool slave_en;
};
struct qspi_slave_idma_config {
@@ -146,6 +152,7 @@ struct qspi_slave_state {
u32 async_rx_count; /* Used in Async mode */
u32 work_mode;
u32 done_mask;
bool bit_mode;
};
struct qspi_bm_transfer {

4
bsp/artinchip/include/hal/hal_sdmc.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
* Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -237,6 +237,7 @@ void hal_sdmc_get_rsp(struct aic_sdmc_host *host, u32 *buf, u32 all);
void aic_sdmc_set_ext_clk_mux(struct aic_sdmc_host *host, u32 mux);
void hal_sdmc_set_phase(struct aic_sdmc_host *host, u32 drv, u32 smp);
void hal_sdmc_set_delay(struct aic_sdmc_host *host, u32 drv, u32 smp);
void hal_sdmc_set_buswidth(struct aic_sdmc_host *host, u32 buswidth);
void hal_sdmc_set_ddrmode(struct aic_sdmc_host *host, u32 ddr);
void hal_sdmc_clk_disable(struct aic_sdmc_host *host);
@@ -245,6 +246,7 @@ void hal_sdmc_sdio_irq_enable(struct aic_sdmc_host *host, u32 en);
void hal_sdmc_set_div(struct aic_sdmc_host *host, u32 div);
void hal_sdmc_fifo_init(struct aic_sdmc_host *host, u32 *thd);
void hal_sdmc_soft_reset(struct aic_sdmc_host *host);
int hal_sdmc_reset(struct aic_sdmc_host *host, u32 value);
void hal_sdmc_init(struct aic_sdmc_host *host);

4
bsp/artinchip/include/hal/hal_spienc.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2023, ArtInChip Technology Co., Ltd
* Copyright (c) 2023-2025, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -29,6 +29,8 @@ int hal_spienc_init(void);
void hal_spienc_set_cfg(u32 spi_bus, u32 addr, u32 cpos, u32 clen);
void hal_spienc_set_bypass(int status);
void hal_spienc_select_tweak(int select);
void hal_spienc_xip_enable(void);
void hal_spienc_xip_disable(void);
void hal_spienc_start(void);
void hal_spienc_stop(void);
int hal_spienc_check_empty(void);

12
bsp/artinchip/include/hal/spienc.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2023, ArtInChip Technology Co., Ltd
* Copyright (c) 2023-2025, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -31,6 +31,16 @@ static inline void spienc_select_tweak(int select)
hal_spienc_select_tweak(select);
}
static inline void spienc_xip_enable(void)
{
hal_spienc_xip_enable();
}
static inline void spienc_xip_disable(void)
{
hal_spienc_xip_disable();
}
static inline void spienc_start(void)
{
hal_spienc_start();