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v1.2.1
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刘可亮
298
bsp/artinchip/include/hal/aic_hal_clk_cmu_v2.h
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298
bsp/artinchip/include/hal/aic_hal_clk_cmu_v2.h
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/*
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* Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __AIC_HAL_CMU_CLK_V2_H__
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#define __AIC_HAL_CMU_CLK_V2_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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struct aic_clk_comm_cfg {
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struct aic_clk_ops *ops;
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const char *name;
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bool enable;
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};
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struct aic_clk_fixed_rate_cfg {
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struct aic_clk_comm_cfg comm;
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unsigned long rate;
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u8 id;
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u8 type;
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u8 parent_id;
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u8 flag;
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};
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/* Define types of pll */
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enum aic_pll_type {
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AIC_PLL_INT, /* integer pll */
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AIC_PLL_FRA, /* fractional pll */
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AIC_PLL_SDM, /* spread spectrum pll */
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};
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struct aic_clk_pll_cfg {
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struct aic_clk_comm_cfg comm;
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u32 offset_gen;
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u32 offset_fra;
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u32 offset_sdm;
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u8 id;
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u8 type;
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u8 parent_id;
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u8 flag;
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};
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enum aic_fixed_parent_type {
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AIC_FPCLK_NORMAL,
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AIC_FPCLK_FIXED_FACTOR,
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};
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/*
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* This structure is designed for compatible with multiple dividers.
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* For example, CPU has three parent clocks: CLK_24M, PLL_INT0, PLL_INT1,
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* with corresponding frequency division coefficients of 1, (DIV + 1), 2, respectively.
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* If shift < 0, wd.div represents the frequency division.
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* If shift >= 0, wd.width represents the width of frequency division in register.
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*/
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struct table_div {
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s16 shift;
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union {
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u16 width;
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u16 div;
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} wd;
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};
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struct aic_clk_fixed_parent_cfg {
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struct aic_clk_comm_cfg comm;
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u32 offset_reg;
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s8 *table_gates;
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u8 num_gates;
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struct table_div *table_div;
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u8 num_div;
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u8 id;
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u8 parent_id;
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u8 flag;
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};
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struct aic_clk_multi_parent_cfg {
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struct aic_clk_comm_cfg comm;
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u32 offset_reg;
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s8 *table_gates;
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u8 num_gates;
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u8 mux_bit;
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u8 mux_mask;
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struct table_div *table_div;
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u8 num_div;
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u8 id;
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u8 num_parents;
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const u8 *parent_ids;
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};
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struct aic_clk_auth_cfg {
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struct aic_clk_comm_cfg comm;
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u32 offset_reg;
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u32 offset_wr_auth_reg;
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u32 key_code;
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u8 key_bit;
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u16 key_mask;
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u8 wr_auth_bit;
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s8 *table_gates;
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u8 num_gates;
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u8 mux_bit;
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u8 mux_mask;
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struct table_div *table_div;
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u8 num_div;
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u8 id;
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u8 num_parents;
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const u8 *parent_ids;
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};
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struct aic_clk {
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const struct aic_clk_comm_cfg *comm_cfg;
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unsigned long rate;
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u8 count;
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u8 parent_id;
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u8 flag;
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};
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struct aic_pll_vco {
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unsigned long vco_min;
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unsigned long vco_max;
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char *name;
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};
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struct aic_clk_ops {
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int (*enable)(struct aic_clk_comm_cfg *comm_cfg);
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void (*disable)(struct aic_clk_comm_cfg *comm_cfg);
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int (*is_enabled)(struct aic_clk_comm_cfg *comm_cfg);
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int (*set_rate)(struct aic_clk_comm_cfg *comm_cfg, unsigned long rate,
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unsigned long parent_rate);
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unsigned long (*recalc_rate)(struct aic_clk_comm_cfg *comm_cfg,
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unsigned long parent_rate);
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long (*round_rate)(struct aic_clk_comm_cfg *comm_cfg, unsigned long rate,
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unsigned long *parent_rate);
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int (*set_parent)(struct aic_clk_comm_cfg *comm_cfg, unsigned int index);
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unsigned int (*get_parent)(struct aic_clk_comm_cfg *comm_cfg);
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int (*enable_clk_deassert_rst)(struct aic_clk_comm_cfg *comm_cfg);
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void (*disable_clk_assert_rst)(struct aic_clk_comm_cfg *comm_cfg);
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};
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#define cmu_reg(x) (volatile void *)(x + CMU_BASE)
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#ifdef AIC_CMU_CROSS_ZONE_CTL
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#define zc_cmu_reg(x) (volatile void *)(x + CMU_BASE1)
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#endif
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#define PARENT(x) (x)
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#define AIC_CLK_CFG_ADDR(_id) [_id] = &(aic_clk_cfg_##_id.comm)
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#define AIC_CLK_CFG(_id) AIC_CLK_CFG_ADDR(_id)
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#define DUMMY_CFG(_id) [_id] = NULL
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/* For clocks fixed rate */
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#define FRCLK_DEF(_id, _name, _rate) \
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static const struct aic_clk_fixed_rate_cfg aic_clk_cfg_##_id = { \
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.id = _id, \
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.parent_id = 0, \
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.rate = _rate, \
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.comm.enable = 1, \
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.comm.ops = &aic_clk_fixed_rate_ops, \
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.comm.name = _name, \
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}
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#define FRCLK(_id, _name, _rate) FRCLK_DEF(_id, _name, _rate)
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/* For PLL clock */
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#define PLL_DEF(_id, _name, _type, _parent_id, _gen, _fra, _sdm, _flag) \
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static const struct aic_clk_pll_cfg aic_clk_cfg_##_id = { \
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.id = _id, \
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.parent_id = _parent_id, \
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.type = _type, \
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.offset_gen = _gen, \
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.offset_fra = _fra, \
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.offset_sdm = _sdm, \
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.flag = _flag, \
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.comm.ops = &aic_clk_pll_ops, \
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.comm.name = _name, \
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}
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#define PLL_INT(_id, _name, _parent_id, _parent_name, _gen, _flag) \
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PLL_DEF(_id, _name, AIC_PLL_INT, _parent_id, _gen, 0, 0, _flag)
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#define PLL_FRA(_id, _name, _parent_id, _parent_name, _gen, _fra, _sdm, _flag) \
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PLL_DEF(_id, _name, AIC_PLL_FRA, _parent_id, _gen, _fra, _sdm, _flag)
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#define PLL_SDM(_id, _name, _parent_id, _parent_name, _gen, _fra, _sdm, _flag) \
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PLL_DEF(_id, _name, AIC_PLL_SDM, _parent_id, _gen, _fra, _sdm, _flag)
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/* For clocks fixed parent */
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#define FPCLK(_id, _name, _parent_id, _parent_name, _reg, _table_gates, \
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_table_div, _flag) \
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static const struct aic_clk_fixed_parent_cfg aic_clk_cfg_##_id = { \
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.id = _id, \
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.parent_id = _parent_id, \
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.offset_reg = _reg, \
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.table_gates = _table_gates,\
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.num_gates = ARRAY_SIZE(_table_gates),\
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.table_div = _table_div,\
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.num_div = ARRAY_SIZE(_table_div),\
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.flag = _flag, \
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.comm.ops = &aic_clk_fixed_parent_ops, \
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.comm.name = _name, \
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}
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/* For clocks that has multi-parent source */
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#define MPCLK(_id, _name, _parent, _reg, _table_gates, _mux, _muxw, _table_div) \
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static const struct aic_clk_multi_parent_cfg aic_clk_cfg_##_id = { \
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.id = _id, \
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.parent_ids = _parent, \
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.num_parents = ARRAY_SIZE(_parent), \
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.offset_reg = _reg, \
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.table_gates = _table_gates,\
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.num_gates = ARRAY_SIZE(_table_gates),\
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.mux_bit = _mux, \
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.mux_mask = ((1 << _muxw) - 1), \
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.table_div = _table_div,\
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.num_div = ARRAY_SIZE(_table_div),\
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.comm.ops = &aic_clk_multi_parent_ops, \
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.comm.name = _name, \
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}
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#define AUTHCLK(_id, _name, _parent, _reg, _wr_auth_reg, _key_code, _key, _keyw, _wr_auth_bit, _table_gates, _mux, _muxw, _table_div) \
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static const struct aic_clk_auth_cfg aic_clk_cfg_##_id = { \
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.id = _id, \
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.parent_ids = _parent, \
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.num_parents = ARRAY_SIZE(_parent), \
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.offset_reg = _reg, \
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.offset_wr_auth_reg = _wr_auth_reg,\
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.key_code = _key_code, \
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.key_bit = _key, \
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.key_mask = ((1 << _keyw) - 1), \
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.wr_auth_bit = _wr_auth_bit,\
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.table_gates = _table_gates,\
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.num_gates = ARRAY_SIZE(_table_gates),\
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.mux_bit = _mux, \
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.mux_mask = ((1 << _muxw) - 1), \
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.table_div = _table_div,\
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.num_div = ARRAY_SIZE(_table_div),\
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.comm.ops = &aic_clk_auth_ops, \
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.comm.name = _name, \
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}
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/* For display clock */
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#define DISPCLK_DEF(_id, _name, _parent_id, _parent_name, _reg, _divn, \
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_nwidth, _divm, _mwidth, _divl, _lwidth, _pix_divsel, \
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_pix_divsel_width) \
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static const struct aic_clk_disp_cfg aic_clk_cfg_##_id = { \
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.id = _id, \
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.parent_id = _parent_id, \
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.offset_reg = _reg, \
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.divn_bit = _divn, \
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.divn_mask = ((1 << _nwidth) - 1), \
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.divm_bit = _divm, \
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.divm_mask = ((1 << _mwidth) - 1), \
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.divl_bit = _divl, \
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.divl_mask = ((1 << _lwidth) - 1), \
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.pix_divsel_bit = _pix_divsel, \
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.pix_divsel_mask = ((1 << _pix_divsel_width) - 1), \
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.comm.ops = &aic_clk_disp_ops, \
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.comm.name = _name, \
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}
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#define DISPCLK(_id, _name, _parent_id, _parent_name, _reg, _divn, _nwidth, \
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_divm, _mwidth, _divl, _lwidth, _pix_divsel, \
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_pix_divsel_width) \
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DISPCLK_DEF(_id, _name, _parent_id, _parent_name, _reg, _divn, _nwidth, \
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_divm, _mwidth, _divl, _lwidth, _pix_divsel, \
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_pix_divsel_width)
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/*
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* flags used across common struct clk. these flags should only affect the
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* top-level framework. custom flags for dealing with hardware specifics
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* belong in struct clk_foo
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*
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* Please update clk_flags[] in drivers/clk/clk.c when making changes here!
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*/
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#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
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#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
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#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
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#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
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#define CLK_CROSS_ZONE_CTL BIT(4) /* Control clk of other zone */
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#define CLK_NO_CHANGE BIT(5) /* don't change rate and parent */
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#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
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#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
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#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
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#define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
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#define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
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#define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
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/* parents need enable during gate/ungate, set rate and re-parent */
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#define CLK_OPS_PARENT_ENABLE BIT(12)
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/* duty cycle call may be forwarded to the parent clock */
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#define CLK_DUTY_CYCLE_PARENT BIT(13)
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#define CLK_DONT_HOLD_STATE BIT(14) /* Don't hold state */
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extern const unsigned long fpga_board_rate[];
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#ifdef __cplusplus
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}
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#endif
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#endif /* __AIC_HAL_CMU_CLK_V2_H__ */
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