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v1.2.2

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This commit is contained in:
刘可亮
2025-10-21 13:59:50 +08:00
parent 33c375efac
commit 3e10f578d3
7070 changed files with 998841 additions and 1402535 deletions
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32
packages/artinchip/lvgl-ui/aic_widgets/aic_spi/SConscript Normal file
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from building import *
import os
cwd = GetCurrentDir()
group = []
src = []
CPPPATH = [cwd]
if GetDepend('AIC_LVGL_SPI_WIDGET'):
src += Glob('lv_aic_spi.c')
if GetDepend('LV_SPI_ST77916'):
src += Glob('lv_st77916.c')
if GetDepend('LV_SPI_ST77912'):
src += Glob('lv_st77912.c')
if GetDepend('LV_SPI_ST7789'):
src += Glob('lv_st7789.c')
if GetDepend('LV_SPI_GC9D01N'):
src += Glob('lv_gc9d01n.c')
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
group = group + SConscript(os.path.join(d, 'SConscript'))
group = group + DefineGroup('LVGL-port', src, depend = ['LPKG_USING_LVGL'], CPPPATH = CPPPATH)
Return('group')

452
packages/artinchip/lvgl-ui/aic_widgets/aic_spi/lv_aic_spi.c Normal file
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/*
* Copyright (C) 2025, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: Huahui <huahui.mai@artinchip.com>
*/
#include "lv_aic_spi.h"
#include "aic_iopoll.h"
#define SPI_DEV_NAME "spidev"
#define SPI_BUF_NAME "spi2"
#define SPI_MODE (RT_SPI_MODE_0 | RT_SPI_MSB)
#define SPI_MAX_HZ 70000000
#define RS_PIN "PB.11"
#define BL_PIN "PC.0"
#define BL_LOW_ACTIVE 1
#if BL_LOW_ACTIVE
#define BL_ACTIVE_LEVEL PIN_LOW
#else
#define BL_ACTIVE_LEVEL PIN_HIGH
#endif
#define LV_SPI_USE_TE 0
#define TE_PIN "PB.10"
#define TE_TIMEOUT_MS 100
#define ALIGN_8B(x) (((x) + (7)) & ~(7))
static struct lv_spi_dev *g_spi_dev = NULL;
static void lv_disp_data_blt(struct lv_spi_dev *spi_dev);
void lv_spi_write_buffer(struct lv_spi_dev *spi_dev, unsigned int cmd, unsigned int len, const u8 *data)
{
struct rt_spi_device *spi = (struct rt_spi_device *)spi_dev->dev;
int ret;
rt_spi_take_bus(spi);
rt_pin_write(spi_dev->rs_pin, PIN_LOW);
rt_spi_transfer(spi, (u8[]){ cmd }, NULL, 1);
rt_pin_write(spi_dev->rs_pin, PIN_HIGH);
if (len != 0) {
ret = rt_spi_transfer(spi, (void *)data, NULL, len);
if (ret != len)
LV_LOG_ERROR("Send spi data failed. ret 0x%x\n", (int)ret);
}
rt_spi_release_bus(spi);
}
void lv_spi_flush(u8 *data, unsigned int len)
{
struct lv_spi_dev *spi_dev = g_spi_dev;
struct rt_spi_device *spi = (struct rt_spi_device *)spi_dev->dev;
spi_dev->data = data;
spi_dev->len = len;
/*
* The first frame is sent throught synchronous interface.
* We need to wait completion in the second frame.
*/
if (spi_dev->frame_count == 2)
rt_spi_wait_completion(spi);
else
spi_dev->frame_count++;
aicos_sem_give(spi_dev->display_sem);
}
static int lv_spi_init(struct lv_spi_dev *spi_dev)
{
struct rt_spi_configuration spi_cfg;
struct rt_spi_device *spi_device = NULL;
struct rt_device *dev = NULL;
rt_err_t result = RT_EOK;
spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
if (spi_device == RT_NULL) {
LV_LOG_ERROR("rt malloc spi device failed.\n");
return -RT_ERROR;
}
result = rt_spi_bus_attach_device(spi_device, SPI_DEV_NAME, spi_dev->bus_name, NULL);
if (result != RT_EOK && spi_device != NULL) {
LV_LOG_ERROR("rt spi bus attach device failed.\n");
result = -RT_ERROR;
goto err;
}
spi_device = (struct rt_spi_device *)rt_device_find(SPI_DEV_NAME);
if (!spi_device) {
LV_LOG_ERROR("Failed to get device in %s\n", SPI_DEV_NAME);
result = -RT_ERROR;
goto err;
}
dev = (struct rt_device *)spi_device;
if (dev->type != RT_Device_Class_SPIDevice) {
spi_device = NULL;
LV_LOG_ERROR("%s is not SPI device.\n", SPI_DEV_NAME);
result = -RT_ERROR;
goto err;
}
rt_memset(&spi_cfg, 0, sizeof(spi_cfg));
spi_cfg.mode = spi_dev->mode;
spi_cfg.max_hz = spi_dev->max_hz;
result = rt_spi_configure(spi_device, &spi_cfg);
if (result < 0) {
LV_LOG_ERROR("qspi configure failure.\n");
result = -RT_ERROR;
goto err;
}
spi_dev->dev = spi_device;
return result;
err:
if (spi_dev)
rt_free(spi_dev);
spi_dev = NULL;
return result;
}
static void lv_disp_data_blt(struct lv_spi_dev *spi_dev)
{
struct ge_bitblt blt = { 0 };
struct mpp_ge *ge2d_dev = spi_dev->ge2d_dev;
blt.src_buf.buf_type = MPP_PHY_ADDR;
blt.src_buf.phy_addr[0] = (uint32_t)(ulong)spi_dev->data;
blt.src_buf.stride[0] = spi_dev->info.stride;
blt.src_buf.size.width = spi_dev->info.width;
blt.src_buf.size.height = spi_dev->info.height;
blt.src_buf.format = spi_dev->info.format;
blt.dst_buf.buf_type = MPP_PHY_ADDR;
blt.dst_buf.phy_addr[0] = (uint32_t)(ulong)spi_dev->tx_buf;
blt.dst_buf.stride[0] = ALIGN_8B(spi_dev->info.width * 2); // rgb565 bpp = 2;
blt.dst_buf.format = MPP_FMT_RGB_565;
blt.dst_buf.size.width = spi_dev->info.width;
blt.dst_buf.size.height = spi_dev->info.height;
blt.ctrl.dither_en = 1;
int ret = mpp_ge_bitblt(ge2d_dev, &blt);
if (ret < 0) {
LV_LOG_ERROR("mpp ge bitblt fail\n");
return;
}
ret = mpp_ge_emit(ge2d_dev);
if (ret < 0) {
LV_LOG_ERROR("mpp ge emit fail\n");
return;
}
ret = mpp_ge_sync(ge2d_dev);
if (ret < 0) {
LV_LOG_ERROR("mpp ge sync fail\n");
return;
}
lv_draw_sw_rgb565_swap(spi_dev->tx_buf, spi_dev->info.width * spi_dev->info.height);
aicos_dcache_clean_invalid_range((ulong *)spi_dev->tx_buf, (ulong)ALIGN_UP(spi_dev->tx_len, CACHE_LINE_SIZE));
}
#if LV_SPI_USE_TE
static void te_input_irq_handler(void *args)
{
struct lv_spi_dev *spi_dev = args;
aicos_wqueue_wakeup(spi_dev->te_queue);
}
#endif
static int te_input_pin_cfg(struct lv_spi_dev *spi_dev)
{
#if LV_SPI_USE_TE
u32 pin = 0;
pin = rt_pin_get(TE_PIN);
if (pin < 0) {
LV_LOG_ERROR("failed to get TE pin\n");
return pin;
}
rt_pin_mode(pin, PIN_MODE_INPUT_PULLUP);
rt_pin_attach_irq(pin, PIN_IRQ_MODE_RISING_FALLING,
te_input_irq_handler, spi_dev);
rt_pin_irq_enable(pin, PIN_IRQ_ENABLE);
#endif
return 0;
}
static inline void *lv_spi_create_te_queue(void)
{
#if LV_SPI_USE_TE
return aicos_wqueue_create();
#else
return NULL;
#endif
}
static void disp_thread(void *arg)
{
struct lv_spi_dev *spi_dev = arg;
struct rt_spi_device *spi = (struct rt_spi_device *)spi_dev->dev;
static bool bl_en = false;
while (1) {
aicos_sem_take(spi_dev->display_sem, AICOS_WAIT_FOREVER);
lv_disp_data_blt(spi_dev);
if (bl_en && spi_dev->te_queue) {
int ret = aicos_wqueue_wait(spi_dev->te_queue, TE_TIMEOUT_MS);
if (ret < 0)
LV_LOG_ERROR("SPI wait TE irq timeout, ret: %d\n", ret);
}
rt_spi_nonblock_set(spi, 0);
rt_pin_write(spi_dev->rs_pin, PIN_LOW);
lv_spi_write_seq(spi_dev, 0x2c);
if (bl_en)
/* flush first pixel frame in synchronous mode */
rt_spi_nonblock_set(spi, 1);
rt_pin_write(spi_dev->rs_pin, PIN_HIGH);
rt_spi_transfer(spi, spi_dev->tx_buf, NULL, spi_dev->tx_len);
if (!bl_en) {
/*
* The first frame is sent throught the spi synchronous interface, and after
* transmission is completed, switches to asynchronous and enables backlight.
*/
rt_pin_write(spi_dev->bl_pin, BL_ACTIVE_LEVEL);
bl_en = true;
te_input_pin_cfg(spi_dev);
}
}
}
static struct lv_spi_dev *lv_spi_setup(void)
{
struct lv_spi_dev *spi = NULL;
rt_base_t pin;
spi = rt_malloc(sizeof(struct lv_spi_dev));
if (!spi) {
LV_LOG_ERROR("malloc spi dev failed\n");
return NULL;
}
rt_memset(spi, 0, sizeof(*spi));
spi->bus_name = SPI_BUF_NAME;
spi->mode = SPI_MODE;
spi->max_hz = SPI_MAX_HZ;
pin = rt_pin_get(RS_PIN);
if (pin < 0) {
LV_LOG_ERROR("get spi rs pin failed\n");
rt_free(spi);
return NULL;
}
rt_pin_mode(pin, PIN_MODE_OUTPUT);
rt_pin_write(pin, PIN_LOW);
spi->rs_pin = pin;
spi->bl_pin = rt_pin_get(BL_PIN);
if (spi->bl_pin < 0) {
LV_LOG_ERROR("get spi bl pin failed\n");
rt_free(spi);
return NULL;
}
rt_pin_mode(spi->bl_pin, PIN_MODE_OUTPUT);
rt_pin_write(spi->bl_pin, PIN_HIGH);
g_spi_dev = spi;
spi->display_sem = aicos_sem_create(0);
spi->send_sem = aicos_sem_create(0);
spi->te_queue = lv_spi_create_te_queue();
spi->frame_count = 0;
struct mpp_fb *fb = mpp_fb_open();
mpp_fb_ioctl(fb, AICFB_GET_SCREENINFO, &spi->info);
int tx_size = spi->info.width * spi->info.height * 2;
spi->tx_buf = aicos_malloc_align(MEM_CMA, tx_size, CACHE_LINE_SIZE);
if (!spi->tx_buf) {
LV_LOG_ERROR("malloc display buf failed\n");
rt_free(spi);
return NULL;
}
aicos_dcache_clean_invalid_range((ulong *)spi->tx_buf, (ulong)ALIGN_UP(tx_size, CACHE_LINE_SIZE));
spi->tx_len = tx_size;
spi->ge2d_dev = mpp_ge_open();
if (lv_spi_init(spi) < 0) {
rt_free(spi);
if (spi->tx_buf)
aicos_free_align(MEM_CMA, spi->tx_buf);
return NULL;
}
return spi;
}
void lv_spi_screen_enable(void)
{
struct lv_spi_dev *dev = NULL;
aicos_thread_t thid = NULL;
dev = lv_spi_setup();
if (!dev) {
LV_LOG_ERROR("spi setup failed\n");
return;
}
lv_spi_panel_enable(dev);
thid = aicos_thread_create("spi_disp", 8192, 15, disp_thread, dev);
if (thid == NULL)
LV_LOG_ERROR("Failed to create display thread\n");
}
static lv_color_format_t lv_display_fmt(enum mpp_pixel_format cf)
{
lv_color_format_t fmt = LV_COLOR_FORMAT_ARGB8888;
switch(cf) {
case MPP_FMT_RGB_565:
fmt = LV_COLOR_FORMAT_RGB565;
break;
case MPP_FMT_RGB_888:
fmt = LV_COLOR_FORMAT_RGB888;
break;
case MPP_FMT_ARGB_8888:
fmt = LV_COLOR_FORMAT_ARGB8888;
break;
case MPP_FMT_XRGB_8888:
fmt = LV_COLOR_FORMAT_XRGB8888;
break;
default:
LV_LOG_ERROR("unsupported format:%d", cf);
break;
}
return fmt;
}
static void spi_disp_poweron(void)
{
static bool first_frame = true;
if (first_frame) {
lv_spi_screen_enable();
first_frame = false;
}
}
static void spi_disp_flush(lv_display_t *disp, const lv_area_t *area, uint8_t *px_map)
{
spi_disp_t *spi_disp = (spi_disp_t *)lv_display_get_user_data(disp);
lv_draw_buf_t *disp_buf = lv_display_get_buf_active(disp);
(void)px_map;
if (lv_disp_flush_is_last(disp)) {
spi_disp_poweron();
aicos_dcache_clean_invalid_range((ulong *)disp_buf->data, (ulong)ALIGN_UP(spi_disp->info.smem_len, CACHE_LINE_SIZE));
lv_spi_flush(disp_buf->data, spi_disp->info.smem_len);
}
lv_display_flush_ready(disp);
}
void lv_spi_display_init(void)
{
spi_disp_t *spi_disp = NULL;
spi_disp = (spi_disp_t *)lv_malloc_zeroed(sizeof(spi_disp_t));
if (!spi_disp) {
LV_LOG_ERROR("malloc aic display failed");
goto err;
}
spi_disp->fb = mpp_fb_open();
if (!spi_disp->fb) {
LV_LOG_ERROR("open mpp fb failed");
goto err;
}
mpp_fb_ioctl(spi_disp->fb, AICFB_GET_SCREENINFO, &spi_disp->info);
int width = spi_disp->info.width;
int height = spi_disp->info.height;
int fb_size = spi_disp->info.smem_len;
spi_disp->buf1 = aicos_malloc_align(MEM_CMA, fb_size, CACHE_LINE_SIZE);
if (!spi_disp->buf1) {
LV_LOG_ERROR("malloc display buf1 failed");
goto err;
}
spi_disp->buf2 = aicos_malloc_align(MEM_CMA, fb_size, CACHE_LINE_SIZE);
if (!spi_disp->buf2) {
LV_LOG_ERROR("malloc display buf2 failed");
goto err;
}
lv_color_format_t cf = lv_display_fmt(spi_disp->info.format);
if (cf == LV_COLOR_FORMAT_UNKNOWN)
goto err;
lv_display_t *disp = lv_display_create(width, height);
lv_display_set_color_format(disp, cf);
lv_display_set_flush_cb(disp, spi_disp_flush);
lv_display_set_user_data(disp, spi_disp);
lv_display_set_buffers(disp, spi_disp->buf1, spi_disp->buf2, fb_size, LV_DISPLAY_RENDER_MODE_DIRECT);
spi_disp->disp = disp;
return;
err:
if (spi_disp)
lv_free(spi_disp);
if (spi_disp->buf1)
lv_free(spi_disp->buf1);
if (spi_disp->buf2)
lv_free(spi_disp->buf2);
LV_LOG_ERROR("create lv spi display failed");
}

75
packages/artinchip/lvgl-ui/aic_widgets/aic_spi/lv_aic_spi.h Normal file
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@@ -0,0 +1,75 @@
/*
* Copyright (C) 2025, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: Huahui <huahui.mai@artinchip.com>
*/
#include <string.h>
#include <rtdevice.h>
#include <aic_core.h>
#include <drv_qspi.h>
#include "lvgl.h"
#include <mpp_fb.h>
#include <mpp_ge.h>
typedef void (*ui_init_cb)(void);
typedef struct {
struct mpp_fb *fb;
struct aicfb_screeninfo info;
void *buf1;
void *buf2;
lv_display_t *disp;
} spi_disp_t;
struct lv_spi_dev {
const char * bus_name;
unsigned int mode;
unsigned int max_hz;
void *dev;
unsigned int rs_pin;
unsigned int bl_pin;
unsigned char *data;
unsigned int len;
unsigned char *tx_buf;
unsigned int tx_len;
struct mpp_ge *ge2d_dev;
aicos_sem_t display_sem;
aicos_sem_t send_sem;
aicos_wqueue_t te_queue;
unsigned int frame_count;
struct aicfb_screeninfo info;
};
void lv_spi_flush(u8 *data, unsigned int len);
void lv_spi_write_buffer(struct lv_spi_dev *spi_dev,
unsigned int cmd, unsigned int len, const u8 *data);
void lv_spi_display_init(void);
/*
* defined in the spi tft controller dirver lv_xxx.c
*/
void lv_spi_panel_enable(struct lv_spi_dev *dev);
#define lv_spi_write_seq(dev, cmd, seq...) \
do { \
static const u8 d[] = { seq }; \
lv_spi_write_buffer(dev, cmd, ARRAY_SIZE(d), d); \
} while(0);
/*
* Init ArtInChip SoC SPI Controller and enable
* lcd peripheral by calling lv_spi_panel_enable()
*/
void lv_spi_screen_enable(void);

78
packages/artinchip/lvgl-ui/aic_widgets/aic_spi/lv_gc9d01n.c Normal file
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@@ -0,0 +1,78 @@
/*
* Copyright (C) 2025, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: Huahui <huahui.mai@artinchip.com>
*/
#include <rtdevice.h>
#include "lv_aic_spi.h"
#define GC9D01N_RST_PIN "PB.11"
void lv_spi_panel_enable(struct lv_spi_dev *dev)
{
u32 rst_pin;
rst_pin = rt_pin_get(GC9D01N_RST_PIN);
rt_pin_mode(rst_pin, PIN_MODE_OUTPUT);
rt_pin_write(rst_pin, 1);
rt_thread_mdelay(120);
lv_spi_write_seq(dev, 0xFE);
lv_spi_write_seq(dev, 0xEF);
lv_spi_write_seq(dev, 0x80, 0xFF);
lv_spi_write_seq(dev, 0x81, 0xFF);
lv_spi_write_seq(dev, 0x82, 0xFF);
lv_spi_write_seq(dev, 0x83, 0xFF);
lv_spi_write_seq(dev, 0x84, 0xFF);
lv_spi_write_seq(dev, 0x85, 0xFF);
lv_spi_write_seq(dev, 0x86, 0xFF);
lv_spi_write_seq(dev, 0x87, 0xFF);
lv_spi_write_seq(dev, 0x88, 0xFF);
lv_spi_write_seq(dev, 0x89, 0xFF);
lv_spi_write_seq(dev, 0x8A, 0xFF);
lv_spi_write_seq(dev, 0x8B, 0xFF);
lv_spi_write_seq(dev, 0x8C, 0xFF);
lv_spi_write_seq(dev, 0x8D, 0xFF);
lv_spi_write_seq(dev, 0x8E, 0xFF);
lv_spi_write_seq(dev, 0x8F, 0xFF);
lv_spi_write_seq(dev, 0x3A, 0x05);
lv_spi_write_seq(dev, 0xEC, 0x01);
lv_spi_write_seq(dev, 0x74, 0x02, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00);
lv_spi_write_seq(dev, 0x98, 0x3E);
lv_spi_write_seq(dev, 0x99, 0x3E);
lv_spi_write_seq(dev, 0xB5, 0x0D, 0x0D);
lv_spi_write_seq(dev, 0x60, 0x38, 0x0F, 0x79, 0x67);
lv_spi_write_seq(dev, 0x61, 0x38, 0x11, 0x79, 0x67);
lv_spi_write_seq(dev, 0x64, 0x38, 0x17, 0x71, 0x5F, 0x79, 0x67);
lv_spi_write_seq(dev, 0x65, 0x38, 0x13, 0x71, 0x5B, 0x79, 0x67);
lv_spi_write_seq(dev, 0x6A, 0x00, 0x00);
lv_spi_write_seq(dev, 0x6C, 0x22, 0x02, 0x22, 0x02, 0x22, 0x22, 0x50);
lv_spi_write_seq(dev, 0x6E, 0x03, 0x03, 0x01, 0x01, 0x00, 0x00, 0x0f, 0x0f, 0x0d, 0x0d, 0x0b,
0x0b, 0x09, 0x09, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x0a, 0x0c, 0x0c, 0x0e,
0x0e, 0x10, 0x10, 0x00, 0x00, 0x02, 0x02, 0x04, 0x04);
lv_spi_write_seq(dev, 0xbf, 0x01);
lv_spi_write_seq(dev, 0xF9, 0x40);
lv_spi_write_seq(dev, 0x9b, 0x3b);
lv_spi_write_seq(dev, 0x93, 0x33, 0x7f, 0x00);
lv_spi_write_seq(dev, 0x7E, 0x30);
lv_spi_write_seq(dev, 0x70, 0x0d, 0x02, 0x08, 0x0d, 0x02, 0x08);
lv_spi_write_seq(dev, 0x71, 0x0d, 0x02, 0x08);
lv_spi_write_seq(dev, 0x91, 0x0E, 0x09);
lv_spi_write_seq(dev, 0xc3, 0x18);
lv_spi_write_seq(dev, 0xc4, 0x18);
lv_spi_write_seq(dev, 0xc9, 0x3c);
lv_spi_write_seq(dev, 0xf0, 0x13, 0x15, 0x04, 0x05, 0x01, 0x38);
lv_spi_write_seq(dev, 0xf2, 0x13, 0x15, 0x04, 0x05, 0x01, 0x34);
lv_spi_write_seq(dev, 0xf1, 0x4b, 0xb8, 0x7b, 0x34, 0x35, 0xef);
lv_spi_write_seq(dev, 0xf3, 0x47, 0xb4, 0x72, 0x34, 0x35, 0xda);
lv_spi_write_seq(dev, 0x36, 0x00);
lv_spi_write_seq(dev, 0x11);
rt_thread_mdelay(120);
lv_spi_write_seq(dev, 0x29);
rt_thread_mdelay(20);
}

49
packages/artinchip/lvgl-ui/aic_widgets/aic_spi/lv_st7789.c Normal file
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@@ -0,0 +1,49 @@
/*
* Copyright (C) 2025, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: Huahui <huahui.mai@artinchip.com>
*/
#include <rtdevice.h>
#include "lv_aic_spi.h"
#define ST7789_RESET_PIN "PB.10"
void lv_spi_panel_enable(struct lv_spi_dev *dev)
{
u32 rst_pin;
rst_pin = rt_pin_get(ST7789_RESET_PIN);
rt_pin_mode(rst_pin, PIN_MODE_OUTPUT);
rt_pin_write(rst_pin, 1);
rt_thread_mdelay(120);
lv_spi_write_seq(dev, 0x11);
rt_thread_mdelay(120);
lv_spi_write_seq(dev, 0x36, 0x00);
lv_spi_write_seq(dev, 0x3a, 0x05);
lv_spi_write_seq(dev, 0x21);
lv_spi_write_seq(dev, 0xB2, 0x05, 0x05, 0x00, 0x33, 0x33);
lv_spi_write_seq(dev, 0xB7, 0x74);
lv_spi_write_seq(dev, 0xBB, 0x25);
lv_spi_write_seq(dev, 0xC0, 0x2C);
lv_spi_write_seq(dev, 0xC2, 0x01);
lv_spi_write_seq(dev, 0xC3, 0x13);
lv_spi_write_seq(dev, 0xC4, 0x20);
lv_spi_write_seq(dev, 0xC6, 0x0F);
lv_spi_write_seq(dev, 0xD0, 0xA4, 0xA1);
lv_spi_write_seq(dev, 0xD6, 0xA1);
lv_spi_write_seq(dev, 0xE0, 0xD0, 0x08, 0x0D, 0x0C, 0x0B, 0x26, 0x30, 0x33, 0x47, 0x36, 0x14,
0x14, 0x2A, 0x2E);
lv_spi_write_seq(dev, 0xE1, 0xD0, 0x05, 0x0A, 0x09, 0x08, 0x04, 0x2E, 0x44, 0x45, 0x39, 0x15,
0x16, 0x2C, 0x2F);
lv_spi_write_seq(dev, 0x2A,0x00, 0x34, 0x00, 0xBB);
lv_spi_write_seq(dev, 0x2B,0x00, 0x28, 0x01, 0x17);
lv_spi_write_seq(dev, 0x29);
rt_thread_mdelay(10);
}

279
packages/artinchip/lvgl-ui/aic_widgets/aic_spi/lv_st77912.c Normal file
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/*
* Copyright (C) 2025, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: Huahui <huahui.mai@artinchip.com>
*/
#include <rtdevice.h>
#include "lv_aic_spi.h"
#define ST77912_RST_PIN "PD.19"
void lv_spi_panel_enable(struct lv_spi_dev *dev)
{
u32 rst_pin;
rst_pin = rt_pin_get(ST77912_RST_PIN);
rt_pin_mode(rst_pin, PIN_MODE_OUTPUT);
rt_pin_write(rst_pin, 1);
rt_thread_mdelay(120);
lv_spi_write_seq(dev, 0xF0, 0x01);
lv_spi_write_seq(dev, 0xF1, 0x01);
lv_spi_write_seq(dev, 0x7A, 0x83);
lv_spi_write_seq(dev, 0xB0, 0x5E);
lv_spi_write_seq(dev, 0xB1, 0x55);
lv_spi_write_seq(dev, 0xB2, 0x24);
lv_spi_write_seq(dev, 0xB4, 0xA7);
lv_spi_write_seq(dev, 0xB5, 0x54);
lv_spi_write_seq(dev, 0xB6, 0x8B);
lv_spi_write_seq(dev, 0xB7, 0x50);
lv_spi_write_seq(dev, 0xBA, 0x00);
lv_spi_write_seq(dev, 0xBB, 0x08);
lv_spi_write_seq(dev, 0xBC, 0x08);
lv_spi_write_seq(dev, 0xBD, 0x00);
lv_spi_write_seq(dev, 0xC0, 0x80);
lv_spi_write_seq(dev, 0xC1, 0x08);
lv_spi_write_seq(dev, 0xC2, 0x54);
lv_spi_write_seq(dev, 0xC3, 0x80);
lv_spi_write_seq(dev, 0xC4, 0x08);
lv_spi_write_seq(dev, 0xC5, 0x54);
lv_spi_write_seq(dev, 0xC6, 0xA9);
lv_spi_write_seq(dev, 0xC7, 0x41);
lv_spi_write_seq(dev, 0xC8, 0x51);
lv_spi_write_seq(dev, 0xC9, 0xA9);
lv_spi_write_seq(dev, 0xCA, 0x41);
lv_spi_write_seq(dev, 0xCB, 0x51);
lv_spi_write_seq(dev, 0xD0, 0x80);
lv_spi_write_seq(dev, 0xD1, 0xF0);
lv_spi_write_seq(dev, 0xD2, 0xF0);
lv_spi_write_seq(dev, 0xF5, 0x00, 0xA5);
lv_spi_write_seq(dev, 0xDD, 0x36);
lv_spi_write_seq(dev, 0xDE, 0x36);
lv_spi_write_seq(dev, 0xF0, 0x02);
lv_spi_write_seq(dev, 0xF1, 0x01);
lv_spi_write_seq(dev, 0xE0, 0xF0, 0x16, 0x1C, 0x0A, 0x0A, 0x06, 0x3E, 0x33, 0x53, 0x07, 0x14, 0x13, 0x31, 0x35);
lv_spi_write_seq(dev, 0xE1, 0xF0, 0x16, 0x1C, 0x0A, 0x0A, 0x06, 0x3E, 0x33, 0x53, 0x07, 0x14, 0x13, 0x31, 0x35);
lv_spi_write_seq(dev, 0xF0, 0x10);
lv_spi_write_seq(dev, 0xF3, 0x10);
lv_spi_write_seq(dev, 0xE0, 0x0B);
lv_spi_write_seq(dev, 0xE1, 0x00);
lv_spi_write_seq(dev, 0xE2, 0x00);
lv_spi_write_seq(dev, 0xE3, 0x00);
lv_spi_write_seq(dev, 0xE4, 0xE0);
lv_spi_write_seq(dev, 0xE5, 0x06);
lv_spi_write_seq(dev, 0xE6, 0x21);
lv_spi_write_seq(dev, 0xE7, 0x80);
lv_spi_write_seq(dev, 0xE8, 0x0A);
lv_spi_write_seq(dev, 0xE9, 0x00);
lv_spi_write_seq(dev, 0xEA, 0x04);
lv_spi_write_seq(dev, 0xEB, 0x00);
lv_spi_write_seq(dev, 0xEC, 0x00);
lv_spi_write_seq(dev, 0xED, 0x24);
lv_spi_write_seq(dev, 0xEE, 0x00);
lv_spi_write_seq(dev, 0xEF, 0x00);
lv_spi_write_seq(dev, 0xF8, 0xFF);
lv_spi_write_seq(dev, 0xF9, 0x00);
lv_spi_write_seq(dev, 0xFA, 0x00);
lv_spi_write_seq(dev, 0xFB, 0x30);
lv_spi_write_seq(dev, 0xFC, 0x00);
lv_spi_write_seq(dev, 0xFD, 0x00);
lv_spi_write_seq(dev, 0xFE, 0x00);
lv_spi_write_seq(dev, 0xFF, 0x00);
lv_spi_write_seq(dev, 0x60, 0x40);
lv_spi_write_seq(dev, 0x61, 0x08);
lv_spi_write_seq(dev, 0x62, 0x00);
lv_spi_write_seq(dev, 0x63, 0x41);
lv_spi_write_seq(dev, 0x64, 0xED);
lv_spi_write_seq(dev, 0x65, 0x00);
lv_spi_write_seq(dev, 0x66, 0x40);
lv_spi_write_seq(dev, 0x67, 0x00);
lv_spi_write_seq(dev, 0x68, 0x00);
lv_spi_write_seq(dev, 0x69, 0x40);
lv_spi_write_seq(dev, 0x6A, 0x00);
lv_spi_write_seq(dev, 0x6B, 0x00);
lv_spi_write_seq(dev, 0x70, 0x40);
lv_spi_write_seq(dev, 0x71, 0x07);
lv_spi_write_seq(dev, 0x72, 0x00);
lv_spi_write_seq(dev, 0x73, 0x41);
lv_spi_write_seq(dev, 0x74, 0xEC);
lv_spi_write_seq(dev, 0x75, 0x00);
lv_spi_write_seq(dev, 0x76, 0x40);
lv_spi_write_seq(dev, 0x77, 0x00);
lv_spi_write_seq(dev, 0x78, 0x00);
lv_spi_write_seq(dev, 0x79, 0x40);
lv_spi_write_seq(dev, 0x7A, 0x00);
lv_spi_write_seq(dev, 0x7B, 0x00);
lv_spi_write_seq(dev, 0x80, 0x48);
lv_spi_write_seq(dev, 0x81, 0x00);
lv_spi_write_seq(dev, 0x82, 0x0A);
lv_spi_write_seq(dev, 0x83, 0x01);
lv_spi_write_seq(dev, 0x84, 0xEA);
lv_spi_write_seq(dev, 0x85, 0x00);
lv_spi_write_seq(dev, 0x86, 0x00);
lv_spi_write_seq(dev, 0x87, 0x00);
lv_spi_write_seq(dev, 0x88, 0x48);
lv_spi_write_seq(dev, 0x89, 0x00);
lv_spi_write_seq(dev, 0x8A, 0x0C);
lv_spi_write_seq(dev, 0x8B, 0x01);
lv_spi_write_seq(dev, 0x8C, 0xEC);
lv_spi_write_seq(dev, 0x8D, 0x00);
lv_spi_write_seq(dev, 0x8E, 0x00);
lv_spi_write_seq(dev, 0x8F, 0x00);
lv_spi_write_seq(dev, 0x90, 0x48);
lv_spi_write_seq(dev, 0x91, 0x00);
lv_spi_write_seq(dev, 0x92, 0x0E);
lv_spi_write_seq(dev, 0x93, 0x01);
lv_spi_write_seq(dev, 0x94, 0xEE);
lv_spi_write_seq(dev, 0x95, 0x00);
lv_spi_write_seq(dev, 0x96, 0x00);
lv_spi_write_seq(dev, 0x97, 0x00);
lv_spi_write_seq(dev, 0x98, 0x48);
lv_spi_write_seq(dev, 0x99, 0x00);
lv_spi_write_seq(dev, 0x9A, 0x10);
lv_spi_write_seq(dev, 0x9B, 0x01);
lv_spi_write_seq(dev, 0x9C, 0xF0);
lv_spi_write_seq(dev, 0x9D, 0x00);
lv_spi_write_seq(dev, 0x9E, 0x00);
lv_spi_write_seq(dev, 0x9F, 0x00);
lv_spi_write_seq(dev, 0xA0, 0x48);
lv_spi_write_seq(dev, 0xA1, 0x00);
lv_spi_write_seq(dev, 0xA2, 0x09);
lv_spi_write_seq(dev, 0xA3, 0x01);
lv_spi_write_seq(dev, 0xA4, 0xE9);
lv_spi_write_seq(dev, 0xA5, 0x00);
lv_spi_write_seq(dev, 0xA6, 0x00);
lv_spi_write_seq(dev, 0xA7, 0x00);
lv_spi_write_seq(dev, 0xA8, 0x48);
lv_spi_write_seq(dev, 0xA9, 0x00);
lv_spi_write_seq(dev, 0xAA, 0x0B);
lv_spi_write_seq(dev, 0xAB, 0x01);
lv_spi_write_seq(dev, 0xAC, 0xEB);
lv_spi_write_seq(dev, 0xAD, 0x00);
lv_spi_write_seq(dev, 0xAE, 0x00);
lv_spi_write_seq(dev, 0xAF, 0x00);
lv_spi_write_seq(dev, 0xB0, 0x48);
lv_spi_write_seq(dev, 0xB1, 0x00);
lv_spi_write_seq(dev, 0xB2, 0x0D);
lv_spi_write_seq(dev, 0xB3, 0x01);
lv_spi_write_seq(dev, 0xB4, 0xED);
lv_spi_write_seq(dev, 0xB5, 0x00);
lv_spi_write_seq(dev, 0xB6, 0x00);
lv_spi_write_seq(dev, 0xB7, 0x00);
lv_spi_write_seq(dev, 0xB8, 0x48);
lv_spi_write_seq(dev, 0xB9, 0x00);
lv_spi_write_seq(dev, 0xBA, 0x0F);
lv_spi_write_seq(dev, 0xBB, 0x01);
lv_spi_write_seq(dev, 0xBC, 0xEF);
lv_spi_write_seq(dev, 0xBD, 0x00);
lv_spi_write_seq(dev, 0xBE, 0x00);
lv_spi_write_seq(dev, 0xBF, 0x00);
lv_spi_write_seq(dev, 0xC0, 0x88);
lv_spi_write_seq(dev, 0xC1, 0x99);
lv_spi_write_seq(dev, 0xC2, 0x01);
lv_spi_write_seq(dev, 0xC3, 0xAA);
lv_spi_write_seq(dev, 0xC4, 0xBB);
lv_spi_write_seq(dev, 0xC5, 0x74);
lv_spi_write_seq(dev, 0xC6, 0x65);
lv_spi_write_seq(dev, 0xC7, 0x56);
lv_spi_write_seq(dev, 0xC8, 0x47);
lv_spi_write_seq(dev, 0xC9, 0x10);
lv_spi_write_seq(dev, 0xD0, 0x88);
lv_spi_write_seq(dev, 0xD1, 0x99);
lv_spi_write_seq(dev, 0xD2, 0x01);
lv_spi_write_seq(dev, 0xD3, 0xAA);
lv_spi_write_seq(dev, 0xD4, 0xBB);
lv_spi_write_seq(dev, 0xD5, 0x74);
lv_spi_write_seq(dev, 0xD6, 0x65);
lv_spi_write_seq(dev, 0xD7, 0x56);
lv_spi_write_seq(dev, 0xD8, 0x47);
lv_spi_write_seq(dev, 0xD9, 0x10);
lv_spi_write_seq(dev, 0xF0, 0x08);
lv_spi_write_seq(dev, 0xF2, 0x08);
lv_spi_write_seq(dev, 0x71, 0x03);
lv_spi_write_seq(dev, 0x73, 0x30);
lv_spi_write_seq(dev, 0x76, 0x00);
lv_spi_write_seq(dev, 0x78, 0x33);
lv_spi_write_seq(dev, 0x79, 0x01);
lv_spi_write_seq(dev, 0x7B, 0xFA);
lv_spi_write_seq(dev, 0x7E, 0x16);
lv_spi_write_seq(dev, 0x86, 0x55);
lv_spi_write_seq(dev, 0x89, 0x61);
lv_spi_write_seq(dev, 0x8A, 0x00);
lv_spi_write_seq(dev, 0xF0, 0x01);
lv_spi_write_seq(dev, 0xF1, 0x01);
lv_spi_write_seq(dev, 0xA0, 0x0B);
lv_spi_write_seq(dev, 0xA3, 0x2A);
lv_spi_write_seq(dev, 0xA5, 0xC3);
lv_spi_write_seq(dev, 0x00, 0x1);
lv_spi_write_seq(dev, 0xA3, 0x2B);
lv_spi_write_seq(dev, 0xA5, 0xC3);
lv_spi_write_seq(dev, 0x00, 0x1);
lv_spi_write_seq(dev, 0xA3, 0x2C);
lv_spi_write_seq(dev, 0xA5, 0xC3);
lv_spi_write_seq(dev, 0x00, 0x1);
lv_spi_write_seq(dev, 0xA3, 0x2D);
lv_spi_write_seq(dev, 0xA5, 0xC3);
lv_spi_write_seq(dev, 0x00, 0x1);
lv_spi_write_seq(dev, 0xA3, 0x2E);
lv_spi_write_seq(dev, 0xA5, 0xC3);
lv_spi_write_seq(dev, 0x00, 0x1);
lv_spi_write_seq(dev, 0xA3, 0x2F);
lv_spi_write_seq(dev, 0xA5, 0xC3);
lv_spi_write_seq(dev, 0x00, 0x1);
lv_spi_write_seq(dev, 0xA3, 0x30);
lv_spi_write_seq(dev, 0xA5, 0xC3);
lv_spi_write_seq(dev, 0x00, 0x1);
lv_spi_write_seq(dev, 0xA3, 0x31);
lv_spi_write_seq(dev, 0xA5, 0xC3);
lv_spi_write_seq(dev, 0x00, 0x1);
lv_spi_write_seq(dev, 0xA3, 0x32);
lv_spi_write_seq(dev, 0xA5, 0xC3);
lv_spi_write_seq(dev, 0x00, 0x1);
lv_spi_write_seq(dev, 0xA3, 0x33);
lv_spi_write_seq(dev, 0xA5, 0xC3);
lv_spi_write_seq(dev, 0x00, 0x1);
lv_spi_write_seq(dev, 0xA0, 0x09);
lv_spi_write_seq(dev, 0xF0, 0x00);
lv_spi_write_seq(dev, 0xF1, 0x10);
lv_spi_write_seq(dev, 0xF2, 0x84);
lv_spi_write_seq(dev, 0xF3, 0x01);
lv_spi_write_seq(dev, 0x3A, 0x05);
lv_spi_write_seq(dev, 0x21);
lv_spi_write_seq(dev, 0x11);
rt_thread_mdelay(120);
lv_spi_write_seq(dev, 0x29);
rt_thread_mdelay(20);
}

224
packages/artinchip/lvgl-ui/aic_widgets/aic_spi/lv_st77916.c Normal file
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/*
* Copyright (C) 2025, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: Huahui <huahui.mai@artinchip.com>
*/
#include <rtdevice.h>
#include "lv_aic_spi.h"
#define ST77916_RST_PIN "PE.11"
void lv_spi_panel_enable(struct lv_spi_dev *dev)
{
u32 rst_pin;
rst_pin = rt_pin_get(ST77916_RST_PIN);
rt_pin_mode(rst_pin, PIN_MODE_OUTPUT);
rt_pin_write(rst_pin, 1);
rt_thread_mdelay(120);
lv_spi_write_seq(dev, 0xf0, 0x28);
lv_spi_write_seq(dev, 0xf2, 0x28);
lv_spi_write_seq(dev, 0x73, 0xF0);
lv_spi_write_seq(dev, 0x7C, 0xD1);
lv_spi_write_seq(dev, 0x83, 0xE0);
lv_spi_write_seq(dev, 0x84, 0x61);
lv_spi_write_seq(dev, 0xf2, 0x82);
lv_spi_write_seq(dev, 0xf0, 0x00);
lv_spi_write_seq(dev, 0xf0, 0x01);
lv_spi_write_seq(dev, 0xf1, 0x01);
lv_spi_write_seq(dev, 0xB0, 0x5E);
lv_spi_write_seq(dev, 0xB1, 0x55);
lv_spi_write_seq(dev, 0xB2, 0x24);
lv_spi_write_seq(dev, 0xB3, 0x01);
lv_spi_write_seq(dev, 0xB4, 0x87);
lv_spi_write_seq(dev, 0xB5, 0x44);
lv_spi_write_seq(dev, 0xB6, 0x8B);
lv_spi_write_seq(dev, 0xB7, 0x40);
lv_spi_write_seq(dev, 0xB8, 0x86);
lv_spi_write_seq(dev, 0xB9, 0x15);
lv_spi_write_seq(dev, 0xBA, 0x00);
lv_spi_write_seq(dev, 0xBB, 0x08);
lv_spi_write_seq(dev, 0xBC, 0x08);
lv_spi_write_seq(dev, 0xBD, 0x00);
lv_spi_write_seq(dev, 0xBE, 0x00);
lv_spi_write_seq(dev, 0xBF, 0x07);
lv_spi_write_seq(dev, 0xC0, 0x80);
lv_spi_write_seq(dev, 0xC1, 0x10);
lv_spi_write_seq(dev, 0xC2, 0x37);
lv_spi_write_seq(dev, 0xC3, 0x80);
lv_spi_write_seq(dev, 0xC4, 0x10);
lv_spi_write_seq(dev, 0xC5, 0x37);
lv_spi_write_seq(dev, 0xC6, 0xA9);
lv_spi_write_seq(dev, 0xC7, 0x41);
lv_spi_write_seq(dev, 0xC8, 0x01);
lv_spi_write_seq(dev, 0xC9, 0xA9);
lv_spi_write_seq(dev, 0xCA, 0x41);
lv_spi_write_seq(dev, 0xCB, 0x01);
lv_spi_write_seq(dev, 0xCC, 0x7F);
lv_spi_write_seq(dev, 0xCD, 0x7F);
lv_spi_write_seq(dev, 0xCE, 0xFF);
lv_spi_write_seq(dev, 0xD0, 0x91);
lv_spi_write_seq(dev, 0xD1, 0x68);
lv_spi_write_seq(dev, 0xD2, 0x68);
lv_spi_write_seq(dev, 0xF5, 0x00, 0xA5);
lv_spi_write_seq(dev, 0xDD, 0x40);
lv_spi_write_seq(dev, 0xDE, 0x40);
lv_spi_write_seq(dev, 0xF1, 0x10);
lv_spi_write_seq(dev, 0xf0, 0x00);
lv_spi_write_seq(dev, 0xf0, 0x02);
lv_spi_write_seq(dev, 0xE0, 0xF0, 0x10, 0x18, 0x0D, 0x0C, 0x38, 0x3E,
0x44, 0x51, 0x39, 0x15, 0x15, 0x30, 0x34);
lv_spi_write_seq(dev, 0xE1, 0xF0, 0x0F, 0x17, 0x0D, 0x0B, 0x07, 0x3E,
0x33, 0x51, 0x39, 0x15, 0x15, 0x30, 0x34);
lv_spi_write_seq(dev, 0xf0, 0x10);
lv_spi_write_seq(dev, 0xF3, 0x10);
lv_spi_write_seq(dev, 0xE0, 0x08);
lv_spi_write_seq(dev, 0xE1, 0x00);
lv_spi_write_seq(dev, 0xE2, 0x00);
lv_spi_write_seq(dev, 0xE3, 0x00);
lv_spi_write_seq(dev, 0xE4, 0xE0);
lv_spi_write_seq(dev, 0xE5, 0x06);
lv_spi_write_seq(dev, 0xE6, 0x21);
lv_spi_write_seq(dev, 0xE7, 0x03);
lv_spi_write_seq(dev, 0xE8, 0x05);
lv_spi_write_seq(dev, 0xE9, 0x02);
lv_spi_write_seq(dev, 0xEA, 0xE9);
lv_spi_write_seq(dev, 0xEB, 0x00);
lv_spi_write_seq(dev, 0xEC, 0x00);
lv_spi_write_seq(dev, 0xED, 0x14);
lv_spi_write_seq(dev, 0xEE, 0xFF);
lv_spi_write_seq(dev, 0xEF, 0x00);
lv_spi_write_seq(dev, 0xF8, 0xFF);
lv_spi_write_seq(dev, 0xF9, 0x00);
lv_spi_write_seq(dev, 0xFA, 0x00);
lv_spi_write_seq(dev, 0xFB, 0x30);
lv_spi_write_seq(dev, 0xFC, 0x00);
lv_spi_write_seq(dev, 0xFD, 0x00);
lv_spi_write_seq(dev, 0xFE, 0x00);
lv_spi_write_seq(dev, 0xFF, 0x00);
lv_spi_write_seq(dev, 0x60, 0x40);
lv_spi_write_seq(dev, 0x61, 0x05);
lv_spi_write_seq(dev, 0x62, 0x00);
lv_spi_write_seq(dev, 0x63, 0x42);
lv_spi_write_seq(dev, 0x64, 0xDA);
lv_spi_write_seq(dev, 0x65, 0x00);
lv_spi_write_seq(dev, 0x66, 0x00);
lv_spi_write_seq(dev, 0x67, 0x00);
lv_spi_write_seq(dev, 0x68, 0x00);
lv_spi_write_seq(dev, 0x69, 0x00);
lv_spi_write_seq(dev, 0x6A, 0x00);
lv_spi_write_seq(dev, 0x6B, 0x00);
lv_spi_write_seq(dev, 0x70, 0x40);
lv_spi_write_seq(dev, 0x71, 0x04);
lv_spi_write_seq(dev, 0x72, 0x00);
lv_spi_write_seq(dev, 0x73, 0x42);
lv_spi_write_seq(dev, 0x74, 0xD9);
lv_spi_write_seq(dev, 0x75, 0x00);
lv_spi_write_seq(dev, 0x76, 0x00);
lv_spi_write_seq(dev, 0x77, 0x00);
lv_spi_write_seq(dev, 0x78, 0x00);
lv_spi_write_seq(dev, 0x79, 0x00);
lv_spi_write_seq(dev, 0x7A, 0x00);
lv_spi_write_seq(dev, 0x7B, 0x00);
lv_spi_write_seq(dev, 0x80, 0x48);
lv_spi_write_seq(dev, 0x81, 0x00);
lv_spi_write_seq(dev, 0x82, 0x07);
lv_spi_write_seq(dev, 0x83, 0x02);
lv_spi_write_seq(dev, 0x84, 0xD7);
lv_spi_write_seq(dev, 0x85, 0x04);
lv_spi_write_seq(dev, 0x86, 0x00);
lv_spi_write_seq(dev, 0x87, 0x00);
lv_spi_write_seq(dev, 0x88, 0x48);
lv_spi_write_seq(dev, 0x89, 0x00);
lv_spi_write_seq(dev, 0x8A, 0x09);
lv_spi_write_seq(dev, 0x8B, 0x02);
lv_spi_write_seq(dev, 0x8C, 0xD9);
lv_spi_write_seq(dev, 0x8D, 0x04);
lv_spi_write_seq(dev, 0x8E, 0x00);
lv_spi_write_seq(dev, 0x8F, 0x00);
lv_spi_write_seq(dev, 0x90, 0x48);
lv_spi_write_seq(dev, 0x91, 0x00);
lv_spi_write_seq(dev, 0x92, 0x0B);
lv_spi_write_seq(dev, 0x93, 0x02);
lv_spi_write_seq(dev, 0x94, 0xDB);
lv_spi_write_seq(dev, 0x95, 0x04);
lv_spi_write_seq(dev, 0x96, 0x00);
lv_spi_write_seq(dev, 0x97, 0x00);
lv_spi_write_seq(dev, 0x98, 0x48);
lv_spi_write_seq(dev, 0x99, 0x00);
lv_spi_write_seq(dev, 0x9A, 0x0D);
lv_spi_write_seq(dev, 0x9B, 0x02);
lv_spi_write_seq(dev, 0x9C, 0xDD);
lv_spi_write_seq(dev, 0x9D, 0x04);
lv_spi_write_seq(dev, 0x9E, 0x00);
lv_spi_write_seq(dev, 0x9F, 0x00);
lv_spi_write_seq(dev, 0xA0, 0x48);
lv_spi_write_seq(dev, 0xA1, 0x00);
lv_spi_write_seq(dev, 0xA2, 0x06);
lv_spi_write_seq(dev, 0xA3, 0x02);
lv_spi_write_seq(dev, 0xA4, 0xD6);
lv_spi_write_seq(dev, 0xA5, 0x04);
lv_spi_write_seq(dev, 0xA6, 0x00);
lv_spi_write_seq(dev, 0xA7, 0x00);
lv_spi_write_seq(dev, 0xA8, 0x48);
lv_spi_write_seq(dev, 0xA9, 0x00);
lv_spi_write_seq(dev, 0xAA, 0x08);
lv_spi_write_seq(dev, 0xAB, 0x02);
lv_spi_write_seq(dev, 0xAC, 0xD8);
lv_spi_write_seq(dev, 0xAD, 0x04);
lv_spi_write_seq(dev, 0xAE, 0x00);
lv_spi_write_seq(dev, 0xAF, 0x00);
lv_spi_write_seq(dev, 0xB0, 0x48);
lv_spi_write_seq(dev, 0xB1, 0x00);
lv_spi_write_seq(dev, 0xB2, 0x0A);
lv_spi_write_seq(dev, 0xB3, 0x02);
lv_spi_write_seq(dev, 0xB4, 0xDA);
lv_spi_write_seq(dev, 0xB5, 0x04);
lv_spi_write_seq(dev, 0xB6, 0x00);
lv_spi_write_seq(dev, 0xB7, 0x00);
lv_spi_write_seq(dev, 0xB8, 0x48);
lv_spi_write_seq(dev, 0xB9, 0x00);
lv_spi_write_seq(dev, 0xBA, 0x0C);
lv_spi_write_seq(dev, 0xBB, 0x02);
lv_spi_write_seq(dev, 0xBC, 0xDC);
lv_spi_write_seq(dev, 0xBD, 0x04);
lv_spi_write_seq(dev, 0xBE, 0x00);
lv_spi_write_seq(dev, 0xBF, 0x00);
lv_spi_write_seq(dev, 0xC0, 0x10);
lv_spi_write_seq(dev, 0xC1, 0x47);
lv_spi_write_seq(dev, 0xC2, 0x56);
lv_spi_write_seq(dev, 0xC3, 0x65);
lv_spi_write_seq(dev, 0xC4, 0x74);
lv_spi_write_seq(dev, 0xC5, 0x88);
lv_spi_write_seq(dev, 0xC6, 0x99);
lv_spi_write_seq(dev, 0xC7, 0x01);
lv_spi_write_seq(dev, 0xC8, 0xBB);
lv_spi_write_seq(dev, 0xC9, 0xAA);
lv_spi_write_seq(dev, 0xD0, 0x10);
lv_spi_write_seq(dev, 0xD1, 0x47);
lv_spi_write_seq(dev, 0xD2, 0x56);
lv_spi_write_seq(dev, 0xD3, 0x65);
lv_spi_write_seq(dev, 0xD4, 0x74);
lv_spi_write_seq(dev, 0xD5, 0x88);
lv_spi_write_seq(dev, 0xD6, 0x99);
lv_spi_write_seq(dev, 0xD7, 0x01);
lv_spi_write_seq(dev, 0xD8, 0xBB);
lv_spi_write_seq(dev, 0xD9, 0xAA);
lv_spi_write_seq(dev, 0xF3, 0x01);
lv_spi_write_seq(dev, 0xf0, 0x00);
lv_spi_write_seq(dev, 0x3A, 0x55);
lv_spi_write_seq(dev, 0x2A, 0x00, 0x00, 0x01, 0x67);
lv_spi_write_seq(dev, 0x2B, 0x00, 0x00, 0x01, 0x67);
lv_spi_write_seq(dev, 0x35, 0x00);
lv_spi_write_seq(dev, 0x21);
lv_spi_write_seq(dev, 0x11);
rt_thread_mdelay(120);
lv_spi_write_seq(dev, 0x29);
rt_thread_mdelay(20);
}