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v1.1.1

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This commit is contained in:
刘可亮
2024-10-30 16:50:31 +08:00
parent 0ef85b55da
commit 661e71562d
458 changed files with 46555 additions and 12133 deletions
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34
target/g73x/common/Kconfig.board
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@@ -14,7 +14,7 @@ source "bsp/artinchip/drv/gpio/Kconfig.dev"
# Interface Class
#================================================
comment "Interface Related: "
comment "Interface Related:"
#---------------------------
# uart device global option
@@ -66,6 +66,12 @@ source "bsp/artinchip/drv/uart/Kconfig.dev"
# i2c device global option
#---------------------------
config AIC_USING_SOFT_I2C
bool "Using SOFT_I2C"
default n
select RT_USING_I2C_BITOPS
select AIC_I2C_DRV
config AIC_USING_I2C0
bool "Using I2C0"
default n
@@ -331,7 +337,7 @@ source "packages/third-party/lwip/contrib/ports/drv/aic/Kconfig.dev"
# Storage Class
#================================================
comment "Storage Related: "
comment "Storage Related:"
#--------------------------------------------
# qspi device global option
@@ -406,6 +412,12 @@ menu "SPI1 Parameter"
bool "Dynamic DMA channel SPI1"
default n
config AIC_QSPI1_BUS_SPI
bool "Work in SPI BUS Mode"
default n
select AIC_QSPI_DRV
depends on AIC_QSPI1_BUS_WIDTH_1
endmenu
config AIC_USING_QSPI2
@@ -441,6 +453,11 @@ menu "SPI2 Parameter"
bool "Dynamic DMA channel SPI2"
default n
config AIC_QSPI2_BUS_SPI
bool "Work in SPI BUS Mode"
default y
select AIC_QSPI_DRV
endmenu
config AIC_USING_QSPI3
@@ -476,6 +493,11 @@ menu "SPI3 Parameter"
bool "Dynamic DMA channel SPI3"
default n
config AIC_QSPI3_BUS_SPI
bool "Work in SPI BUS Mode"
default y
select AIC_QSPI_DRV
endmenu
source "bsp/artinchip/drv/qspi/Kconfig.dev"
@@ -511,7 +533,7 @@ source "bsp/peripheral/wireless/Kconfig"
# Analog Class
#================================================
comment "Analog Related: "
comment "Analog Related:"
#---------------------------
# TSEN device global option
@@ -599,7 +621,7 @@ endmenu
# MutiMedia Class
#================================================
comment "MutiMedia Related: "
comment "MutiMedia Related:"
#--------------------------------------------
# DE device global option
@@ -688,7 +710,7 @@ endif
# System Class
#================================================
comment "System Related: "
comment "System Related:"
#---------------------------
# DMA device global option
@@ -1085,7 +1107,7 @@ source "bsp/artinchip/drv/pm/Kconfig"
# Security Class
#================================================
comment "Security Related: "
comment "Security Related:"
#--------------------------------------------
# spienc device global option

BIN
target/g73x/demo100-nor/pack/bootloader.bin
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4
target/g73x/demo100-nor/pack/image_cfg.json
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@@ -60,8 +60,8 @@
"head_ver": "0x00010001",
"loader": {
"file": "bootloader.bin",
"load address": "0x30100000",
"entry point": "0x30100100", // 256 byte aic header
"load address": "CONFIG_AIC_BOOTLOADER_LOAD_BASE",
"entry point": "CONFIG_AIC_BOOTLOADER_TEXT_BASE", // 256 byte aic header
},
"resource": {
"private": "pbp_cfg.bin",

BIN
target/g73x/demo68-nor/pack/bootloader.bin
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Binary file not shown.

4
target/g73x/demo68-nor/pack/image_cfg.json
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@@ -60,8 +60,8 @@
"head_ver": "0x00010001",
"loader": {
"file": "bootloader.bin",
"load address": "0x30100000",
"entry point": "0x30100100", // 256 byte aic header
"load address": "CONFIG_AIC_BOOTLOADER_LOAD_BASE",
"entry point": "CONFIG_AIC_BOOTLOADER_TEXT_BASE", // 256 byte aic header
},
"resource": {
"private": "pbp_cfg.bin",

14
target/g73x/scan/SConscript Executable file
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@@ -0,0 +1,14 @@
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
# add the board drivers.
src = Glob("*.c") + Glob("*.cpp") + Glob("*.S")
LOCAL_CPPPATH = [cwd]
CPPPATH = [cwd + '/include']
group = DefineGroup('Board', src, depend = [''], LOCAL_CPPPATH = LOCAL_CPPPATH, CPPPATH = CPPPATH)
Return('group')

187
target/g73x/scan/board.c Normal file
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@@ -0,0 +1,187 @@
/*
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: weilin.peng@artinchip.com
*/
#include <aic_core.h>
#include <rtconfig.h>
#include "board.h"
extern void aic_board_pinmux_init(void);
extern void aic_board_sysclk_init(void);
#if defined(KERNEL_RTTHREAD)
#include <aic_drv.h>
#include <rthw.h>
#include <rtthread.h>
extern size_t __heap_start;
extern size_t __heap_end;
#ifdef RT_USING_MEMHEAP
extern size_t __sram_cma_heap_start;
extern size_t __sram_cma_heap_end;
struct aic_memheap
{
aic_mem_region_t type;
char * name;
void * begin_addr;
void * end_addr;
struct rt_memheap heap;
struct rt_mutex lock;
};
struct aic_memheap aic_memheaps[] = {
#if defined(AIC_PSRAM_CMA_EN) || defined(AIC_SRAM1_CMA_EN)
{MEM_CMA, "heap_cma", (void *)&__cma_heap_start, (void *)&__cma_heap_end},
#endif
};
void aic_memheap_init(void)
{
rt_ubase_t begin_align;
rt_ubase_t end_align;
int i = 0;
for (i=0; i<sizeof(aic_memheaps)/sizeof(struct aic_memheap); i++) {
begin_align = RT_ALIGN((rt_ubase_t)aic_memheaps[i].begin_addr, RT_ALIGN_SIZE);
end_align = RT_ALIGN_DOWN((rt_ubase_t)aic_memheaps[i].end_addr, RT_ALIGN_SIZE);
RT_ASSERT(end_align > begin_align);
rt_memheap_init(&aic_memheaps[i].heap, aic_memheaps[i].name,
(void *)begin_align, end_align - begin_align);
rt_mutex_init(&aic_memheaps[i].lock, aic_memheaps[i].name, RT_IPC_FLAG_PRIO);
}
}
void *aic_memheap_malloc(int type, size_t size)
{
void *ptr;
int i = 0;
for (i=0; i<sizeof(aic_memheaps)/sizeof(struct aic_memheap); i++) {
if (aic_memheaps[i].type == type)
break;
}
if (i >= sizeof(aic_memheaps)/sizeof(struct aic_memheap))
return NULL;
/* Enter critical zone */
rt_mutex_take(&aic_memheaps[i].lock, RT_WAITING_FOREVER);
/* allocate memory block from system heap */
ptr = rt_memheap_alloc(&aic_memheaps[i].heap, size);
/* Exit critical zone */
rt_mutex_release(&aic_memheaps[i].lock);
return ptr;
}
void aic_memheap_free(int type, void *rmem)
{
int i = 0;
if (rmem == RT_NULL)
return;
for (i=0; i<sizeof(aic_memheaps)/sizeof(struct aic_memheap); i++) {
if (aic_memheaps[i].type == type)
break;
}
if (i >= sizeof(aic_memheaps)/sizeof(struct aic_memheap))
return;
/* Enter critical zone */
rt_mutex_take(&aic_memheaps[i].lock, RT_WAITING_FOREVER);
rt_memheap_free(rmem);
/* Exit critical zone */
rt_mutex_release(&aic_memheaps[i].lock);
}
#endif
/**
* This function will initial smart-evb board.
*/
void rt_hw_board_init(void)
{
aic_board_sysclk_init();
aic_board_pinmux_init();
#ifdef RT_USING_HEAP
rt_system_heap_init((void *)&__heap_start, (void *)&__heap_end);
#if (!defined(QEMU_RUN) && defined(RT_USING_MEMHEAP))
aic_memheap_init();
#endif
#endif
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
}
#elif defined(KERNEL_FREERTOS)
#elif defined(KERNEL_BAREMETAL)
#include <aic_tlsf.h>
void aic_hw_board_init(void)
{
#ifdef TLSF_MEM_HEAP
aic_tlsf_heap_init();
#endif
aic_board_sysclk_init();
aic_board_pinmux_init();
}
#endif
#ifdef RT_USING_DFS_MNTTABLE
#include <dfs_fs.h>
/*@}*/
#ifdef RT_USING_DFS_ROMFS
#include "dfs_romfs.h"
static const struct romfs_dirent _mountpoint_root[] =
{
{ROMFS_DIRENT_DIR, "ram", RT_NULL, 0},
{ROMFS_DIRENT_DIR, "data", RT_NULL, 0},
{ROMFS_DIRENT_DIR, "rodata", RT_NULL, 0},
{ROMFS_DIRENT_DIR, "sdcard", RT_NULL, 0},
{ROMFS_DIRENT_DIR, "udisk", RT_NULL, 0},
};
const struct romfs_dirent romfs_root =
{
ROMFS_DIRENT_DIR, "/", (rt_uint8_t *)_mountpoint_root, ARRAY_SIZE(_mountpoint_root)
};
#endif
const struct dfs_mount_tbl mount_table[] = {
#ifdef RT_USING_DFS_ROMFS
{RT_NULL, "/", "rom", 0, &romfs_root, 0},
#endif
#ifdef LPKG_RAMDISK_TYPE_INITDATA
{"ramdisk0", "/ram", "elm", 0, 0, 0},
#endif
#ifndef AIC_AB_SYSTEM_INTERFACE
#if (defined(AIC_USING_FS_IMAGE_TYPE_FATFS_FOR_0) || defined(AIC_USING_FS_IMAGE_TYPE_FATFS_FOR_1))
{"blk_rodata", "/rodata", "elm", 0, 0, 0},
#endif
#endif
#ifdef LPKG_USING_LITTLEFS
{"data", "/data", "lfs", 0, 0, 0},
#endif
#ifdef LPKG_USING_DFS_UFFS
{"data", "/data", "uffs", 0, 0, 1},
#endif
#ifdef AIC_USING_SDMC1
{"sd0p0", "/sdcard", "elm", 0, 0, 0},
{"sd0", "/sdcard", "elm", 0, 0, 0},
#endif
#if (defined(AIC_USING_USB0_HOST) || defined(AIC_USING_USB0_OTG) || defined(AIC_USING_USB1_HOST))
{"udisk", "/udisk", "elm", 0, 0, 0xFF},
#endif
{0}
};
#endif

20
target/g73x/scan/include/board.h Normal file
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@@ -0,0 +1,20 @@
/*
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: weilin.peng@artinchip.com
*/
#ifndef __AIC_BOARD_H__
#define __AIC_BOARD_H__
#include <rtconfig.h>
#if defined(KERNEL_RTTHREAD)
#elif defined(KERNEL_FREERTOS)
#elif defined(KERNEL_BAREMETAL)
void aic_hw_board_init(void);
#endif
#endif /* __AIC_BOARD_H__ */

13
target/g73x/scan/pack/env.txt Normal file
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@@ -0,0 +1,13 @@
osAB_next=A
osAB_now=A
rodataAB_next=A
rodataAB_now=A
dataAB_next=A
dataAB_now=A
upgrade_available=0
bootlimit=5
bootcount=0
rodata_partname=blk_rodata
rodata_partname_r=blk_rodata_r
data_partname=blk_data
data_partname_r=blk_data_r

85
target/g73x/scan/pack/image_cfg.json Normal file
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@@ -0,0 +1,85 @@
{
"spi-nor": { // Device, The name should be the same with string in image:info:media:type
"size": "2m", // Size of SPI NOR
"partitions": {
"spl": { "size": "256k" },
"env": { "size": "128k" },
"os": { "size": "1m" },
},
},
"image": {
"info": { // Header information about image
"platform": "g73x",
"product": "scan",
"version": "1.0.0",
"media": {
"type": "spi-nor",
"device_id": 0,
}
},
"updater": { // Image writer which is downloaded to RAM by USB
"spl": {
"file": "bootloader.aic",
"attr": ["required", "run"],
"ram": "0x30100000"
},
},
"target": { // Image components which will be burn to device's partitions
"spl": {
"file": "bootloader.aic",
"attr": ["mtd", "required"],
"part": ["spl"]
},
"env": {
"file": "env.bin",
"attr": ["mtd", "optional"],
"part": ["env"]
},
"os": {
"file": "g73x_os.itb",
"attr": ["mtd", "required"],
"part": ["os"]
},
},
},
"pre-process": { // Pre-proccess to generate image components from raw data
"aicimage": { // Create aic boot image
"pbp_ext.aic": {
"head_ver": "0x00010001",
"resource": {
"pbp": "g73x.pbp",
"private": "pbp_cfg.bin",
},
// combine to use with loader.aic
"with_ext": "true",
},
"loader.aic": {
"head_ver": "0x00010001",
"loader": {
"file": "bootloader.bin",
"load address": "CONFIG_AIC_BOOTLOADER_LOAD_BASE",
"entry point": "CONFIG_AIC_BOOTLOADER_TEXT_BASE", // 256 byte aic header
},
"resource": {
"private": "pbp_cfg.bin",
},
},
},
"concatenate": { // cat files in order
"bootloader.aic": ["pbp_ext.aic", "loader.aic"],
},
"itb": { // Create itb image from its
"g73x_os.itb": {
"its": "g73x_os.its"
},
},
"uboot_env": { // Create env data from txt
"env.bin": {
"file": "env.txt",
"size": "4096",
"redundant": "enable",
},
},
},
}

7
target/g73x/scan/pack/ota-subimgs.cfg Normal file
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@@ -0,0 +1,7 @@
[image]
size = "";
version = "1.0.0";
[file]
ota_info.bin:file;
g73x_os.itb:os;

249
target/g73x/scan/pack/pbp_cfg.json Normal file
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@@ -0,0 +1,249 @@
{
"psram": {
"cfg0": { //OPI APS3208K 8M PSRAM
"common": {
"clock": "198000000",
"cs0_pins": "0x0",
"cs1_pins": "0x0",
"xspi_ctl": "0x116d",
"xspi_tcr": "0x280011",
"xspi_cfg": "0x01020001",
"xspi_ldo": "0x17", //1.92V
"psram_cfg0": "0x03030303",
"psram_cfg1": "0x00400001",
"xspi_cs0_iocfg1": "0x06060606",
"xspi_cs0_iocfg2": "0x06060606",
"xspi_cs0_iocfg3": "0x36062636",
"xspi_cs0_iocfg4": "0x26",
"xspi_cs1_iocfg1": "0x06060606",
"xspi_cs1_iocfg2": "0x06060606",
"xspi_cs1_iocfg3": "0x36062636",
"xspi_cs1_iocfg4": "0x26",
},
"reset": {
"proto": "0xff000001",
"buf": "0x00ffffff",
},
"getid": {
"proto": "0x40030204",
"id": "0x80c980c9",
"buf": "0xffffffff",
},
"init": {
"proto0": "0xc0000002", //cmd: byte[0]=0xc0; dummy: byte[1]=0x00; addr: byte[2]=0x00; len: byte[3]=0x02;
"buf0": "0x19000000",
"proto1": "0xc0000402",
"buf1": "0x80000000",
"proto2": "0xffffffff",
"buf2": "0xffffffff",
"proto3": "0xffffffff",
"buf3": "0xffffffff",
},
"xip_cfg": {
"wr_proto": "0x80020002",
"wr_buf": "0xffffffff",
"rd_proto": "0x00060003",
"rd_buf": "0xffffffff",
},
"backup": {
"buf0": "0xAA55AA55", // training_value1
"buf1": "0x55AA55AA", // training_value2
"buf2": "0x02080100", //byte0:read_hold (0x02); byte1:write_hold (0x08); byte3:axi_read_first(0x01); byte4: bit mode
"buf3": "0xFFFFFF04",
"buf4": "0xFFFFFF05",
"buf5": "0xFFFFFF06",
"buf6": "0xFFFFFF07",
"buf7": "0xFFFFFF08",
"buf8": "0xFFFFFF09",
"buf9": "0xFFFFFF00",
},
},
"cfg1": { // XCCELA AP12816 16M PSRAM
"common": {
"clock": "198000000",
"cs0_pins": "0x0",
"cs1_pins": "0x0",
"xspi_ctl": "0x116d",
"xspi_tcr": "0x280011",
"xspi_cfg": "0x03000001",
"xspi_ldo": "0x17", //1.92V
"psram_cfg0": "0x03030304", //cmd_lines, addr_lines, data_lines, addr_width
"psram_cfg1": "0x02000001",
"xspi_cs0_iocfg1": "0x06060606",
"xspi_cs0_iocfg2": "0x06060606",
"xspi_cs0_iocfg3": "0x36062636",
"xspi_cs0_iocfg4": "0x26",
"xspi_cs1_iocfg1": "0x06060606",
"xspi_cs1_iocfg2": "0x06060606",
"xspi_cs1_iocfg3": "0x36062636",
"xspi_cs1_iocfg4": "0x26",
},
"reset": {
"proto": "0xff000001",
"buf": "0x00ffffff",
},
"getid": {
"proto": "0x40040104",
"id": "0xdd8ddd8d",
"buf": "0xffffffff",
},
"init": {
"proto0": "0xc0000001", //cmd: byte[0]=0xc0; dummy: byte[1]=0x00; addr: byte[2]=0x00; len: byte[3]=0x02;
"buf0": "0x11000000",
"proto1": "0xc0000401",
"buf1": "0x20000000",
"proto2": "0xc0000801",
"buf2": "0x4c000000",
"proto3": "0xffffffff",
"buf3": "0xffffffff",
},
"xip_cfg": {
"wr_proto": "0x80070002", //cmd: byte[0]=0x80; dummy: byte[1]=0x07; addr: byte[2]=0x08; len: byte[3]=0x02;
"wr_buf": "0xffffffff",
"rd_proto": "0x00070003",
"rd_buf": "0xffffffff",
},
"backup": {
"buf0": "0x5555aaaa",
"buf1": "0xaaaa5555",
"buf2": "0x05050101", //byte0:read_hold; byte1:write_hold; byte3:axi_read_first; byte4:bit mode
"buf3": "0xFFFFFF04",
"buf4": "0xFFFFFF05",
"buf5": "0xFFFFFF06",
"buf6": "0xFFFFFF07",
"buf7": "0xFFFFFF08",
"buf8": "0xFFFFFF09",
"buf9": "0xFFFFFF00",
},
},
"cfg2": { // XCCELA UnilC SCKW18X12816 16M PSRAM
"common": {
"clock": "198000000",
"cs0_pins": "0x0",
"cs1_pins": "0x0",
"xspi_ctl": "0x116d",
"xspi_tcr": "0x280011",
"xspi_cfg": "0x03000001",
"xspi_ldo": "0x17", //1.92V
"psram_cfg0": "0x03030304", //cmd_lines, addr_lines, data_lines, addr_width
"psram_cfg1": "0x02000001",
"xspi_cs0_iocfg1": "0x06060606",
"xspi_cs0_iocfg2": "0x06060606",
"xspi_cs0_iocfg3": "0x36062636",
"xspi_cs0_iocfg4": "0x26",
"xspi_cs1_iocfg1": "0x06060606",
"xspi_cs1_iocfg2": "0x06060606",
"xspi_cs1_iocfg3": "0x36062636",
"xspi_cs1_iocfg4": "0x26",
},
"reset": {
"proto": "0xff000001",
"buf": "0x00ffffff",
},
"getid": {
"proto": "0x40040104",
"id": "0xc59ac59a",
"buf": "0xffffffff",
},
"init": {
"proto0": "0xc0000001", //cmd: byte[0]=0xc0; dummy: byte[1]=0x00; addr: byte[2]=0x00; len: byte[3]=0x02;
"buf0": "0x10000000",
"proto1": "0xc0000401",
"buf1": "0x20000000",
"proto2": "0xc0000801",
"buf2": "0x4c000000",
"proto3": "0xffffffff",
"buf3": "0xffffffff",
},
"xip_cfg": {
"wr_proto": "0x80070002", //cmd: byte[0]=0x80; dummy: byte[1]=0x07; addr: byte[2]=0x08; len: byte[3]=0x02;
"wr_buf": "0xffffffff",
"rd_proto": "0x00070003",
"rd_buf": "0xffffffff",
},
"backup": {
"buf0": "0x5555aaaa",
"buf1": "0xaaaa5555",
"buf2": "0x05050101", //byte0:read_hold; byte1:write_hold; byte3:axi_read_first; byte4:bit mode
"buf3": "0xFFFFFF04",
"buf4": "0xFFFFFF05",
"buf5": "0xFFFFFF06",
"buf6": "0xFFFFFF07",
"buf7": "0xFFFFFF08",
"buf8": "0xFFFFFF09",
"buf9": "0xFFFFFF00",
},
},
},
"system": {
"upgmode": { // Set PIN to enter BROM's upgrading mode
// If set upgmode_pin_cfg_reg to "0", disable bootpin detect in PBP
"upgmode_pin_cfg_reg": "0x18700080", // PINMUX REG, PA0
"upgmode_pin_cfg_val": "0x10321", // PINMUX VAL
"upgmode_pin_input_reg": "0x18700000", // INPUT VAL REG
"upgmode_pin_input_msk": "0x1", // Bit MSK
"upgmode_pin_input_val": "0x0", // Bit VAL
"upgmode_pin_pullup_dly": "500", // us
},
"uart": { // PBP's uart setting
"main": {
"uart_id": "0", // UART0 for log output
"uart_tx_pin_cfg_reg": "0x18700080", // PA0
"uart_tx_pin_cfg_val": "0x035",
"uart_rx_pin_cfg_reg": "0x18700084", // PA1
"uart_rx_pin_cfg_val": "0x035",
// "uart_id": "0", // UART0 for log output
// "uart_tx_pin_cfg_reg": "0x18700E88", // PN2
// "uart_tx_pin_cfg_val": "0x324",
// "uart_rx_pin_cfg_reg": "0x18700E8C", // PN3
// "uart_rx_pin_cfg_val": "0x324",
// "uart_id": "1", // UART1 for log output
// "uart_tx_pin_cfg_reg": "0x18700090", // PA4
// "uart_tx_pin_cfg_val": "0x325",
// "uart_rx_pin_cfg_reg": "0x18700094", // PA5
// "uart_rx_pin_cfg_val": "0x325",
// "uart_id": "3", // UART3 for log output
// "uart_tx_pin_cfg_reg": "0x187004B8", // PE14
// "uart_tx_pin_cfg_val": "0x325",
// "uart_rx_pin_cfg_reg": "0x187004BC", // PE15
// "uart_rx_pin_cfg_val": "0x325",
// "uart_id": "4", // UART4 for log output
// "uart_tx_pin_cfg_reg": "0x18700198", // PB6
// "uart_tx_pin_cfg_val": "0x325",
// "uart_rx_pin_cfg_reg": "0x1870019C", // PB7
// "uart_rx_pin_cfg_val": "0x325",
// "uart_id": "5", // UART5 for log output
// "uart_tx_pin_cfg_reg": "0x18700490", // PE4
// "uart_tx_pin_cfg_val": "0x325",
// "uart_rx_pin_cfg_reg": "0x18700494", // PE5
// "uart_rx_pin_cfg_val": "0x325",
},
},
"jtag": {
"jtag_only": "0", // 1: Boot code stop in PBP after DDR init and jtag init
"main": {
"jtag_id": "0",
"jtag_ms_pin_cfg_reg": "0x187000A8", // PA10
"jtag_ms_pin_cfg_val": "0x338",
"jtag_ck_pin_cfg_reg": "0x187000AC", // PA11
"jtag_ck_pin_cfg_val": "0x338",
// "jtag_ms_pin_cfg_reg": "0x18700280", // PC0
// "jtag_ms_pin_cfg_val": "0x338",
// "jtag_ck_pin_cfg_reg": "0x18700294", // PC5
// "jtag_ck_pin_cfg_val": "0x338",
},
},
},
}

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target/g73x/scan/pinmux.c Normal file
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/*
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: weilin.peng@artinchip.com
*/
#include <aic_core.h>
#include <aic_hal.h>
#include "board.h"
struct aic_pinmux
{
unsigned char func;
unsigned char bias;
unsigned char drive;
char * name;
};
struct aic_pinmux aic_pinmux_config[] = {
#ifdef AIC_USING_UART0
/* uart0 */
{5, PIN_PULL_DIS, 3, "PA.0"},
{5, PIN_PULL_UP, 3, "PA.1"},
#ifdef AIC_DEV_UART0_MODE_RS485
{1, PIN_PULL_DIS, 3, AIC_UART0_PA_RS485_CTL_NAME},
#endif
#endif
#ifdef AIC_USING_UART1
/* uart1 */
{5, PIN_PULL_DIS, 3, "PD.2"},
{5, PIN_PULL_UP, 3, "PD.3"},
#ifdef AIC_DEV_UART1_MODE_RS485
{1, PIN_PULL_DIS, 3, AIC_UART1_PA_RS485_CTL_NAME},
#endif
#endif
#ifdef AIC_USING_UART2
/* uart2 */
#ifdef AIC_DEV_UART2_MODE_RS485
{5, PIN_PULL_DIS, 3, "PD.4"}, // BT_UART2_TX
{5, PIN_PULL_UP, 3, "PD.5"}, // BT_UART2_RX
{1, PIN_PULL_DIS, 3, AIC_UART2_PA_RS485_CTL_NAME},
#else
{8, PIN_PULL_DIS, 3, "PA.2"}, // BT_UART2_CTS
{8, PIN_PULL_DIS, 3, "PA.3"}, // BT_UART2_RTS
{5, PIN_PULL_DIS, 3, "PD.4"}, // BT_UART2_TX
{5, PIN_PULL_UP, 3, "PD.5"}, // BT_UART2_RX
{1, PIN_PULL_DIS, 3, "PD.6"}, // BT_PWR_ON
#endif
#endif
#ifdef AIC_USING_CAN0
/* can0 */
{4, PIN_PULL_DIS, 3, "PA.4"},
{4, PIN_PULL_DIS, 3, "PA.5"},
#endif
#ifdef AIC_USING_AUDIO
#ifdef AIC_AUDIO_DMIC
{4, PIN_PULL_DIS, 3, "PD.16"},
{4, PIN_PULL_DIS, 3, "PD.17"},
#endif
#ifdef AIC_AUDIO_PLAYBACK
{5, PIN_PULL_DIS, 3, "PE.12"},
{1, PIN_PULL_DIS, 3, AIC_AUDIO_PA_ENABLE_GPIO},
#endif
#endif
#ifdef AIC_USING_I2S0
{4, PIN_PULL_DIS, 3, "PD.11"},
{4, PIN_PULL_DIS, 3, "PD.12"},
{4, PIN_PULL_DIS, 3, "PD.13"},
{4, PIN_PULL_DIS, 3, "PD.14"},
{4, PIN_PULL_DIS, 3, "PD.15"},
#endif
#ifdef AIC_USING_RTP
{2, PIN_PULL_DIS, 3, "PA.8"},
{2, PIN_PULL_DIS, 3, "PA.9"},
{2, PIN_PULL_DIS, 3, "PA.10"},
{2, PIN_PULL_DIS, 3, "PA.11"},
#endif
#ifdef AIC_USING_I2C2
{4, PIN_PULL_DIS, 3, "PA.8"}, // SCK
{4, PIN_PULL_DIS, 3, "PA.9"}, // SDA
#endif
#if defined(AIC_USING_QSPI0) && !defined(AIC_SYSCFG_SIP_FLASH_ENABLE)
/* qspi0 */
{2, PIN_PULL_DIS, 3, "PB.0"},
{2, PIN_PULL_DIS, 3, "PB.1"},
{2, PIN_PULL_DIS, 3, "PB.2"},
{2, PIN_PULL_DIS, 3, "PB.3"},
{2, PIN_PULL_DIS, 3, "PB.4"},
{2, PIN_PULL_DIS, 3, "PB.5"},
#endif
#ifdef AIC_USING_QSPI1
/* qspi1 */
{3, PIN_PULL_DIS, 3, "PD.4"},
{3, PIN_PULL_DIS, 3, "PD.5"},
{3, PIN_PULL_DIS, 3, "PD.6"},
{3, PIN_PULL_DIS, 3, "PD.7"},
{3, PIN_PULL_DIS, 3, "PD.8"},
{3, PIN_PULL_DIS, 3, "PD.9"},
#endif
#ifdef AIC_USING_QSPI2
/* qspi2 */
{2, PIN_PULL_DIS, 3, "PE.12"},
{2, PIN_PULL_DIS, 3, "PE.13"},
{2, PIN_PULL_DIS, 3, "PE.14"},
{2, PIN_PULL_DIS, 3, "PE.15"},
{2, PIN_PULL_DIS, 3, "PE.16"},
{2, PIN_PULL_DIS, 3, "PE.17"},
#endif
#ifdef AIC_USING_QSPI3
/* qspi3 */
{2, PIN_PULL_DIS, 3, "PC.8"},
{2, PIN_PULL_DIS, 3, "PC.9"},
{2, PIN_PULL_DIS, 3, "PC.10"},
{2, PIN_PULL_DIS, 3, "PC.11"},
#endif
#ifdef AIC_USING_SDMC0
{2, PIN_PULL_UP, 7, "PB.6"},
{2, PIN_PULL_UP, 7, "PB.7"},
{2, PIN_PULL_UP, 7, "PB.8"},
{2, PIN_PULL_UP, 7, "PB.9"},
{2, PIN_PULL_UP, 7, "PB.10"},
{2, PIN_PULL_UP, 7, "PB.11"},
#endif
#ifdef AIC_USING_SDMC1
{2, PIN_PULL_UP, 3, "PC.0"},
{2, PIN_PULL_UP, 3, "PC.1"},
{2, PIN_PULL_UP, 3, "PC.2"},
{2, PIN_PULL_UP, 3, "PC.3"},
{2, PIN_PULL_UP, 3, "PC.4"},
{2, PIN_PULL_UP, 3, "PC.5"},
{2, PIN_PULL_UP, 3, "PC.6"},
#endif
#ifdef AIC_USING_CAP0
{3, PIN_PULL_UP, 3, "PC.6"},
#endif
#ifdef AIC_USING_CAP1
{3, PIN_PULL_UP, 3, "PC.7"},
#endif
#ifdef AIC_USING_CAP2
{3, PIN_PULL_UP, 3, "PC.8"},
#endif
#ifdef AIC_USING_CAP3
{3, PIN_PULL_UP, 3, "PC.9"},
#endif
#ifdef AIC_USING_CAP4
{3, PIN_PULL_UP, 3, "PC.10"},
#endif
#ifdef AIC_USING_CAP5
{3, PIN_PULL_UP, 3, "PC.11"},
#endif
#ifdef AIC_WIRELESS_LAN
{1, PIN_PULL_DIS, 3, "PD.7"}, // WIFI_PWR_ON
#endif
#ifdef AIC_USING_I2C0
{4, PIN_PULL_DIS, 3, "PD.0"}, // SCK
{4, PIN_PULL_DIS, 3, "PD.1"}, // SDA
#endif
#ifdef AIC_PANEL_ENABLE_GPIO
{1, PIN_PULL_DIS, 3, AIC_PANEL_ENABLE_GPIO},
#endif
#ifdef AIC_PRGB_16BIT_LD
{2, PIN_PULL_DIS, 3, "PD.8"},
{2, PIN_PULL_DIS, 3, "PD.9"},
{2, PIN_PULL_DIS, 3, "PD.10"},
{2, PIN_PULL_DIS, 3, "PD.11"},
{2, PIN_PULL_DIS, 3, "PD.12"},
{2, PIN_PULL_DIS, 3, "PD.13"},
{2, PIN_PULL_DIS, 3, "PD.14"},
{2, PIN_PULL_DIS, 3, "PD.15"},
{2, PIN_PULL_DIS, 3, "PD.16"},
{2, PIN_PULL_DIS, 3, "PD.17"},
{2, PIN_PULL_DIS, 3, "PD.18"},
{2, PIN_PULL_DIS, 3, "PD.19"},
{2, PIN_PULL_DIS, 3, "PD.20"},
{2, PIN_PULL_DIS, 3, "PD.21"},
{2, PIN_PULL_DIS, 3, "PD.22"},
{2, PIN_PULL_DIS, 3, "PD.23"},
{2, PIN_PULL_DIS, 3, "PD.24"},
{2, PIN_PULL_DIS, 3, "PD.25"},
{2, PIN_PULL_DIS, 3, "PD.26"},
{2, PIN_PULL_DIS, 3, "PD.27"},
#endif
#ifdef AIC_USING_DVP
{3, PIN_PULL_DIS, 3, "PE.0"},
{3, PIN_PULL_DIS, 3, "PE.1"},
{3, PIN_PULL_DIS, 3, "PE.2"},
{3, PIN_PULL_DIS, 3, "PE.3"},
{3, PIN_PULL_DIS, 3, "PE.4"},
{3, PIN_PULL_DIS, 3, "PE.5"},
{3, PIN_PULL_DIS, 3, "PE.6"},
{3, PIN_PULL_DIS, 3, "PE.7"},
{3, PIN_PULL_DIS, 3, "PE.8"},
{3, PIN_PULL_DIS, 3, "PE.9"},
{3, PIN_PULL_DIS, 3, "PE.10"},
#endif
#ifdef AIC_LVDS_LINK_0
{3, PIN_PULL_DIS, 3, "PD.18"},
{3, PIN_PULL_DIS, 3, "PD.19"},
{3, PIN_PULL_DIS, 3, "PD.20"},
{3, PIN_PULL_DIS, 3, "PD.21"},
{3, PIN_PULL_DIS, 3, "PD.22"},
{3, PIN_PULL_DIS, 3, "PD.23"},
{3, PIN_PULL_DIS, 3, "PD.24"},
{3, PIN_PULL_DIS, 3, "PD.25"},
{3, PIN_PULL_DIS, 3, "PD.26"},
{3, PIN_PULL_DIS, 3, "PD.27"},
#endif
#ifdef AIC_DISP_MIPI_DSI
{4, PIN_PULL_DIS, 3, "PD.18"},
{4, PIN_PULL_DIS, 3, "PD.19"},
{4, PIN_PULL_DIS, 3, "PD.20"},
{4, PIN_PULL_DIS, 3, "PD.21"},
{4, PIN_PULL_DIS, 3, "PD.22"},
{4, PIN_PULL_DIS, 3, "PD.23"},
{4, PIN_PULL_DIS, 3, "PD.24"},
{4, PIN_PULL_DIS, 3, "PD.25"},
{4, PIN_PULL_DIS, 3, "PD.26"},
{4, PIN_PULL_DIS, 3, "PD.27"},
#endif
#ifdef AIC_USING_GMAC0
/* gmac0 */
{2, PIN_PULL_DIS, 3, "PE.0"},
{2, PIN_PULL_DIS, 3, "PE.1"},
{2, PIN_PULL_DIS, 3, "PE.2"},
{2, PIN_PULL_DIS, 3, "PE.3"},
{2, PIN_PULL_DIS, 3, "PE.4"},
{2, PIN_PULL_DIS, 3, "PE.5"},
{2, PIN_PULL_DIS, 3, "PE.7"},
{2, PIN_PULL_DIS, 3, "PE.8"},
{2, PIN_PULL_DIS, 3, "PE.9"},
/* phy0 reset gpio */
{1, PIN_PULL_DIS, 3, "PE.6"},
#endif
#ifdef AIC_USING_CLK_OUT0
{6, PIN_PULL_DIS, 3, "PD.13"},
#endif
#ifdef AIC_USING_CLK_OUT1
{2, PIN_PULL_DIS, 3, "PE.11"},
#endif
#ifdef AIC_USING_CLK_OUT2
{2, PIN_PULL_DIS, 3, "PE.10"},
#endif
#ifdef AIC_USING_CLK_OUT3
{7, PIN_PULL_DIS, 3, "PC.6"},
#endif
#ifdef AIC_USING_PWM0
{4, PIN_PULL_DIS, 3, "PE.0"},
//{4, PIN_PULL_DIS, 3, "PE.1"},
#endif
#ifdef AIC_USING_PWM1
{3, PIN_PULL_DIS, 3, "PE.11"},
//{3, PIN_PULL_DIS, 3, "PE.12"},
#endif
#ifdef AIC_USING_PWM2
{3, PIN_PULL_DIS, 3, "PE.13"},
//{3, PIN_PULL_DIS, 3, "PE.15"},
#endif
#ifdef AIC_USING_PWM3
{3, PIN_PULL_DIS, 3, "PE.16"},
//{3, PIN_PULL_DIS, 3, "PE.15"},
#endif
#ifdef AIC_USING_EPWM0
{7, PIN_PULL_DIS, 3, "PD.26"},
{7, PIN_PULL_DIS, 3, "PD.27"},
#endif
#ifdef AIC_USING_EPWM1
{7, PIN_PULL_DIS, 3, "PD.24"},
{7, PIN_PULL_DIS, 3, "PD.25"},
#endif
#ifdef AIC_USING_EPWM2
{7, PIN_PULL_DIS, 3, "PD.22"},
{7, PIN_PULL_DIS, 3, "PD.23"},
#endif
#ifdef AIC_USING_EPWM3
{7, PIN_PULL_DIS, 3, "PD.20"},
{7, PIN_PULL_DIS, 3, "PD.21"},
#endif
#ifdef AIC_USING_EPWM4
{7, PIN_PULL_DIS, 3, "PD.18"},
{7, PIN_PULL_DIS, 3, "PD.19"},
#endif
#ifdef AIC_USING_EPWM5
{7, PIN_PULL_DIS, 3, "PD.16"},
{7, PIN_PULL_DIS, 3, "PD.17"},
#endif
#ifdef AIC_USING_EPWM6
{7, PIN_PULL_DIS, 3, "PD.14"},
{7, PIN_PULL_DIS, 3, "PD.15"},
#endif
#ifdef AIC_USING_EPWM7
{7, PIN_PULL_DIS, 3, "PD.12"},
{7, PIN_PULL_DIS, 3, "PD.13"},
#endif
#ifdef AIC_USING_EPWM8
{7, PIN_PULL_DIS, 3, "PD.10"},
{7, PIN_PULL_DIS, 3, "PD.11"},
#endif
#ifdef AIC_USING_EPWM9
{7, PIN_PULL_DIS, 3, "PD.8"},
{7, PIN_PULL_DIS, 3, "PD.9"},
#endif
#ifdef AIC_USING_EPWM10
{7, PIN_PULL_DIS, 3, "PD.2"},
{7, PIN_PULL_DIS, 3, "PD.3"},
#endif
#ifdef AIC_USING_EPWM11
{7, PIN_PULL_DIS, 3, "PD.0"},
{7, PIN_PULL_DIS, 3, "PD.1"},
#endif
#if (defined(AIC_USING_USB0_DEVICE) || defined(AIC_USING_USB0_HOST))
/* usb0 */
{2, PIN_PULL_DIS, 3, "PO.0"}, // USB-DM
{2, PIN_PULL_DIS, 3, "PO.1"}, // USB-DP
{1, PIN_PULL_DIS, 3, "PD.8"}, // USB-ID
#endif
#ifdef AIC_USING_PSADC0
{7, PIN_PULL_DIS, 3, "PA.0"},
#endif
#ifdef AIC_USING_PSADC1
{7, PIN_PULL_DIS, 3, "PA.1"},
#endif
#ifdef AIC_USING_PSADC2
{7, PIN_PULL_DIS, 3, "PA.2"},
#endif
#ifdef AIC_USING_PSADC3
{7, PIN_PULL_DIS, 3, "PA.3"},
#endif
#ifdef AIC_USING_PSADC4
{7, PIN_PULL_DIS, 3, "PA.4"},
#endif
#ifdef AIC_USING_PSADC5
{7, PIN_PULL_DIS, 3, "PA.5"},
#endif
#ifdef AIC_USING_PSADC6
{7, PIN_PULL_DIS, 3, "PA.6"},
#endif
#ifdef AIC_USING_PSADC7
{7, PIN_PULL_DIS, 3, "PA.7"},
#endif
#ifdef AIC_USING_PSADC8
{7, PIN_PULL_DIS, 3, "PA.8"},
#endif
#ifdef AIC_USING_PSADC9
{7, PIN_PULL_DIS, 3, "PA.9"},
#endif
#ifdef AIC_USING_PSADC10
{7, PIN_PULL_DIS, 3, "PA.10"},
#endif
#ifdef AIC_USING_PSADC11
{7, PIN_PULL_DIS, 3, "PA.11"},
#endif
#ifdef AIC_USING_PSADC12
{7, PIN_PULL_DIS, 3, "PA.12"},
#endif
#ifdef AIC_USING_PSADC13
{7, PIN_PULL_DIS, 3, "PA.13"},
#endif
#ifdef AIC_USING_PSADC14
{7, PIN_PULL_DIS, 3, "PA.14"},
#endif
#ifdef AIC_USING_PSADC15
{7, PIN_PULL_DIS, 3, "PA.15"},
#endif
#ifdef AIC_USING_CTP
{1, PIN_PULL_DIS, 3, AIC_TOUCH_PANEL_RST_PIN},
{1, PIN_PULL_DIS, 3, AIC_TOUCH_PANEL_INT_PIN},
#endif
};
void aic_board_pinmux_init(void)
{
uint32_t i = 0;
long pin = 0;
unsigned int g;
unsigned int p;
for (i=0; i<ARRAY_SIZE(aic_pinmux_config); i++) {
pin = hal_gpio_name2pin(aic_pinmux_config[i].name);
if (pin < 0)
continue;
g = GPIO_GROUP(pin);
p = GPIO_GROUP_PIN(pin);
hal_gpio_set_func(g, p, aic_pinmux_config[i].func);
hal_gpio_set_bias_pull(g, p, aic_pinmux_config[i].bias);
hal_gpio_set_drive_strength(g, p, aic_pinmux_config[i].drive);
}
}

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target/g73x/scan/sys_clk.c Normal file
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/*
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: weilin.peng@artinchip.com
*/
#include <aic_core.h>
#include <aic_hal.h>
#include "board.h"
struct aic_sysclk
{
unsigned long freq;
unsigned int clk_id;
unsigned int parent_clk_id;
};
struct aic_sysclk aic_sysclk_config[] = {
{AIC_CLK_PLL_INT0_FREQ, CLK_PLL_INT0, 0}, /* 480000000 */
{AIC_CLK_PLL_INT1_FREQ, CLK_PLL_INT1, 0}, /* 1200000000 */
{AIC_CLK_PLL_FRA0_FREQ, CLK_PLL_FRA0, 0}, /* 792000000 */
{AIC_CLK_PLL_FRA2_FREQ, CLK_PLL_FRA2, 0}, /* 1188000000 */
{AIC_CLK_CPU_FREQ, CLK_CPU, CLK_CPU_SRC1}, /* 480000000 */
{AIC_CLK_AXI0_FREQ, CLK_AXI0, CLK_AXI_AHB_SRC1}, /* 200000000 */
{AIC_CLK_AHB0_FREQ, CLK_AHB0, CLK_AXI_AHB_SRC1}, /* 200000000 */
{AIC_CLK_APB0_FREQ, CLK_APB0, CLK_APB0_SRC1}, /* 100000000 */
// {24000000, CLK_APB1, 0},
#ifdef AIC_USING_CLK_OUT0
{AIC_CLK_OUT0_FREQ, CLK_OUT0, 0},
#endif /* AIC_USING_CLK_OUT0 */
#ifdef AIC_USING_CLK_OUT1
{AIC_CLK_OUT1_FREQ, CLK_OUT1, 0},
#endif /* AIC_USING_CLK_OUT1 */
#ifdef AIC_USING_CLK_OUT2
{AIC_CLK_OUT2_FREQ, CLK_OUT2, 0},
#endif /* AIC_USING_CLK_OUT2 */
#ifdef AIC_USING_CLK_OUT3
{AIC_CLK_OUT3_FREQ, CLK_OUT3, 0},
#endif /* AIC_USING_CLK_OUT3 */
};
/*
* Some Chips may enable USB0 EHCI in Boot ROM,
* it is better to disable USB0 EHCI during boot to avoid some side effect.
*/
static void usb_ehci_disable(void)
{
hal_clk_disable_assertrst(CLK_USBH0);
hal_clk_disable(CLK_USBH0);
}
void aic_board_sysclk_init(void)
{
uint32_t i = 0;
usb_ehci_disable();
for (i=0; i<sizeof(aic_sysclk_config)/sizeof(struct aic_sysclk); i++) {
if (aic_sysclk_config[i].freq == 0)
continue;
/* multi parent clk */
if (aic_sysclk_config[i].parent_clk_id) {
hal_clk_set_freq(aic_sysclk_config[i].parent_clk_id,
aic_sysclk_config[i].freq);
hal_clk_enable(aic_sysclk_config[i].parent_clk_id);
hal_clk_set_parent(aic_sysclk_config[i].clk_id,
aic_sysclk_config[i].parent_clk_id);
} else {
hal_clk_set_freq(aic_sysclk_config[i].clk_id, aic_sysclk_config[i].freq);
hal_clk_enable(aic_sysclk_config[i].clk_id);
}
}
/* Enable sys clk */
hal_clk_enable_deassertrst_iter(CLK_GPIO);
hal_clk_enable_deassertrst_iter(CLK_GTC);
}