wen/luban-lite
1
0
Fork 0
mirror of https://gitee.com/Vancouver2017/luban-lite.git synced 2025-12-17 01:28:54 +00:00
Code Issues Packages Projects Releases Wiki Activity

v1.1.1

Browse Source
This commit is contained in:
刘可亮
2024-10-30 16:50:31 +08:00
parent 0ef85b55da
commit 661e71562d
458 changed files with 46555 additions and 12133 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
target/g73x/scan/pack/env.txt Normal file
View File

@@ -0,0 +1,13 @@
osAB_next=A
osAB_now=A
rodataAB_next=A
rodataAB_now=A
dataAB_next=A
dataAB_now=A
upgrade_available=0
bootlimit=5
bootcount=0
rodata_partname=blk_rodata
rodata_partname_r=blk_rodata_r
data_partname=blk_data
data_partname_r=blk_data_r

85
target/g73x/scan/pack/image_cfg.json Normal file
View File

@@ -0,0 +1,85 @@
{
"spi-nor": { // Device, The name should be the same with string in image:info:media:type
"size": "2m", // Size of SPI NOR
"partitions": {
"spl": { "size": "256k" },
"env": { "size": "128k" },
"os": { "size": "1m" },
},
},
"image": {
"info": { // Header information about image
"platform": "g73x",
"product": "scan",
"version": "1.0.0",
"media": {
"type": "spi-nor",
"device_id": 0,
}
},
"updater": { // Image writer which is downloaded to RAM by USB
"spl": {
"file": "bootloader.aic",
"attr": ["required", "run"],
"ram": "0x30100000"
},
},
"target": { // Image components which will be burn to device's partitions
"spl": {
"file": "bootloader.aic",
"attr": ["mtd", "required"],
"part": ["spl"]
},
"env": {
"file": "env.bin",
"attr": ["mtd", "optional"],
"part": ["env"]
},
"os": {
"file": "g73x_os.itb",
"attr": ["mtd", "required"],
"part": ["os"]
},
},
},
"pre-process": { // Pre-proccess to generate image components from raw data
"aicimage": { // Create aic boot image
"pbp_ext.aic": {
"head_ver": "0x00010001",
"resource": {
"pbp": "g73x.pbp",
"private": "pbp_cfg.bin",
},
// combine to use with loader.aic
"with_ext": "true",
},
"loader.aic": {
"head_ver": "0x00010001",
"loader": {
"file": "bootloader.bin",
"load address": "CONFIG_AIC_BOOTLOADER_LOAD_BASE",
"entry point": "CONFIG_AIC_BOOTLOADER_TEXT_BASE", // 256 byte aic header
},
"resource": {
"private": "pbp_cfg.bin",
},
},
},
"concatenate": { // cat files in order
"bootloader.aic": ["pbp_ext.aic", "loader.aic"],
},
"itb": { // Create itb image from its
"g73x_os.itb": {
"its": "g73x_os.its"
},
},
"uboot_env": { // Create env data from txt
"env.bin": {
"file": "env.txt",
"size": "4096",
"redundant": "enable",
},
},
},
}

7
target/g73x/scan/pack/ota-subimgs.cfg Normal file
View File

@@ -0,0 +1,7 @@
[image]
size = "";
version = "1.0.0";
[file]
ota_info.bin:file;
g73x_os.itb:os;

249
target/g73x/scan/pack/pbp_cfg.json Normal file
View File

@@ -0,0 +1,249 @@
{
"psram": {
"cfg0": { //OPI APS3208K 8M PSRAM
"common": {
"clock": "198000000",
"cs0_pins": "0x0",
"cs1_pins": "0x0",
"xspi_ctl": "0x116d",
"xspi_tcr": "0x280011",
"xspi_cfg": "0x01020001",
"xspi_ldo": "0x17", //1.92V
"psram_cfg0": "0x03030303",
"psram_cfg1": "0x00400001",
"xspi_cs0_iocfg1": "0x06060606",
"xspi_cs0_iocfg2": "0x06060606",
"xspi_cs0_iocfg3": "0x36062636",
"xspi_cs0_iocfg4": "0x26",
"xspi_cs1_iocfg1": "0x06060606",
"xspi_cs1_iocfg2": "0x06060606",
"xspi_cs1_iocfg3": "0x36062636",
"xspi_cs1_iocfg4": "0x26",
},
"reset": {
"proto": "0xff000001",
"buf": "0x00ffffff",
},
"getid": {
"proto": "0x40030204",
"id": "0x80c980c9",
"buf": "0xffffffff",
},
"init": {
"proto0": "0xc0000002", //cmd: byte[0]=0xc0; dummy: byte[1]=0x00; addr: byte[2]=0x00; len: byte[3]=0x02;
"buf0": "0x19000000",
"proto1": "0xc0000402",
"buf1": "0x80000000",
"proto2": "0xffffffff",
"buf2": "0xffffffff",
"proto3": "0xffffffff",
"buf3": "0xffffffff",
},
"xip_cfg": {
"wr_proto": "0x80020002",
"wr_buf": "0xffffffff",
"rd_proto": "0x00060003",
"rd_buf": "0xffffffff",
},
"backup": {
"buf0": "0xAA55AA55", // training_value1
"buf1": "0x55AA55AA", // training_value2
"buf2": "0x02080100", //byte0:read_hold (0x02); byte1:write_hold (0x08); byte3:axi_read_first(0x01); byte4: bit mode
"buf3": "0xFFFFFF04",
"buf4": "0xFFFFFF05",
"buf5": "0xFFFFFF06",
"buf6": "0xFFFFFF07",
"buf7": "0xFFFFFF08",
"buf8": "0xFFFFFF09",
"buf9": "0xFFFFFF00",
},
},
"cfg1": { // XCCELA AP12816 16M PSRAM
"common": {
"clock": "198000000",
"cs0_pins": "0x0",
"cs1_pins": "0x0",
"xspi_ctl": "0x116d",
"xspi_tcr": "0x280011",
"xspi_cfg": "0x03000001",
"xspi_ldo": "0x17", //1.92V
"psram_cfg0": "0x03030304", //cmd_lines, addr_lines, data_lines, addr_width
"psram_cfg1": "0x02000001",
"xspi_cs0_iocfg1": "0x06060606",
"xspi_cs0_iocfg2": "0x06060606",
"xspi_cs0_iocfg3": "0x36062636",
"xspi_cs0_iocfg4": "0x26",
"xspi_cs1_iocfg1": "0x06060606",
"xspi_cs1_iocfg2": "0x06060606",
"xspi_cs1_iocfg3": "0x36062636",
"xspi_cs1_iocfg4": "0x26",
},
"reset": {
"proto": "0xff000001",
"buf": "0x00ffffff",
},
"getid": {
"proto": "0x40040104",
"id": "0xdd8ddd8d",
"buf": "0xffffffff",
},
"init": {
"proto0": "0xc0000001", //cmd: byte[0]=0xc0; dummy: byte[1]=0x00; addr: byte[2]=0x00; len: byte[3]=0x02;
"buf0": "0x11000000",
"proto1": "0xc0000401",
"buf1": "0x20000000",
"proto2": "0xc0000801",
"buf2": "0x4c000000",
"proto3": "0xffffffff",
"buf3": "0xffffffff",
},
"xip_cfg": {
"wr_proto": "0x80070002", //cmd: byte[0]=0x80; dummy: byte[1]=0x07; addr: byte[2]=0x08; len: byte[3]=0x02;
"wr_buf": "0xffffffff",
"rd_proto": "0x00070003",
"rd_buf": "0xffffffff",
},
"backup": {
"buf0": "0x5555aaaa",
"buf1": "0xaaaa5555",
"buf2": "0x05050101", //byte0:read_hold; byte1:write_hold; byte3:axi_read_first; byte4:bit mode
"buf3": "0xFFFFFF04",
"buf4": "0xFFFFFF05",
"buf5": "0xFFFFFF06",
"buf6": "0xFFFFFF07",
"buf7": "0xFFFFFF08",
"buf8": "0xFFFFFF09",
"buf9": "0xFFFFFF00",
},
},
"cfg2": { // XCCELA UnilC SCKW18X12816 16M PSRAM
"common": {
"clock": "198000000",
"cs0_pins": "0x0",
"cs1_pins": "0x0",
"xspi_ctl": "0x116d",
"xspi_tcr": "0x280011",
"xspi_cfg": "0x03000001",
"xspi_ldo": "0x17", //1.92V
"psram_cfg0": "0x03030304", //cmd_lines, addr_lines, data_lines, addr_width
"psram_cfg1": "0x02000001",
"xspi_cs0_iocfg1": "0x06060606",
"xspi_cs0_iocfg2": "0x06060606",
"xspi_cs0_iocfg3": "0x36062636",
"xspi_cs0_iocfg4": "0x26",
"xspi_cs1_iocfg1": "0x06060606",
"xspi_cs1_iocfg2": "0x06060606",
"xspi_cs1_iocfg3": "0x36062636",
"xspi_cs1_iocfg4": "0x26",
},
"reset": {
"proto": "0xff000001",
"buf": "0x00ffffff",
},
"getid": {
"proto": "0x40040104",
"id": "0xc59ac59a",
"buf": "0xffffffff",
},
"init": {
"proto0": "0xc0000001", //cmd: byte[0]=0xc0; dummy: byte[1]=0x00; addr: byte[2]=0x00; len: byte[3]=0x02;
"buf0": "0x10000000",
"proto1": "0xc0000401",
"buf1": "0x20000000",
"proto2": "0xc0000801",
"buf2": "0x4c000000",
"proto3": "0xffffffff",
"buf3": "0xffffffff",
},
"xip_cfg": {
"wr_proto": "0x80070002", //cmd: byte[0]=0x80; dummy: byte[1]=0x07; addr: byte[2]=0x08; len: byte[3]=0x02;
"wr_buf": "0xffffffff",
"rd_proto": "0x00070003",
"rd_buf": "0xffffffff",
},
"backup": {
"buf0": "0x5555aaaa",
"buf1": "0xaaaa5555",
"buf2": "0x05050101", //byte0:read_hold; byte1:write_hold; byte3:axi_read_first; byte4:bit mode
"buf3": "0xFFFFFF04",
"buf4": "0xFFFFFF05",
"buf5": "0xFFFFFF06",
"buf6": "0xFFFFFF07",
"buf7": "0xFFFFFF08",
"buf8": "0xFFFFFF09",
"buf9": "0xFFFFFF00",
},
},
},
"system": {
"upgmode": { // Set PIN to enter BROM's upgrading mode
// If set upgmode_pin_cfg_reg to "0", disable bootpin detect in PBP
"upgmode_pin_cfg_reg": "0x18700080", // PINMUX REG, PA0
"upgmode_pin_cfg_val": "0x10321", // PINMUX VAL
"upgmode_pin_input_reg": "0x18700000", // INPUT VAL REG
"upgmode_pin_input_msk": "0x1", // Bit MSK
"upgmode_pin_input_val": "0x0", // Bit VAL
"upgmode_pin_pullup_dly": "500", // us
},
"uart": { // PBP's uart setting
"main": {
"uart_id": "0", // UART0 for log output
"uart_tx_pin_cfg_reg": "0x18700080", // PA0
"uart_tx_pin_cfg_val": "0x035",
"uart_rx_pin_cfg_reg": "0x18700084", // PA1
"uart_rx_pin_cfg_val": "0x035",
// "uart_id": "0", // UART0 for log output
// "uart_tx_pin_cfg_reg": "0x18700E88", // PN2
// "uart_tx_pin_cfg_val": "0x324",
// "uart_rx_pin_cfg_reg": "0x18700E8C", // PN3
// "uart_rx_pin_cfg_val": "0x324",
// "uart_id": "1", // UART1 for log output
// "uart_tx_pin_cfg_reg": "0x18700090", // PA4
// "uart_tx_pin_cfg_val": "0x325",
// "uart_rx_pin_cfg_reg": "0x18700094", // PA5
// "uart_rx_pin_cfg_val": "0x325",
// "uart_id": "3", // UART3 for log output
// "uart_tx_pin_cfg_reg": "0x187004B8", // PE14
// "uart_tx_pin_cfg_val": "0x325",
// "uart_rx_pin_cfg_reg": "0x187004BC", // PE15
// "uart_rx_pin_cfg_val": "0x325",
// "uart_id": "4", // UART4 for log output
// "uart_tx_pin_cfg_reg": "0x18700198", // PB6
// "uart_tx_pin_cfg_val": "0x325",
// "uart_rx_pin_cfg_reg": "0x1870019C", // PB7
// "uart_rx_pin_cfg_val": "0x325",
// "uart_id": "5", // UART5 for log output
// "uart_tx_pin_cfg_reg": "0x18700490", // PE4
// "uart_tx_pin_cfg_val": "0x325",
// "uart_rx_pin_cfg_reg": "0x18700494", // PE5
// "uart_rx_pin_cfg_val": "0x325",
},
},
"jtag": {
"jtag_only": "0", // 1: Boot code stop in PBP after DDR init and jtag init
"main": {
"jtag_id": "0",
"jtag_ms_pin_cfg_reg": "0x187000A8", // PA10
"jtag_ms_pin_cfg_val": "0x338",
"jtag_ck_pin_cfg_reg": "0x187000AC", // PA11
"jtag_ck_pin_cfg_val": "0x338",
// "jtag_ms_pin_cfg_reg": "0x18700280", // PC0
// "jtag_ms_pin_cfg_val": "0x338",
// "jtag_ck_pin_cfg_reg": "0x18700294", // PC5
// "jtag_ck_pin_cfg_val": "0x338",
},
},
},
}