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V1.0.6

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This commit is contained in:
刘可亮
2024-09-03 11:16:08 +08:00
parent cf270df8d6
commit 803cac77d5
2931 changed files with 614364 additions and 31222 deletions
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20
bsp/artinchip/drv/pm/Kconfig
View File

@@ -5,27 +5,9 @@
menu "PM configure"
depends on AIC_USING_PM
config AIC_PM_POWER_KEY
bool "Enable gpio to sleep/wakeup system"
default n
config AIC_PM_POWER_KEY_GPIO
string "Select sleep/wakeup pin"
default "PD.6"
depends on AIC_PM_POWER_KEY
config AIC_PM_POWER_TOUCH_WAKEUP
bool "Enable touch panel to wakeup system"
default n
config AIC_PM_POWER_TOUCH_TIME_SLEEP
int "Seconds to enter sleep"
default 120
depends on AIC_PM_POWER_TOUCH_WAKEUP
choice
prompt "Select default sleep mode"
default AIC_PM_POWER_DEFAULT_LIGHT_MODE
default AIC_PM_POWER_DEFAULT_DEEP_MODE
config AIC_PM_POWER_DEFAULT_LIGHT_MODE
bool "light sleep mode"

101
bsp/artinchip/drv/pm/drv_pm_v10.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -29,52 +29,6 @@ void aic_pm_enter_idle(void)
void aic_pm_enter_light_sleep(void)
{
rt_base_t level;
level = rt_hw_interrupt_disable();
/* change bus frequency to 24M */
hal_clk_set_parent(CLK_AXI0, CLK_OSC24M);
hal_clk_set_parent(CLK_AHB0, CLK_OSC24M);
hal_clk_set_parent(CLK_APB0, CLK_OSC24M);
/* change cpu frequency to 24M */
hal_clk_set_parent(CLK_CPU, CLK_OSC24M);
/* disable PLL_FRA1: audio pll */
hal_clk_disable(CLK_PLL_FRA1);
/* disable PLL_FRA2: display pll */
hal_clk_disable(CLK_PLL_FRA2);
/* disable PLL_INT0: cpu pll */
hal_clk_disable(CLK_PLL_INT0);
rt_hw_interrupt_enable(level);
/* reset all pins */
//TO DO
while (1)
{
if (wakeup_triggered)
break;
}
/* wakeup flow */
level = rt_hw_interrupt_disable();
/* enable PLL_INT0: cpu pll */
hal_clk_enable(CLK_PLL_INT0);
/* change cpu frequency to pll */
hal_clk_set_parent(CLK_CPU, CLK_CPU_SRC1);
/* change bus frequency to pll */
hal_clk_set_parent(CLK_AXI0, CLK_AXI0_SRC1);
hal_clk_set_parent(CLK_AHB0, CLK_AHB0_SRC1);
hal_clk_set_parent(CLK_APB0, CLK_APB0_SRC1);
/* enable PLL_FRA2: display pll */
hal_clk_enable(CLK_PLL_FRA2);
/* enable PLL_FRA1: audio pll */
hal_clk_enable(CLK_PLL_FRA1);
rt_hw_interrupt_enable(level);
}
void aic_pm_enter_deep_sleep(void)
{
rt_base_t level;
level = rt_hw_interrupt_disable();
/* change bus frequency to 24M */
hal_clk_set_parent(CLK_AXI0, CLK_OSC24M);
hal_clk_set_parent(CLK_AHB0, CLK_OSC24M);
@@ -89,10 +43,45 @@ void aic_pm_enter_deep_sleep(void)
hal_clk_disable(CLK_PLL_INT1);
/* disable PLL_INT0: cpu pll */
hal_clk_disable(CLK_PLL_INT0);
/* reset all pins */
//TO DO
rt_memcpy((void *)AIC_SRAM_BASE, aic_suspend_resume, aic_suspend_resume_size);
__WFI();
/* wakeup flow */
/* enable PLL_INT0: cpu pll */
hal_clk_enable(CLK_PLL_INT0);
/* change cpu frequency to pll */
hal_clk_set_parent(CLK_CPU, CLK_CPU_SRC1);
/* enable PLL_INT1: bus pll */
hal_clk_enable(CLK_PLL_INT1);
/* change bus frequency to pll */
hal_clk_set_parent(CLK_AXI0, CLK_AXI0_SRC1);
hal_clk_set_parent(CLK_AHB0, CLK_AHB0_SRC1);
hal_clk_set_parent(CLK_APB0, CLK_APB0_SRC1);
/* enable PLL_FRA2: display pll */
hal_clk_enable(CLK_PLL_FRA2);
/* enable PLL_FRA1: audio pll */
hal_clk_enable(CLK_PLL_FRA1);
}
void aic_pm_enter_deep_sleep(void)
{
/* change bus frequency to 24M */
hal_clk_set_parent(CLK_AXI0, CLK_OSC24M);
hal_clk_set_parent(CLK_AHB0, CLK_OSC24M);
hal_clk_set_parent(CLK_APB0, CLK_OSC24M);
/* change cpu frequency to 24M */
hal_clk_set_parent(CLK_CPU, CLK_OSC24M);
/* disable PLL_FRA1: audio pll */
hal_clk_disable(CLK_PLL_FRA1);
/* disable PLL_FRA2: display pll */
hal_clk_disable(CLK_PLL_FRA2);
/* disable PLL_INT1: bus pll */
hal_clk_disable(CLK_PLL_INT1);
/* disable PLL_INT0: cpu pll */
hal_clk_disable(CLK_PLL_INT0);
rt_memcpy((void *)AIC_SRAM_BASE, aic_suspend_resume,
aic_suspend_resume_size);
aic_suspend_resume_fn = (void *)AIC_SRAM_BASE;
aicos_icache_invalid();
aicos_dcache_clean_invalid();
@@ -113,10 +102,8 @@ void aic_pm_enter_deep_sleep(void)
hal_clk_enable(CLK_PLL_FRA2);
/* enable PLL_FRA1: audio pll */
hal_clk_enable(CLK_PLL_FRA1);
rt_hw_interrupt_enable(level);
}
static void aic_sleep(struct rt_pm *pm, uint8_t mode)
{
switch (mode)
@@ -134,8 +121,6 @@ static void aic_sleep(struct rt_pm *pm, uint8_t mode)
aic_pm_enter_deep_sleep();
break;
case PM_SLEEP_MODE_STANDBY:
// TO DO DDR selfrefresh
break;
case PM_SLEEP_MODE_SHUTDOWN:
break;
default:
@@ -177,7 +162,10 @@ static void aic_run(struct rt_pm *pm, rt_uint8_t mode)
}
}
/* timeout unit is rt_tick_t, but MTIMECMPH/L unit is HZ, one tick is 4000 counter */
/*
* timeout unit is rt_tick_t, but MTIMECMPH/L unit is HZ,
* one tick is 4000 counter
*/
static void aic_timer_start(struct rt_pm *pm, rt_uint32_t timeout)
{
uint64_t tmp_counter;
@@ -231,7 +219,8 @@ int aic_pm_hw_init(void)
#ifdef AIC_PM_POWER_DEFAULT_LIGHT_MODE
rt_pm_default_set(PM_SLEEP_MODE_LIGHT);
#endif
timer_mask = 1UL << PM_SLEEP_MODE_DEEP;
timer_mask = 3UL << PM_SLEEP_MODE_LIGHT;
/* initialize system pm module */
rt_system_pm_init(&aic_pm_ops, timer_mask, RT_NULL);

22
bsp/artinchip/drv/pm/drv_pm_v11.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -24,9 +24,6 @@ void aic_pm_enter_idle(void)
void aic_pm_enter_light_sleep(void)
{
rt_base_t level;
level = rt_hw_interrupt_disable();
/* change bus frequency to 24M */
hal_clk_set_parent(CLK_AXI0, CLK_OSC24M);
hal_clk_set_parent(CLK_AHB0, CLK_OSC24M);
@@ -37,17 +34,10 @@ void aic_pm_enter_light_sleep(void)
hal_clk_disable(CLK_PLL_FRA2);
/* disable PLL_INT0: cpu pll */
hal_clk_disable(CLK_PLL_INT0);
rt_hw_interrupt_enable(level);
/* reset all pins */
//TO DO
while (1)
{
if (wakeup_triggered)
break;
}
__WFI();
/* wakeup flow */
level = rt_hw_interrupt_disable();
/* enable PLL_INT0: cpu pll */
hal_clk_enable(CLK_PLL_INT0);
/* change cpu frequency to pll */
@@ -57,15 +47,12 @@ void aic_pm_enter_light_sleep(void)
hal_clk_set_parent(CLK_APB0, CLK_APB0_SRC1);
/* enable PLL_FRA2: display pll */
hal_clk_enable(CLK_PLL_FRA2);
rt_hw_interrupt_enable(level);
}
void aic_pm_enter_deep_sleep(void)
{
rt_base_t level;
uint32_t fra0_freq;
level = rt_hw_interrupt_disable();
/* change bus frequency to 24M */
hal_clk_set_parent(CLK_AXI0, CLK_OSC24M);
hal_clk_set_parent(CLK_AHB0, CLK_OSC24M);
@@ -101,7 +88,6 @@ void aic_pm_enter_deep_sleep(void)
hal_clk_set_parent(CLK_APB0, CLK_APB0_SRC1);
/* enable PLL_FRA2: display pll */
hal_clk_enable(CLK_PLL_FRA2);
rt_hw_interrupt_enable(level);
}
@@ -225,7 +211,7 @@ int aic_pm_hw_init(void)
#ifdef AIC_PM_POWER_DEFAULT_LIGHT_MODE
rt_pm_default_set(PM_SLEEP_MODE_LIGHT);
#endif
timer_mask = 1UL << PM_SLEEP_MODE_DEEP;
timer_mask = 3UL << PM_SLEEP_MODE_LIGHT;
/* initialize system pm module */
rt_system_pm_init(&aic_pm_ops, timer_mask, RT_NULL);

6
bsp/artinchip/drv/pm/drv_pm_v12.c
View File

@@ -36,8 +36,8 @@ void aic_pm_enter_idle(void)
#ifndef AIC_USING_SRAM
void aic_ddr_sr_code_on_ddr(void)
{
rt_kprintf("aic_suspend_resume_size: %d\n", aic_suspend_resume_size);
rt_kprintf("__sram_start: %x\n", (uint32_t)&__sram_start);
pr_debug("aic_suspend_resume_size: %d\n", aic_suspend_resume_size);
pr_debug("__sram_start: %x\n", (uint32_t)&__sram_start);
rt_memcpy((void *)&__sram_start, aic_suspend_resume, aic_suspend_resume_size);
aic_suspend_resume_fn = (void *)&__sram_start;
@@ -48,7 +48,7 @@ void aic_ddr_sr_code_on_ddr(void)
#else
void aic_ddr_sr_code_on_sram(void)
{
rt_kprintf("aic_suspend_resume_size: %d\n", aic_suspend_resume_size);
pr_debug("aic_suspend_resume_size: %d\n", aic_suspend_resume_size);
aic_suspend_resume_fn = aic_suspend_resume;
aic_suspend_resume_fn();
}

6
bsp/artinchip/drv/pm/drv_pm_v13.c
View File

@@ -17,6 +17,7 @@
uint64_t sleep_counter;
uint64_t resume_counter;
extern void systemmap_config(void);
extern void sc_save_context_and_suspend();
extern void sc_restore_context_and_resume();
extern u32 sc_restore_context_and_resume_size;
@@ -47,6 +48,11 @@ void aic_pm_enter_deep_sleep(void)
sc_save_context_and_suspend(&save_sc_context);
/* SC power up and resume flow */
/* Since SCSS is powered off during suspend, sysmap must be configure
* after wakeup to ensure that the mailbox's buffer is uncacheable.
*/
systemmap_config();
CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >>
CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos);
/* config CLIC attribute to use vector interrupt */

60
bsp/artinchip/drv/pm/pm_key.c
View File

@@ -1,60 +0,0 @@
/*
* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: dwj <weijie.ding@artinchip.com>
*/
#include <stdio.h>
#include <rtdevice.h>
#include <rtthread.h>
#include <aic_core.h>
#include <aic_drv.h>
#include <string.h>
#include <aic_osal.h>
volatile uint8_t wakeup_triggered;
void pm_key_irq_callback(void *args)
{
rt_uint8_t sleep_mode;
sleep_mode = rt_pm_get_sleep_mode();
if (sleep_mode == PM_SLEEP_MODE_NONE)
{ /* enter sleep */
rt_pm_module_release(PM_POWER_ID, PM_SLEEP_MODE_NONE);
wakeup_triggered = 0;
}
else
{
rt_pm_module_request(PM_POWER_ID, PM_SLEEP_MODE_NONE);
wakeup_triggered = 1;
#ifdef AIC_PM_POWER_TOUCH_WAKEUP
/* touch timer restart */
rt_timer_start(touch_timer);
#endif
}
}
int pm_key_init(void)
{
rt_base_t pin;
unsigned int g, p;
pin = rt_pin_get(AIC_PM_POWER_KEY_GPIO);
g = GPIO_GROUP(pin);
p = GPIO_GROUP_PIN(pin);
hal_gpio_set_drive_strength(g, p, 3);
hal_gpio_set_debounce(g, p, 0xFFF);
rt_pin_mode(pin, PIN_MODE_INPUT_PULLUP);
rt_pin_attach_irq(pin, PIN_IRQ_MODE_FALLING, pm_key_irq_callback, RT_NULL);
rt_pin_irq_enable(pin, PIN_IRQ_ENABLE);
return 0;
}
INIT_DEVICE_EXPORT(pm_key_init);

74
bsp/artinchip/drv/pm/pm_pin.c Normal file
View File

@@ -0,0 +1,74 @@
/*
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: dwj <weijie.ding@artinchip.com>
*/
#include <stdio.h>
#include <rtdevice.h>
#include <rtthread.h>
#include <aic_core.h>
#include <aic_drv.h>
#include <string.h>
#include <aic_osal.h>
extern void Default_Handler(void);
extern void * g_irqvector[MAX_IRQ_ENTRY];
/* A bitmap indicating which pin is the wakeup source */
static uint32_t rt_pm_pin_wakeup_source[GPIO_GROUP_MAX] = {0};
void rt_pm_set_pin_wakeup_source(rt_base_t pin)
{
rt_pm_pin_wakeup_source[pin >> 5] |= (1 << (pin % GPIO_GROUP_SIZE));
}
void rt_pm_clear_pin_wakeup_source(rt_base_t pin)
{
rt_pm_pin_wakeup_source[pin >> 5] &= ~(1 << (pin % GPIO_GROUP_SIZE));
}
void rt_pm_disable_pin_irq_nonwakeup(void)
{
int index, offset;
uint32_t tmp;
/* disable pin irq */
for (index = 0; index < ARRAY_SIZE(rt_pm_pin_wakeup_source); index++)
{
if (rt_pm_pin_wakeup_source[index] == 0)
{
hal_gpio_group_set_irq_en(index, 0);
}
else
{
tmp = rt_pm_pin_wakeup_source[index];
for (offset = 0; offset < GPIO_GROUP_SIZE; offset++)
{
if (!(tmp & 1))
hal_gpio_disable_irq(index, offset);
tmp >>= 1;
}
}
}
}
void rt_pm_resume_pin_irq(void)
{
int index, pin_name, group, pin;
/* Enable pin irq */
for (index = MAX_IRQn; index < MAX_IRQ_ENTRY; index++)
{
if (g_irqvector[index] && g_irqvector[index] != Default_Handler)
{
pin_name = AIC_IRQ_TO_GPIO(index);
group = GPIO_GROUP(pin_name);
pin = GPIO_GROUP_PIN(pin_name);
hal_gpio_enable_irq(group, pin);
}
}
}

52
bsp/artinchip/drv/pm/pm_touch_timer.c
View File

@@ -1,52 +0,0 @@
/*
* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: dwj <weijie.ding@artinchip.com>
*/
#include <stdio.h>
#include <rtdevice.h>
#include <rtthread.h>
#include <aic_core.h>
#include <aic_drv.h>
#include <string.h>
#include <aic_osal.h>
rt_timer_t touch_timer;
static void touch_timer_timeout(void *parameter)
{
rt_uint8_t sleep_mode;
sleep_mode = rt_pm_get_sleep_mode();
if (sleep_mode == PM_SLEEP_MODE_NONE)
{
rt_pm_module_release(PM_POWER_ID, PM_SLEEP_MODE_NONE);
wakeup_triggered = 0;
}
}
int touch_timer_init(void)
{
rt_tick_t timeout;
if (!AIC_PM_POWER_TOUCH_TIME_SLEEP)
timeout = RT_TICK_MAX / 2 - 1;
else
timeout = AIC_PM_POWER_TOUCH_TIME_SLEEP * RT_TICK_PER_SECOND;
touch_timer = rt_timer_create("tp_timer", touch_timer_timeout, RT_NULL,
timeout, RT_TIMER_FLAG_PERIODIC);
if (touch_timer)
rt_timer_start(touch_timer);
return 0;
}
INIT_DEVICE_EXPORT(touch_timer_init);