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刘可亮
2024-09-03 11:16:08 +08:00
parent cf270df8d6
commit 803cac77d5
2931 changed files with 614364 additions and 31222 deletions
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109
target/d21x/demo100-nor/sys_clk.c Normal file
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/*
* Copyright (c) 2022, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: weilin.peng@artinchip.com
*/
#include <aic_core.h>
#include <aic_hal.h>
#include "board.h"
#ifndef AIC_CLK_PLL_INT0_FREQ
#define AIC_CLK_PLL_INT0_FREQ 600000000
#endif
#ifndef AIC_CLK_PLL_INT1_FREQ
#define AIC_CLK_PLL_INT1_FREQ 1200000000
#endif
#ifndef AIC_CLK_PLL_FRA0_FREQ
#define AIC_CLK_PLL_FRA0_FREQ 600000000
#endif
#ifndef AIC_CLK_PLL_FRA1_FREQ
#define AIC_CLK_PLL_FRA1_FREQ 491520000
#endif
#ifndef AIC_CLK_PLL_FRA2_FREQ
#define AIC_CLK_PLL_FRA2_FREQ 840000000
#endif
#ifndef AIC_CLK_CPU_FREQ
#define AIC_CLK_CPU_FREQ 600000000
#endif
#ifndef AIC_CLK_AXI0_FREQ
#define AIC_CLK_AXI0_FREQ 240000000
#endif
#ifndef AIC_CLK_AHB0_FREQ
#define AIC_CLK_AHB0_FREQ 240000000
#endif
#ifndef AIC_CLK_APB0_FREQ
#define AIC_CLK_APB0_FREQ 100000000
#endif
struct aic_sysclk
{
unsigned long freq;
unsigned int clk_id;
unsigned int parent_clk_id;
};
struct aic_sysclk aic_sysclk_config[] = {
{AIC_CLK_PLL_INT0_FREQ, CLK_PLL_INT0, 0}, /* 600000000 */
{AIC_CLK_PLL_INT1_FREQ, CLK_PLL_INT1, 0}, /* 1200000000 */
//{AIC_CLK_PLL_FRA0_FREQ, CLK_PLL_FRA0, 0}, /* ddr2/ddr3 */
{AIC_CLK_PLL_FRA1_FREQ, CLK_PLL_FRA1, 0}, /* 491520000 */
{AIC_CLK_PLL_FRA2_FREQ, CLK_PLL_FRA2, 0}, /* 840000000 */
{AIC_CLK_CPU_FREQ, CLK_CPU, CLK_CPU_SRC1}, /* 600000000 */
{AIC_CLK_AXI0_FREQ, CLK_AXI0, CLK_AXI0_SRC1}, /* 240000000 */
{AIC_CLK_AHB0_FREQ, CLK_AHB0, CLK_AHB0_SRC1}, /* 240000000 */
{AIC_CLK_APB0_FREQ, CLK_APB0, CLK_APB0_SRC1}, /* 100000000 */
// {24000000, CLK_APB1, 0},
#ifdef AIC_USING_CLK_OUT0
{AIC_CLK_OUT0_FREQ, CLK_OUT0, 0},
#endif /* AIC_USING_CLK_OUT0 */
#ifdef AIC_USING_CLK_OUT1
{AIC_CLK_OUT1_FREQ, CLK_OUT1, 0},
#endif /* AIC_USING_CLK_OUT1 */
#ifdef AIC_USING_CLK_OUT2
{AIC_CLK_OUT2_FREQ, CLK_OUT2, 0},
#endif /* AIC_USING_CLK_OUT2 */
#ifdef AIC_USING_CLK_OUT3
{AIC_CLK_OUT3_FREQ, CLK_OUT3, 0},
#endif /* AIC_USING_CLK_OUT3 */
};
/*
* Some Chips may enable USB0 EHCI in Boot ROM,
* it is better to disable USB0 EHCI during boot to avoid some side effect.
*/
static void usb_ehci_disable(void)
{
hal_clk_disable_assertrst(CLK_USBH0);
hal_clk_disable(CLK_USBH0);
}
void aic_board_sysclk_init(void)
{
uint32_t i = 0;
usb_ehci_disable();
for (i=0; i<sizeof(aic_sysclk_config)/sizeof(struct aic_sysclk); i++) {
if (aic_sysclk_config[i].freq == 0)
continue;
/* multi parent clk */
if (aic_sysclk_config[i].parent_clk_id) {
hal_clk_set_freq(aic_sysclk_config[i].parent_clk_id,
aic_sysclk_config[i].freq);
hal_clk_enable(aic_sysclk_config[i].parent_clk_id);
hal_clk_set_parent(aic_sysclk_config[i].clk_id,
aic_sysclk_config[i].parent_clk_id);
} else {
hal_clk_set_freq(aic_sysclk_config[i].clk_id, aic_sysclk_config[i].freq);
hal_clk_enable(aic_sysclk_config[i].clk_id);
}
}
/* Enable sys clk */
hal_clk_enable_deassertrst_iter(CLK_GPIO);
hal_clk_enable_deassertrst_iter(CLK_GTC);
}