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V1.0.6

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刘可亮
2024-09-03 11:16:08 +08:00
parent cf270df8d6
commit 803cac77d5
2931 changed files with 614364 additions and 31222 deletions
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14
target/d21x/demo88-nand/SConscript Normal file
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Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
# add the board drivers.
src = Glob("*.c") + Glob("*.cpp") + Glob("*.S")
LOCAL_CPPPATH = [cwd]
CPPPATH = [cwd + '/include']
group = DefineGroup('Board', src, depend = [''], LOCAL_CPPPATH = LOCAL_CPPPATH, CPPPATH = CPPPATH)
Return('group')

186
target/d21x/demo88-nand/board.c Normal file
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/*
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: weilin.peng@artinchip.com
*/
#include <aic_core.h>
#include "board.h"
extern void aic_board_pinmux_init(void);
extern void aic_board_sysclk_init(void);
#if defined(KERNEL_RTTHREAD)
#include <aic_drv.h>
#include <rthw.h>
#include <rtthread.h>
extern size_t __heap_start;
extern size_t __heap_end;
#ifdef RT_USING_MEMHEAP
extern size_t __dram_cma_heap_start;
extern size_t __dram_cma_heap_end;
struct aic_memheap
{
aic_mem_region_t type;
char * name;
void * begin_addr;
void * end_addr;
struct rt_memheap heap;
struct rt_mutex lock;
};
struct aic_memheap aic_memheaps[] = {
#ifdef AIC_DRAM_CMA_EN
{MEM_DRAM_CMA, "heap_cma", (void *)&__dram_cma_heap_start, (void *)&__dram_cma_heap_end},
#endif
};
void aic_memheap_init(void)
{
rt_ubase_t begin_align;
rt_ubase_t end_align;
int i = 0;
for (i=0; i<sizeof(aic_memheaps)/sizeof(struct aic_memheap); i++) {
begin_align = RT_ALIGN((rt_ubase_t)aic_memheaps[i].begin_addr, RT_ALIGN_SIZE);
end_align = RT_ALIGN_DOWN((rt_ubase_t)aic_memheaps[i].end_addr, RT_ALIGN_SIZE);
RT_ASSERT(end_align > begin_align);
rt_memheap_init(&aic_memheaps[i].heap, aic_memheaps[i].name,
(void *)begin_align, end_align - begin_align);
rt_mutex_init(&aic_memheaps[i].lock, aic_memheaps[i].name, RT_IPC_FLAG_PRIO);
}
}
void *aic_memheap_malloc(int type, size_t size)
{
void *ptr;
int i = 0;
for (i=0; i<sizeof(aic_memheaps)/sizeof(struct aic_memheap); i++) {
if (aic_memheaps[i].type == type)
break;
}
if (i >= sizeof(aic_memheaps)/sizeof(struct aic_memheap))
return NULL;
/* Enter critical zone */
rt_mutex_take(&aic_memheaps[i].lock, RT_WAITING_FOREVER);
/* allocate memory block from system heap */
ptr = rt_memheap_alloc(&aic_memheaps[i].heap, size);
/* Exit critical zone */
rt_mutex_release(&aic_memheaps[i].lock);
return ptr;
}
void aic_memheap_free(int type, void *rmem)
{
int i = 0;
if (rmem == RT_NULL)
return;
for (i=0; i<sizeof(aic_memheaps)/sizeof(struct aic_memheap); i++) {
if (aic_memheaps[i].type == type)
break;
}
if (i >= sizeof(aic_memheaps)/sizeof(struct aic_memheap))
return;
/* Enter critical zone */
rt_mutex_take(&aic_memheaps[i].lock, RT_WAITING_FOREVER);
rt_memheap_free(rmem);
/* Exit critical zone */
rt_mutex_release(&aic_memheaps[i].lock);
}
#endif
/**
* This function will initial smart-evb board.
*/
void rt_hw_board_init(void)
{
#ifdef RT_USING_HEAP
rt_system_heap_init((void *)&__heap_start, (void *)&__heap_end);
#if (!defined(QEMU_RUN) && defined(RT_USING_MEMHEAP))
aic_memheap_init();
#endif
#endif
aic_board_sysclk_init();
aic_board_pinmux_init();
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
}
#elif defined(KERNEL_FREERTOS)
#elif defined(KERNEL_BAREMETAL)
#include <aic_tlsf.h>
void aic_hw_board_init(void)
{
#ifdef TLSF_MEM_HEAP
aic_tlsf_heap_init();
#endif
aic_board_sysclk_init();
aic_board_pinmux_init();
}
#endif
#ifdef RT_USING_DFS_MNTTABLE
#include <dfs_fs.h>
#ifdef RT_USING_DFS_ROMFS
#include "dfs_romfs.h"
static const struct romfs_dirent _mountpoint_root[] =
{
{ROMFS_DIRENT_DIR, "ram", RT_NULL, 0},
{ROMFS_DIRENT_DIR, "data", RT_NULL, 0},
{ROMFS_DIRENT_DIR, "rodata", RT_NULL, 0},
{ROMFS_DIRENT_DIR, "sdcard", RT_NULL, 0},
{ROMFS_DIRENT_DIR, "udisk", RT_NULL, 0},
};
const struct romfs_dirent romfs_root =
{
ROMFS_DIRENT_DIR, "/", (rt_uint8_t *)_mountpoint_root, ARRAY_SIZE(_mountpoint_root)
};
#endif
const struct dfs_mount_tbl mount_table[] = {
#ifdef RT_USING_DFS_ROMFS
{RT_NULL, "/", "rom", 0, &romfs_root, 0},
#endif
#ifdef LPKG_RAMDISK_TYPE_INITDATA
{"ramdisk0", "/ram", "elm", 0, 0, 0},
#endif
#ifndef AIC_AB_SYSTEM_INTERFACE
#if (defined(AIC_USING_FS_IMAGE_TYPE_FATFS_FOR_0) || defined(AIC_USING_FS_IMAGE_TYPE_FATFS_FOR_1))
{"blk_rodata", "/rodata", "elm", 0, 0, 0},
{"blk_data", "/data", "elm", 0, 0, 1},
#endif
#endif
#ifdef LPKG_USING_DFS_UFFS
{"data", "/data", "uffs", 0, 0, 1},
#endif
#ifdef AIC_USING_SDMC1
{"sd0", "/sdcard", "elm", 0, 0, 0},
#endif
#if (defined(AIC_USING_USB0_HOST) || defined(AIC_USING_USB0_OTG) || defined(AIC_USING_USB1_HOST))
{"udisk", "/udisk", "elm", 0, 0, 0xFF},
#endif
{0}
};
#endif

20
target/d21x/demo88-nand/include/board.h Normal file
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/*
* Copyright (c) 2022, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: weilin.peng@artinchip.com
*/
#ifndef __AIC_BOARD_H__
#define __AIC_BOARD_H__
#include <rtconfig.h>
#if defined(KERNEL_RTTHREAD)
#elif defined(KERNEL_FREERTOS)
#elif defined(KERNEL_BAREMETAL)
void aic_hw_board_init(void);
#endif
#endif /* __AIC_BOARD_H__ */

147
target/d21x/demo88-nand/pack/ddr_init.json Normal file
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{
"dram": { // DDR init parameters
"ddr2": {
"type": "0x00000002",
"memsize": "0x04000000",
"freq": "504000000",
"zq": "0x80004b4b",
"odt": "0x00000000",
"para1": "0x000020DA",
"para2": "0x00400000",
"mr0": "0x00000A63",
"mr1": "0x00000040",
"mr2": "0x00000000",
"mr3": "0x00000000",
"mr4": "0x00000000",
"mr5": "0x00000000",
"mr6": "0x00000000",
"tpr0": "0x0048A192",
"tpr1": "0x01C2418D",
"tpr2": "0x00076051",
"tpr3": "0x00000000",
"tpr4": "0x00000000",
"tpr5": "0x00000000",
"tpr6": "0x00000000",
"tpr7": "0x00000000",
"tpr8": "0x09090000",
"tpr9": "0x0a0a0000",
"tpr10": "0x00000000",
"tpr11": "0x00000000",
"tpr12": "0x00000000",
"tpr13": "0x0001FC01",
"tpr14": "0x00000000",
"tpr15": "0x00000000",
"tpr16": "0x00000000",
"tpr17": "0x00000000",
"tpr18": "0x00000000",
},
"ddr3": {
"type": "0x00000003",
"memsize": "0x8000000",
"freq": "672000000",
"zq": "0x80005d5d",
"odt": "0x00000000",
"para1": "0x000030DA",
"para2": "0x02000000",
"mr0": "0x00001C70",
"mr1": "0x00000040",
"mr2": "0x00000018",
"mr3": "0x00000000",
"mr4": "0x00000000",
"mr5": "0x00000400",
"mr6": "0x00000848",
"tpr0": "0x0048A192",
"tpr1": "0x01B1A94B",
"tpr2": "0x00061043",
"tpr3": "0x78787896",
"tpr4": "0x00000000",
"tpr5": "0x00000000",
"tpr6": "0x00000000",
"tpr7": "0x00000000",
"tpr8": "0x06060000",
"tpr9": "0x06060000",
"tpr10": "0x00000000",
"tpr11": "0x00000000",
"tpr12": "0x00000000",
"tpr13": "0x0001FC01",
"tpr14": "0x00000000",
"tpr15": "0x00000000",
"tpr16": "0x00000000",
"tpr17": "0x00000000",
"tpr18": "0x00000000",
},
},
"system": {
"upgmode": { // Set PIN to enter BROM's upgrading mode
// If set upgmode_pin_cfg_reg to "0", disable bootpin detect in PBP
"upgmode_pin_cfg_reg": "0x18700080", // PINMUX REG, PA0
"upgmode_pin_cfg_val": "0x10321", // PINMUX VAL
"upgmode_pin_input_reg": "0x18700000", // INPUT VAL REG
"upgmode_pin_input_msk": "0x1", // Bit MSK
"upgmode_pin_input_val": "0x0", // Bit VAL
"upgmode_pin_pullup_dly": "500", // n * 1us delay, limited to between 500us and 100ms
},
"uart": { // PBP's uart setting, remove uart setting to disable log in PBP
"main": {
"uart_id": "0", // UART0 for log output
"uart_tx_pin_cfg_reg": "0x18700080", // PA0
"uart_tx_pin_cfg_val": "0x325",
"uart_rx_pin_cfg_reg": "0x18700084", // PA1
"uart_rx_pin_cfg_val": "0x325",
// "uart_id": "0", // UART0 for log output
// "uart_tx_pin_cfg_reg": "0x18700E88", // PN2
// "uart_tx_pin_cfg_val": "0x324",
// "uart_rx_pin_cfg_reg": "0x18700E8C", // PN3
// "uart_rx_pin_cfg_val": "0x324",
// "uart_id": "1", // UART1 for log output
// "uart_tx_pin_cfg_reg": "0x18700090", // PA4
// "uart_tx_pin_cfg_val": "0x325",
// "uart_rx_pin_cfg_reg": "0x18700094", // PA5
// "uart_rx_pin_cfg_val": "0x325",
// "uart_id": "3", // UART3 for log output
// "uart_tx_pin_cfg_reg": "0x187004B8", // PE14
// "uart_tx_pin_cfg_val": "0x325",
// "uart_rx_pin_cfg_reg": "0x187004BC", // PE15
// "uart_rx_pin_cfg_val": "0x325",
// "uart_id": "4", // UART4 for log output
// "uart_tx_pin_cfg_reg": "0x18700198", // PB6
// "uart_tx_pin_cfg_val": "0x325",
// "uart_rx_pin_cfg_reg": "0x1870019C", // PB7
// "uart_rx_pin_cfg_val": "0x325",
// "uart_id": "5", // UART5 for log output
// "uart_tx_pin_cfg_reg": "0x18700490", // PE4
// "uart_tx_pin_cfg_val": "0x325",
// "uart_rx_pin_cfg_reg": "0x18700494", // PE5
// "uart_rx_pin_cfg_val": "0x325",
},
},
"jtag": {
"jtag_only": "0", // 1: Boot code stop in PBP after DDR init and jtag init
"main": {
"jtag_id": "0",
"jtag_do_pin_cfg_reg": "0x187000A0", // PA8
"jtag_do_pin_cfg_val": "0x336",
"jtag_di_pin_cfg_reg": "0x187000A4", // PA9
"jtag_di_pin_cfg_val": "0x336",
"jtag_ms_pin_cfg_reg": "0x187000A8", // PA10
"jtag_ms_pin_cfg_val": "0x336",
"jtag_ck_pin_cfg_reg": "0x187000AC", // PA11
"jtag_ck_pin_cfg_val": "0x336",
// "jtag_do_pin_cfg_reg": "0x1870028C", // PC3
// "jtag_do_pin_cfg_val": "0x336",
// "jtag_di_pin_cfg_reg": "0x18700284", // PC1
// "jtag_di_pin_cfg_val": "0x336",
// "jtag_ms_pin_cfg_reg": "0x18700280", // PC0
// "jtag_ms_pin_cfg_val": "0x336",
// "jtag_ck_pin_cfg_reg": "0x18700294", // PC5
// "jtag_ck_pin_cfg_val": "0x336",
},
},
},
}

13
target/d21x/demo88-nand/pack/env.txt Normal file
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osAB_next=A
osAB_now=A
rodataAB_next=A
rodataAB_now=A
dataAB_next=A
dataAB_now=A
upgrade_available=0
bootlimit=5
bootcount=0
rodata_partname=blk_rodata
rodata_partname_r=blk_rodata_r
data_partname=blk_data
data_partname_r=blk_data_r

126
target/d21x/demo88-nand/pack/image_cfg.json Normal file
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{
"spi-nand": { // Device, The name should be the same with string in image:info:media:type
"size": "128m", // Size of SPI NAND
"partitions": {
"spl": { "size": "1m" },
"env": { "size": "256k" },
"env_r": { "size": "256k" },
"os": { "size": "4m" },
"os_r": { "size": "4m" },
"rodata": { "size": "12m" },
"rodata_r": { "size": "12m" },
"data": {
"size": "40m",
"nftl": { // Volume in NFTL device
"data": { "size": "-" },
},
},
"data_r": {
"size": "40m",
"nftl": { // Volume in NFTL device
"data": { "size": "-" },
},
},
},
},
"image": {
"info": { // Header information about image
"platform": "d21x",
"product": "demo88_nand",
"version": "1.0.0",
"media": {
"type": "spi-nand",
"device_id": 0,
"array_organization": [
{ "page": "2k", "block": "128k", "oob": "64" },
// { "page": "4k", "block": "256k", "oob": "128" },
],
}
},
"updater": { // Image writer which is downloaded to RAM by USB
"ddr": {
"file": "usbupg-ddr-init.aic",
"attr": ["required", "run"],
"ram": "0x00103000"
},
"spl": {
"file": "bootloader.aic",
"attr": ["required", "run"],
"ram": "0x41000000"
},
},
"target": { // Image components which will be burn to device's partitions
"spl": {
"file": "bootloader.aic",
"attr": ["mtd", "required"],
"part": ["spl"]
},
"env": {
"file": "env.bin",
"attr": ["mtd", "optional"],
"part": ["env","env_r"]
},
"os": {
"file": "d21x_os.itb",
"attr": ["mtd", "required"],
"part": ["os"]
},
"rodata": {
"file": "rodata.fatfs",
"attr": ["mtd", "optional"],
"part": ["rodata"]
},
"data": {
"file": "data.fatfs",
"attr": ["block", "optional"],
"part": ["data"]
},
},
},
"pre-process": { // Pre-proccess to generate image components from raw data
"aicimage": { // Create aic boot image
"usbupg-ddr-init.aic": { // No loader, only PreBootProgram to initialize DDR
"head_ver": "0x00010001",
"resource": {
"private": "ddr_init.bin",
"pbp": "d21x.pbp",
},
},
"pbp_ext.aic": {
"head_ver": "0x00010001",
"resource": {
"pbp": "d21x.pbp",
"private": "ddr_init.bin",
},
// combine to use with loader.aic
"with_ext": "true",
},
"loader.aic": {
"head_ver": "0x00010001",
"loader": {
"file": "bootloader.bin",
"load address": "0x40200000",
"entry point": "0x40200100", // 256 byte aic header
},
"resource": {
"private": "ddr_init.bin",
},
},
},
"concatenate": { // cat files in order
"bootloader.aic": ["pbp_ext.aic", "loader.aic"],
},
"uboot_env": { // Create env data from txt
"env.bin": {
"file": "env.txt",
"size": "4096",
"redundant": "enable",
},
},
"itb": { // Create itb image from its
"d21x_os.itb": {
"its": "d21x_os.its"
},
},
},
}

9
target/d21x/demo88-nand/pack/ota-subimgs.cfg Normal file
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[image]
size = "";
version = "1.0.0";
[file]
ota_info.bin:file;
d21x_os.itb:os;
rodata.fatfs:rodata;
data.fatfs:blk_data;

412
target/d21x/demo88-nand/pinmux.c Normal file
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/*
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: weilin.peng@artinchip.com
*/
#include <aic_core.h>
#include <aic_hal.h>
#include "board.h"
#include <libfdt.h>
#include <of.h>
#include <aic_utils.h>
extern size_t __dtb_pos_f;
struct aic_pinmux
{
unsigned char func;
unsigned char bias;
unsigned char drive;
char * name;
};
struct aic_pinmux aic_pinmux_config[] = {
#ifdef AIC_USING_UART0
/* uart0 */
{5, PIN_PULL_DIS, 3, "PA.0"},
{5, PIN_PULL_UP, 3, "PA.1"},
#endif
#ifdef AIC_USING_UART1
/* uart1 */
{5, PIN_PULL_DIS, 3, "PA.4"},
{5, PIN_PULL_UP, 3, "PA.5"},
#endif
#ifdef AIC_USING_UART2
/* uart2 */
{5, PIN_PULL_DIS, 3, "PA.8"},
{5, PIN_PULL_UP, 3, "PA.9"},
#endif
#ifdef AIC_USING_SDMC0
{2, PIN_PULL_UP, 3, "PB.0"},
{2, PIN_PULL_UP, 3, "PB.1"},
{2, PIN_PULL_UP, 3, "PB.2"},
{2, PIN_PULL_UP, 3, "PB.3"},
{2, PIN_PULL_UP, 3, "PB.4"},
{2, PIN_PULL_UP, 3, "PB.5"},
{2, PIN_PULL_UP, 3, "PB.6"},
{2, PIN_PULL_UP, 3, "PB.7"},
{2, PIN_PULL_UP, 3, "PB.8"},
{2, PIN_PULL_UP, 3, "PB.9"},
{2, PIN_PULL_UP, 3, "PB.10"},
{2, PIN_PULL_UP, 3, "PB.11"},
#endif
#ifdef AIC_USING_SDMC1
{2, PIN_PULL_UP, 3, "PC.0"},
{2, PIN_PULL_UP, 3, "PC.1"},
{2, PIN_PULL_UP, 3, "PC.2"},
{2, PIN_PULL_UP, 3, "PC.3"},
{2, PIN_PULL_UP, 3, "PC.4"},
{2, PIN_PULL_UP, 3, "PC.5"},
{2, PIN_PULL_UP, 3, "PC.6"},
#endif
#ifdef AIC_USING_SDMC2
{2, PIN_PULL_UP, 3, "PF.0"},
{2, PIN_PULL_UP, 3, "PF.1"},
{2, PIN_PULL_UP, 3, "PF.2"},
{2, PIN_PULL_UP, 3, "PF.3"},
{2, PIN_PULL_UP, 3, "PF.4"},
{2, PIN_PULL_UP, 3, "PF.5"},
#endif
#ifdef AIC_USING_I2C0
{4, PIN_PULL_DIS, 3, "PD.6"}, // SCK
{4, PIN_PULL_DIS, 3, "PD.7"}, // SDA
#endif
#ifdef AIC_USING_I2C1
{5, PIN_PULL_DIS, 3, "PD.18"}, // SCK
{5, PIN_PULL_DIS, 3, "PD.19"}, // SDA
#endif
#ifdef AIC_USING_I2C2
{4, PIN_PULL_DIS, 3, "PA.8"}, // SCK
{4, PIN_PULL_DIS, 3, "PA.9"}, // SDA
#endif
#ifdef AIC_USING_I2C3
{4, PIN_PULL_DIS, 3, "PA.10"}, // SCK
{4, PIN_PULL_DIS, 3, "PA.11"}, // SDA
#endif
#if defined(AIC_USING_QSPI0) && !defined(AIC_SYSCFG_SIP_FLASH_ENABLE)
/* qspi0 */
{3, PIN_PULL_DIS, 3, "PB.0"},
{3, PIN_PULL_DIS, 3, "PB.1"},
{3, PIN_PULL_DIS, 3, "PB.2"},
{3, PIN_PULL_DIS, 3, "PB.3"},
{3, PIN_PULL_DIS, 3, "PB.4"},
{3, PIN_PULL_DIS, 3, "PB.5"},
#endif
#ifdef AIC_PRGB_24BIT
{2, PIN_PULL_DIS, 3, "PD.0"},
{2, PIN_PULL_DIS, 3, "PD.1"},
{2, PIN_PULL_DIS, 3, "PD.2"},
{2, PIN_PULL_DIS, 3, "PD.3"},
{2, PIN_PULL_DIS, 3, "PD.4"},
{2, PIN_PULL_DIS, 3, "PD.5"},
{2, PIN_PULL_DIS, 3, "PD.6"},
{2, PIN_PULL_DIS, 3, "PD.7"},
{2, PIN_PULL_DIS, 3, "PD.8"},
{2, PIN_PULL_DIS, 3, "PD.9"},
{2, PIN_PULL_DIS, 3, "PD.10"},
{2, PIN_PULL_DIS, 3, "PD.11"},
{2, PIN_PULL_DIS, 3, "PD.12"},
{2, PIN_PULL_DIS, 3, "PD.13"},
{2, PIN_PULL_DIS, 3, "PD.14"},
{2, PIN_PULL_DIS, 3, "PD.15"},
{2, PIN_PULL_DIS, 3, "PD.16"},
{2, PIN_PULL_DIS, 3, "PD.17"},
{2, PIN_PULL_DIS, 3, "PD.18"},
{2, PIN_PULL_DIS, 3, "PD.19"},
{2, PIN_PULL_DIS, 3, "PD.20"},
{2, PIN_PULL_DIS, 3, "PD.21"},
{2, PIN_PULL_DIS, 3, "PD.22"},
{2, PIN_PULL_DIS, 3, "PD.23"},
{2, PIN_PULL_DIS, 3, "PD.24"},
{2, PIN_PULL_DIS, 3, "PD.25"},
{2, PIN_PULL_DIS, 3, "PD.26"},
{2, PIN_PULL_DIS, 3, "PD.27"},
#endif
#if defined(AIC_PRGB_18BIT_LD)
{2, PIN_PULL_DIS, 3, "PD.6"},
{2, PIN_PULL_DIS, 3, "PD.7"},
#endif
#if defined(AIC_PRGB_16BIT_LD) || defined(AIC_PRGB_18BIT_LD)
{2, PIN_PULL_DIS, 3, "PD.8"},
{2, PIN_PULL_DIS, 3, "PD.9"},
{2, PIN_PULL_DIS, 3, "PD.10"},
{2, PIN_PULL_DIS, 3, "PD.11"},
{2, PIN_PULL_DIS, 3, "PD.12"},
{2, PIN_PULL_DIS, 3, "PD.13"},
{2, PIN_PULL_DIS, 3, "PD.14"},
{2, PIN_PULL_DIS, 3, "PD.15"},
{2, PIN_PULL_DIS, 3, "PD.16"},
{2, PIN_PULL_DIS, 3, "PD.17"},
{2, PIN_PULL_DIS, 3, "PD.18"},
{2, PIN_PULL_DIS, 3, "PD.19"},
{2, PIN_PULL_DIS, 3, "PD.20"},
{2, PIN_PULL_DIS, 3, "PD.21"},
{2, PIN_PULL_DIS, 3, "PD.22"},
{2, PIN_PULL_DIS, 3, "PD.23"},
{2, PIN_PULL_DIS, 3, "PD.24"},
{2, PIN_PULL_DIS, 3, "PD.25"},
{2, PIN_PULL_DIS, 3, "PD.26"},
{2, PIN_PULL_DIS, 3, "PD.27"},
#endif
#if defined(AIC_PRGB_18BIT_HD)
{2, PIN_PULL_DIS, 3, "PD.16"},
{2, PIN_PULL_DIS, 3, "PD.17"},
#endif
#if defined(AIC_PRGB_16BIT_HD) || defined(AIC_PRGB_18BIT_HD)
{2, PIN_PULL_DIS, 3, "PD.0"},
{2, PIN_PULL_DIS, 3, "PD.1"},
{2, PIN_PULL_DIS, 3, "PD.2"},
{2, PIN_PULL_DIS, 3, "PD.3"},
{2, PIN_PULL_DIS, 3, "PD.4"},
{2, PIN_PULL_DIS, 3, "PD.5"},
{2, PIN_PULL_DIS, 3, "PD.6"},
{2, PIN_PULL_DIS, 3, "PD.7"},
{2, PIN_PULL_DIS, 3, "PD.8"},
{2, PIN_PULL_DIS, 3, "PD.9"},
{2, PIN_PULL_DIS, 3, "PD.10"},
{2, PIN_PULL_DIS, 3, "PD.11"},
{2, PIN_PULL_DIS, 3, "PD.12"},
{2, PIN_PULL_DIS, 3, "PD.13"},
{2, PIN_PULL_DIS, 3, "PD.14"},
{2, PIN_PULL_DIS, 3, "PD.15"},
{2, PIN_PULL_DIS, 3, "PD.24"},
{2, PIN_PULL_DIS, 3, "PD.25"},
{2, PIN_PULL_DIS, 3, "PD.26"},
{2, PIN_PULL_DIS, 3, "PD.27"},
#endif
#ifdef AIC_LVDS_LINK_1
{3, PIN_PULL_DIS, 3, "PD.8"},
{3, PIN_PULL_DIS, 3, "PD.9"},
{3, PIN_PULL_DIS, 3, "PD.10"},
{3, PIN_PULL_DIS, 3, "PD.11"},
{3, PIN_PULL_DIS, 3, "PD.12"},
{3, PIN_PULL_DIS, 3, "PD.13"},
{3, PIN_PULL_DIS, 3, "PD.14"},
{3, PIN_PULL_DIS, 3, "PD.15"},
{3, PIN_PULL_DIS, 3, "PD.16"},
{3, PIN_PULL_DIS, 3, "PD.17"},
#endif
#ifdef AIC_LVDS_LINK_0
{3, PIN_PULL_DIS, 3, "PD.18"},
{3, PIN_PULL_DIS, 3, "PD.19"},
{3, PIN_PULL_DIS, 3, "PD.20"},
{3, PIN_PULL_DIS, 3, "PD.21"},
{3, PIN_PULL_DIS, 3, "PD.22"},
{3, PIN_PULL_DIS, 3, "PD.23"},
{3, PIN_PULL_DIS, 3, "PD.24"},
{3, PIN_PULL_DIS, 3, "PD.25"},
{3, PIN_PULL_DIS, 3, "PD.26"},
{3, PIN_PULL_DIS, 3, "PD.27"},
#endif
#if defined(AIC_LVDS_DOUBLE_SCREEN) || defined(AIC_LVDS_DUAL_LINK)
{3, PIN_PULL_DIS, 3, "PD.8"},
{3, PIN_PULL_DIS, 3, "PD.9"},
{3, PIN_PULL_DIS, 3, "PD.10"},
{3, PIN_PULL_DIS, 3, "PD.11"},
{3, PIN_PULL_DIS, 3, "PD.12"},
{3, PIN_PULL_DIS, 3, "PD.13"},
{3, PIN_PULL_DIS, 3, "PD.14"},
{3, PIN_PULL_DIS, 3, "PD.15"},
{3, PIN_PULL_DIS, 3, "PD.16"},
{3, PIN_PULL_DIS, 3, "PD.17"},
{3, PIN_PULL_DIS, 3, "PD.18"},
{3, PIN_PULL_DIS, 3, "PD.19"},
{3, PIN_PULL_DIS, 3, "PD.20"},
{3, PIN_PULL_DIS, 3, "PD.21"},
{3, PIN_PULL_DIS, 3, "PD.22"},
{3, PIN_PULL_DIS, 3, "PD.23"},
{3, PIN_PULL_DIS, 3, "PD.24"},
{3, PIN_PULL_DIS, 3, "PD.25"},
{3, PIN_PULL_DIS, 3, "PD.26"},
{3, PIN_PULL_DIS, 3, "PD.27"},
#endif
#ifdef AIC_PANEL_ENABLE_GPIO
{1, PIN_PULL_DIS, 3, AIC_PANEL_ENABLE_GPIO},
#endif
#if (defined(AIC_USING_USB0_DEVICE) || defined(AIC_USING_USB0_HOST))
/* usb0 */
{2, PIN_PULL_DIS, 3, "PO.0"},
{2, PIN_PULL_DIS, 3, "PO.1"},
#endif
#ifdef AIC_USING_GMAC0
/* gmac0 */
{6, PIN_PULL_DIS, 3, "PE.0"},
{6, PIN_PULL_DIS, 3, "PE.1"},
{6, PIN_PULL_DIS, 3, "PE.2"},
{6, PIN_PULL_DIS, 3, "PE.3"},
{6, PIN_PULL_DIS, 3, "PE.4"},
{6, PIN_PULL_DIS, 3, "PE.5"},
{6, PIN_PULL_DIS, 3, "PE.7"},
{6, PIN_PULL_DIS, 3, "PE.8"},
{6, PIN_PULL_DIS, 3, "PE.9"},
/* phy0 reset gpio */
{1, PIN_PULL_DIS, 3, "PE.6"},
#endif
#ifdef AIC_USING_CLK_OUT0
{6, PIN_PULL_DIS, 3, "PD.21"},
#endif
#ifdef AIC_USING_CLK_OUT1
{5, PIN_PULL_DIS, 3, "PE.11"},
#endif
#ifdef AIC_USING_CLK_OUT2
{6, PIN_PULL_DIS, 3, "PE.10"},
#endif
#ifdef AIC_USING_CLK_OUT3
{6, PIN_PULL_DIS, 3, "PF.10"},
#endif
#ifdef AIC_USING_DVP
{3, PIN_PULL_DIS, 3, "PE.0"},
{3, PIN_PULL_DIS, 3, "PE.1"},
{3, PIN_PULL_DIS, 3, "PE.2"},
{3, PIN_PULL_DIS, 3, "PE.3"},
{3, PIN_PULL_DIS, 3, "PE.4"},
{3, PIN_PULL_DIS, 3, "PE.5"},
{3, PIN_PULL_DIS, 3, "PE.6"},
{3, PIN_PULL_DIS, 3, "PE.7"},
{3, PIN_PULL_DIS, 3, "PE.8"},
{3, PIN_PULL_DIS, 3, "PE.9"},
{3, PIN_PULL_DIS, 3, "PE.10"},
#endif
#ifdef AIC_USING_PWM0
{7, PIN_PULL_DIS, 3, "PC.0"},
{7, PIN_PULL_DIS, 3, "PC.1"},
#endif
#ifdef AIC_USING_PWM1
{7, PIN_PULL_DIS, 3, "PC.2"},
{7, PIN_PULL_DIS, 3, "PC.3"},
#endif
#ifdef AIC_USING_PWM2
{7, PIN_PULL_DIS, 3, "PC.4"},
{7, PIN_PULL_DIS, 3, "PC.5"},
#endif
#ifdef AIC_USING_PWM3
{5, PIN_PULL_DIS, 3, "PE.18"},
{5, PIN_PULL_DIS, 3, "PE.19"},
#endif
#ifdef AIC_USING_CAP0
{8, PIN_PULL_DIS, 3, "PE.6"},
#endif
#ifdef AIC_USING_CAP1
{8, PIN_PULL_DIS, 3, "PE.7"},
#endif
#ifdef AIC_USING_CAP2
{8, PIN_PULL_DIS, 3, "PE.8"},
#endif
#ifdef AIC_USING_GPAI0
{2, PIN_PULL_DIS, 3, "PA.0"},
#endif
#ifdef AIC_USING_GPAI1
{2, PIN_PULL_DIS, 3, "PA.1"},
#endif
#ifdef AIC_USING_GPAI2
{2, PIN_PULL_DIS, 3, "PA.2"},
#endif
#ifdef AIC_USING_GPAI7
{2, PIN_PULL_DIS, 3, "PA.7"},
#endif
#ifdef AIC_USING_AUDIO
#ifdef AIC_AUDIO_PLAYBACK
{4, PIN_PULL_DIS, 3, "PE.11"},
{1, PIN_PULL_DIS, 3, AIC_AUDIO_PA_ENABLE_GPIO},
#endif
#ifdef AIC_AUDIO_DMIC
{4, PIN_PULL_DIS, 3, "PF.14"},
{4, PIN_PULL_DIS, 3, "PF.15"},
#endif
#endif
#ifdef AIC_USING_RTP
{2, PIN_PULL_DIS, 3, "PA.8"},
{2, PIN_PULL_DIS, 3, "PA.9"},
{2, PIN_PULL_DIS, 3, "PA.10"},
{2, PIN_PULL_DIS, 3, "PA.11"},
#endif
#ifdef AIC_USING_PSADC0
{3, PIN_PULL_DIS, 3, "PA.0"},
#endif
#ifdef AIC_USING_PSADC1
{3, PIN_PULL_DIS, 3, "PA.1"},
#endif
#ifdef AIC_USING_PSADC2
{3, PIN_PULL_DIS, 3, "PA.2"},
#endif
#ifdef AIC_USING_PSADC3
{3, PIN_PULL_DIS, 3, "PA.3"},
#endif
#ifdef AIC_USING_PSADC4
{3, PIN_PULL_DIS, 3, "PA.4"},
#endif
#ifdef AIC_USING_PSADC5
{3, PIN_PULL_DIS, 3, "PA.5"},
#endif
#ifdef AIC_USING_PSADC6
{3, PIN_PULL_DIS, 3, "PA.6"},
#endif
#ifdef AIC_USING_PSADC7
{3, PIN_PULL_DIS, 3, "PA.7"},
#endif
#ifdef AIC_USING_PSADC8
{3, PIN_PULL_DIS, 3, "PA.8"},
#endif
#ifdef AIC_USING_PSADC9
{3, PIN_PULL_DIS, 3, "PA.9"},
#endif
#ifdef AIC_USING_PSADC10
{3, PIN_PULL_DIS, 3, "PA.10"},
#endif
#ifdef AIC_USING_PSADC11
{3, PIN_PULL_DIS, 3, "PA.11"},
#endif
#ifdef AIC_USING_CAN0
{4, PIN_PULL_DIS, 3, "PE.16"},
{4, PIN_PULL_DIS, 3, "PE.17"},
#endif
#ifdef AIC_USING_CTP
{1, PIN_PULL_DIS, 3, AIC_TOUCH_PANEL_RST_PIN},
{1, PIN_PULL_DIS, 3, AIC_TOUCH_PANEL_INT_PIN},
#endif
#ifdef LV_USB_OSD_SETTINGS_MENU
{1, PIN_PULL_DIS, 3, LV_USB_OSD_SETTINGS_WAKEUP_KEY},
#endif
};
void aic_board_pinmux_init(void)
{
uint32_t i = 0;
long pin = 0;
unsigned int g;
unsigned int p;
for (i=0; i<ARRAY_SIZE(aic_pinmux_config); i++) {
pin = hal_gpio_name2pin(aic_pinmux_config[i].name);
if (pin < 0)
continue;
g = GPIO_GROUP(pin);
p = GPIO_GROUP_PIN(pin);
hal_gpio_set_func(g, p, aic_pinmux_config[i].func);
hal_gpio_set_bias_pull(g, p, aic_pinmux_config[i].bias);
hal_gpio_set_drive_strength(g, p, aic_pinmux_config[i].drive);
}
#ifndef AIC_BOOTLOADER
struct fdt_header *header;
uint32_t dtb_size;
void *dtb_pos_r;
header = (struct fdt_header *)(&__dtb_pos_f);
if (fdt_magic(header) == FDT_MAGIC)
{
dtb_size = fdt_totalsize(header);
dtb_pos_r = aicos_malloc(0, dtb_size);
aicos_memcpy(dtb_pos_r, (void *)(&__dtb_pos_f), dtb_size);
of_relocate_dtb((unsigned long)dtb_pos_r);
pinmux_fdt_parse();
}
#endif
}

109
target/d21x/demo88-nand/sys_clk.c Normal file
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/*
* Copyright (c) 2022, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: weilin.peng@artinchip.com
*/
#include <aic_core.h>
#include <aic_hal.h>
#include "board.h"
#ifndef AIC_CLK_PLL_INT0_FREQ
#define AIC_CLK_PLL_INT0_FREQ 600000000
#endif
#ifndef AIC_CLK_PLL_INT1_FREQ
#define AIC_CLK_PLL_INT1_FREQ 1200000000
#endif
#ifndef AIC_CLK_PLL_FRA0_FREQ
#define AIC_CLK_PLL_FRA0_FREQ 600000000
#endif
#ifndef AIC_CLK_PLL_FRA1_FREQ
#define AIC_CLK_PLL_FRA1_FREQ 491520000
#endif
#ifndef AIC_CLK_PLL_FRA2_FREQ
#define AIC_CLK_PLL_FRA2_FREQ 840000000
#endif
#ifndef AIC_CLK_CPU_FREQ
#define AIC_CLK_CPU_FREQ 600000000
#endif
#ifndef AIC_CLK_AXI0_FREQ
#define AIC_CLK_AXI0_FREQ 240000000
#endif
#ifndef AIC_CLK_AHB0_FREQ
#define AIC_CLK_AHB0_FREQ 240000000
#endif
#ifndef AIC_CLK_APB0_FREQ
#define AIC_CLK_APB0_FREQ 100000000
#endif
struct aic_sysclk
{
unsigned long freq;
unsigned int clk_id;
unsigned int parent_clk_id;
};
struct aic_sysclk aic_sysclk_config[] = {
{AIC_CLK_PLL_INT0_FREQ, CLK_PLL_INT0, 0}, /* 600000000 */
{AIC_CLK_PLL_INT1_FREQ, CLK_PLL_INT1, 0}, /* 1200000000 */
//{AIC_CLK_PLL_FRA0_FREQ, CLK_PLL_FRA0, 0}, /* ddr2/ddr3 */
{AIC_CLK_PLL_FRA1_FREQ, CLK_PLL_FRA1, 0}, /* 491520000 */
{AIC_CLK_PLL_FRA2_FREQ, CLK_PLL_FRA2, 0}, /* 840000000 */
{AIC_CLK_CPU_FREQ, CLK_CPU, CLK_CPU_SRC1}, /* 600000000 */
{AIC_CLK_AXI0_FREQ, CLK_AXI0, CLK_AXI0_SRC1}, /* 240000000 */
{AIC_CLK_AHB0_FREQ, CLK_AHB0, CLK_AHB0_SRC1}, /* 240000000 */
{AIC_CLK_APB0_FREQ, CLK_APB0, CLK_APB0_SRC1}, /* 100000000 */
// {24000000, CLK_APB1, 0},
#ifdef AIC_USING_CLK_OUT0
{AIC_CLK_OUT0_FREQ, CLK_OUT0, 0},
#endif /* AIC_USING_CLK_OUT0 */
#ifdef AIC_USING_CLK_OUT1
{AIC_CLK_OUT1_FREQ, CLK_OUT1, 0},
#endif /* AIC_USING_CLK_OUT1 */
#ifdef AIC_USING_CLK_OUT2
{AIC_CLK_OUT2_FREQ, CLK_OUT2, 0},
#endif /* AIC_USING_CLK_OUT2 */
#ifdef AIC_USING_CLK_OUT3
{AIC_CLK_OUT3_FREQ, CLK_OUT3, 0},
#endif /* AIC_USING_CLK_OUT3 */
};
/*
* Some Chips may enable USB0 EHCI in Boot ROM,
* it is better to disable USB0 EHCI during boot to avoid some side effect.
*/
static void usb_ehci_disable(void)
{
hal_clk_disable_assertrst(CLK_USBH0);
hal_clk_disable(CLK_USBH0);
}
void aic_board_sysclk_init(void)
{
uint32_t i = 0;
usb_ehci_disable();
for (i=0; i<sizeof(aic_sysclk_config)/sizeof(struct aic_sysclk); i++) {
if (aic_sysclk_config[i].freq == 0)
continue;
/* multi parent clk */
if (aic_sysclk_config[i].parent_clk_id) {
hal_clk_set_freq(aic_sysclk_config[i].parent_clk_id,
aic_sysclk_config[i].freq);
hal_clk_enable(aic_sysclk_config[i].parent_clk_id);
hal_clk_set_parent(aic_sysclk_config[i].clk_id,
aic_sysclk_config[i].parent_clk_id);
} else {
hal_clk_set_freq(aic_sysclk_config[i].clk_id, aic_sysclk_config[i].freq);
hal_clk_enable(aic_sysclk_config[i].clk_id);
}
}
/* Enable sys clk */
hal_clk_enable_deassertrst_iter(CLK_GPIO);
hal_clk_enable_deassertrst_iter(CLK_GTC);
}