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This commit is contained in:
刘可亮
2024-01-27 08:47:24 +08:00
parent d3bd993b5f
commit 9f7ba67007
2345 changed files with 74421 additions and 76616 deletions
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24
bsp/artinchip/hal/cmu/aic_hal_clk.c
View File

@@ -21,6 +21,7 @@ int hal_clk_enable_deassertrst(uint32_t clk_id)
cfg->ops->enable_clk_deassert_rst != NULL,
-EINVAL);
cfg->enable_count = 1;
return (cfg->ops->enable_clk_deassert_rst(cfg));
}
@@ -35,6 +36,7 @@ int hal_clk_disable_assertrst(uint32_t clk_id)
cfg->ops->disable_clk_assert_rst != NULL,
-EINVAL);
cfg->enable_count = 0;
cfg->ops->disable_clk_assert_rst(cfg);
return 0;
}
@@ -44,11 +46,12 @@ int hal_clk_enable(uint32_t clk_id)
struct aic_clk_comm_cfg *cfg;
CHECK_PARAM(clk_id < AIC_CLK_END && clk_id > 0, -EINVAL);
cfg = (struct aic_clk_comm_cfg *)aic_clk_cfgs[clk_id];
CHECK_PARAM(cfg != NULL && cfg->ops != NULL && cfg->ops->enable != NULL,
-EINVAL);
cfg->enable_count = 1;
return (cfg->ops->enable(cfg));
}
@@ -62,6 +65,8 @@ int hal_clk_disable(uint32_t clk_id)
CHECK_PARAM(cfg != NULL && cfg->ops != NULL && cfg->ops->disable != NULL,
-EINVAL);
cfg->enable_count = 0;
cfg->ops->disable(cfg);
return 0;
}
@@ -73,8 +78,10 @@ int hal_clk_is_enabled(uint32_t clk_id)
CHECK_PARAM(clk_id < AIC_CLK_END && clk_id > 0, -EINVAL);
cfg = (struct aic_clk_comm_cfg *)aic_clk_cfgs[clk_id];
CHECK_PARAM(cfg != NULL && cfg->ops != NULL && cfg->ops->is_enabled != NULL,
-EINVAL);
CHECK_PARAM(cfg != NULL && cfg->ops != NULL, -EINVAL);
if (cfg->ops->is_enabled == NULL)
return cfg->enable_count;
return (cfg->ops->is_enabled(cfg));
}
@@ -220,3 +227,14 @@ int hal_clk_enable_deassertrst_iter(uint32_t clk_id)
ret = hal_clk_enable(clk_id);
return ret;
}
const char *hal_clk_get_name(uint32_t clk_id)
{
struct aic_clk_comm_cfg *cfg;
CHECK_PARAM(clk_id < AIC_CLK_END && clk_id > 0, 0);
cfg = (struct aic_clk_comm_cfg *)aic_clk_cfgs[clk_id];
CHECK_PARAM(cfg != NULL && cfg->name != NULL, NULL);
return cfg->name;
}

4
bsp/artinchip/hal/cmu/aic_hal_clk_def_v11.c
View File

@@ -79,8 +79,8 @@ FPCLK(CLK_PBUS, "pbus", CLK_AHB0, PARENT("ahb0"), CLK_PBUS_REG, 12, -1, 0, 0);
FPCLK(CLK_SYSCFG, "syscfg", CLK_OSC24M, PARENT("osc24m"), CLK_SYSCFG_REG, 12,
-1, 0, 0);
FPCLK(CLK_RTC, "rtc", CLK_OSC32K, PARENT("osc32k"), CLK_RTC_REG, 12, -1, 0, 0);
FPCLK_BASE(CLK_AUDIO_SCLK, "audio_sclk", CLK_PLL_INT1, PARENT("pll_int1"), CLK_AUDIO_REG, 0,
0, 0, 1, 49, 4);
FPCLK_BASE(CLK_AUDIO_SCLK, "audio_sclk", CLK_PLL_INT1, PARENT("pll_int1"), CLK_AUDIO_REG, -1,
-1, 0, 1, 49, 4);
FPCLK(CLK_CODEC, "codec", CLK_AUDIO_SCLK, PARENT("audio_sclk"), CLK_CODEC_REG, 12,
8, 0, 0);
FPCLK(CLK_I2S0, "i2s0", CLK_AUDIO_SCLK, PARENT("audio_sclk"), CLK_I2S0_REG, 12, 8,

208
bsp/artinchip/hal/cmu/aic_hal_clk_def_v12.c Normal file
View File

@@ -0,0 +1,208 @@
/*
* Copyright (c) 2022, Artinchip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <aic_core.h>
#include "aic_hal_clk.h"
extern struct aic_clk_ops aic_clk_fixed_rate_ops;
extern struct aic_clk_ops aic_clk_pll_ops;
extern struct aic_clk_ops aic_clk_fixed_parent_ops;
extern struct aic_clk_ops aic_clk_multi_parent_ops;
extern struct aic_clk_ops aic_clk_disp_ops;
/* Fixed rate clocks */
FRCLK(CLK_OSC24M, "osc24m", CLOCK_24M);
FRCLK(CLK_OSC32K, "osc32k", CLOCK_32K);
/* PLL clocks */
PLL_INT(CLK_PLL_INT0, "pll_int0", CLK_OSC24M, PARENT("osc24m"),
PLL_INT0_GEN_REG, 0);
PLL_INT(CLK_PLL_INT1, "pll_int1", CLK_OSC24M, PARENT("osc24m"),
PLL_INT1_GEN_REG, 0);
#ifdef AIC_CLK_PLL_FRA0_SSC_DIS
PLL_FRA(CLK_PLL_FRA0, "pll_fra0", CLK_OSC24M, PARENT("osc24m"),
PLL_FRA0_GEN_REG, PLL_FRA0_CFG_REG, PLL_FRA0_SDM_REG,
CLK_IGNORE_UNUSED);
#else
PLL_SDM(CLK_PLL_FRA0, "pll_fra0", CLK_OSC24M, PARENT("osc24m"),
PLL_FRA0_GEN_REG, PLL_FRA0_CFG_REG, PLL_FRA0_SDM_REG,
CLK_IGNORE_UNUSED);
#endif
#ifdef AIC_CLK_PLL_FRA2_SSC_DIS
PLL_FRA(CLK_PLL_FRA2, "pll_fra2", CLK_OSC24M, PARENT("osc24m"),
PLL_FRA2_GEN_REG, PLL_FRA2_CFG_REG, PLL_FRA2_SDM_REG, 0);
#else
PLL_SDM(CLK_PLL_FRA2, "pll_fra2", CLK_OSC24M, PARENT("osc24m"),
PLL_FRA2_GEN_REG, PLL_FRA2_CFG_REG, PLL_FRA2_SDM_REG, 0);
#endif
/* Fixed parent clocks */
FPCLK(CLK_CPU_SRC1, "cpu_src1", CLK_PLL_INT0, PARENT("pll_int0"), CLK_CPU_REG,
-1, -1, 0, 5);
FPCLK(CLK_AXI_AHB_SRC1, "axi_ahb_src1", CLK_PLL_INT1, PARENT("pll_int1"),
CLK_AXI_AHB_REG, -1, -1, 0, 5);
FPCLK(CLK_APB0_SRC1, "apb0_src1", CLK_PLL_INT1, PARENT("pll_int1"),
CLK_APB0_REG, -1, -1, 0, 5);
FPCLK(CLK_APB1, "apb1", CLK_OSC24M, PARENT("osc24m"), CLK_APB1_REG, -1, -1, 0,
0);
FPCLK(CLK_DMA, "dma", CLK_AHB0, PARENT("ahb0"), CLK_DMA_REG, 12, -1, 0, 0);
FPCLK(CLK_DCE, "dce", CLK_AHB0, PARENT("ahb0"), CLK_DCE_REG, 12, -1, 0, 0);
FPCLK(CLK_XSPI, "xspi", CLK_PLL_FRA0, PARENT("pll_fra0"), CLK_XSPI_REG, 12, 8,
0, 5);
FPCLK(CLK_QSPI0, "qspi0", CLK_PLL_FRA0, PARENT("pll_fra0"), CLK_QSPI0_REG, 12,
8, 0, 5);
FPCLK(CLK_QSPI1, "qspi1", CLK_PLL_FRA0, PARENT("pll_fra0"), CLK_QSPI1_REG, 12,
8, 0, 5);
FPCLK(CLK_SDMC0, "sdmc0", CLK_PLL_FRA0, PARENT("pll_fra0"), CLK_SDMC0_REG, 12,
8, 0, 5);
FPCLK(CLK_SDMC1, "sdmc1", CLK_PLL_FRA0, PARENT("pll_fra0"), CLK_SDMC1_REG, 12,
8, 0, 5);
FPCLK(CLK_SYSCFG, "syscfg", CLK_OSC24M, PARENT("osc24m"), CLK_SYSCFG_REG, 12,
-1, 0, 0);
FPCLK(CLK_CODEC, "codec", CLK_AUDIO_SCLK, PARENT("audio_sclk"), CLK_CODEC_REG, 12,
8, 0, 0);
FPCLK(CLK_DE, "de", CLK_PLL_INT1, PARENT("pll_int1"), CLK_DE_REG, 12, 8, 0, 5);
FPCLK(CLK_GE, "ge", CLK_PLL_INT1, PARENT("pll_int1"), CLK_GE_REG, 12, 8, 0, 5);
FPCLK(CLK_VE, "ve", CLK_PLL_INT1, PARENT("pll_int1"), CLK_VE_REG, 12, 8, 0, 5);
FPCLK(CLK_WDT, "wdt", CLK_OSC32K, PARENT("clk_32k"), CLK_WDT_REG, 12, 8, 0,
0);
FPCLK(CLK_SID, "sid", CLK_OSC24M, PARENT("osc24m"), CLK_SID_REG, 12, 8, 0, 0);
FPCLK(CLK_GTC, "gtc", CLK_APB1, PARENT("apb1"), CLK_GTC_REG, 12, -1, 0, 0);
FPCLK(CLK_GPIO, "gpio", CLK_APB0, PARENT("apb0"), CLK_GPIO_REG, 12, 8, 0, 5);
FPCLK(CLK_UART0, "uart0", CLK_PLL_INT1, PARENT("pll_int1"), CLK_UART0_REG, 12,
8, 0, 5);
FPCLK(CLK_UART1, "uart1", CLK_PLL_INT1, PARENT("pll_int1"), CLK_UART1_REG, 12,
8, 0, 5);
FPCLK(CLK_UART2, "uart2", CLK_PLL_INT1, PARENT("pll_int1"), CLK_UART2_REG, 12,
8, 0, 5);
FPCLK(CLK_UART3, "uart3", CLK_PLL_INT1, PARENT("pll_int1"), CLK_UART3_REG, 12,
8, 0, 5);
FPCLK(CLK_I2C0, "i2c0", CLK_APB1, PARENT("apb1"), CLK_I2C0_REG, 12, -1, 0, 0);
FPCLK(CLK_I2C1, "i2c1", CLK_APB1, PARENT("apb1"), CLK_I2C1_REG, 12, -1, 0, 0);
FPCLK(CLK_CAN0, "can0", CLK_APB1, PARENT("apb1"), CLK_CAN0_REG, 12, -1, 0, 0);
FPCLK(CLK_CAN1, "can1", CLK_APB1, PARENT("apb1"), CLK_CAN1_REG, 12, -1, 0, 0);
FPCLK(CLK_PWM, "pwm", CLK_PLL_INT1, PARENT("pll_int1"), CLK_PWM_REG, 12, 8, 0,
5);
FPCLK(CLK_ADCIM, "adcim", CLK_PLL_INT1, PARENT("pll_int1"), CLK_ADCIM_REG, 12,
8, 0, 5);
FPCLK(CLK_GPAI, "gpai", CLK_APB1, PARENT("apb1"), CLK_GPAI_REG, 12, -1, 0, 0);
FPCLK(CLK_RTP, "rtp", CLK_APB1, PARENT("apb1"), CLK_RTP_REG, 12, -1, 0, 0);
FPCLK(CLK_TSEN, "tsen", CLK_APB1, PARENT("apb1"), CLK_TSEN_REG, 12, -1, 0, 0);
FPCLK(CLK_CIR, "cir", CLK_APB1, PARENT("apb1"), CLK_CIR_REG, 12, -1, 0, 0);
FPCLK(CLK_MDI, "mdi", CLK_PLL_FRA2, PARENT("pll_fra2"), CLK_MDI_REG, 12, 8, 0,
5);
FPCLK(CLK_MTOP, "mtop", CLK_APB0, PARENT("apb0"), CLK_MTOP_REG, 12, -1, 0, 0);
FPCLK(CLK_SPIENC, "spienc", CLK_AHB0, PARENT("ahb0"), CLK_SPIENC_REG, 12, 8, 0,
0);
FPCLK(CLK_RGB, "rgb", CLK_SCLK, PARENT("sclk"), CLK_RGB_REG, 12, 8, 0, 0);
/* Multi parent clocks */
static const u8 axi_ahb_src_sels[] = {
/* "osc24m", "ahb0_src1", */
CLK_OSC24M,
CLK_AXI_AHB_SRC1,
};
static const u8 apb0_src_sels[] = {
/* "osc24m",
"apb0_src1", */
CLK_OSC24M,
CLK_APB0_SRC1,
};
static const u8 cpu_src_sels[] = {
/* "osc24m",
"cpu_src1", */
CLK_OSC24M,
CLK_CPU_SRC1,
};
static const u8 audio_src_sels[] = {
/* "pll_int0",
"pll_fra0", */
CLK_PLL_INT1,
CLK_PLL_FRA0,
};
MPCLK(CLK_CPU, "cpu", cpu_src_sels, CLK_CPU_REG, -1, 8, 1, 0, 0);
MPCLK(CLK_AXI0, "axi0", axi_ahb_src_sels, CLK_AXI_AHB_REG, -1, 8, 1, 0, 0);
MPCLK(CLK_AHB0, "ahb0", axi_ahb_src_sels, CLK_AXI_AHB_REG, -1, 8, 1, 0, 0);
MPCLK(CLK_APB0, "apb0", apb0_src_sels, CLK_APB0_REG, -1, 8, 1, 0, 0);
MPCLK(CLK_AUDIO_SCLK, "audio_sclk", audio_src_sels, CLK_AUDIO_REG, -1, 8, 1, 0, 5);
/* Disp clocks */
DISPCLK(CLK_PIX, "pixclk", CLK_SCLK, PARENT("sclk"), CLK_DISP_REG, 0, 0, 4, 5,
10, 2, 12, 2);
DISPCLK(CLK_SCLK, "sclk", CLK_PLL_FRA2, PARENT("pll_fra2"), CLK_DISP_REG, 0, 3,
0, 0, 0, 0, 0, 0);
/* Clock cfg array */
const struct aic_clk_comm_cfg *aic_clk_cfgs[AIC_CLK_END] = {
/* Fixed rate clock */
DUMMY_CFG(CLK_DUMMY),
AIC_CLK_CFG(CLK_OSC24M),
AIC_CLK_CFG(CLK_OSC32K),
/* PLL clock */
AIC_CLK_CFG(CLK_PLL_INT0),
AIC_CLK_CFG(CLK_PLL_INT1),
AIC_CLK_CFG(CLK_PLL_FRA0),
AIC_CLK_CFG(CLK_PLL_FRA2),
/* fixed factor clock */
AIC_CLK_CFG(CLK_AXI_AHB_SRC1),
AIC_CLK_CFG(CLK_APB0_SRC1),
AIC_CLK_CFG(CLK_CPU_SRC1),
/* system clock */
AIC_CLK_CFG(CLK_AXI0),
AIC_CLK_CFG(CLK_AHB0),
AIC_CLK_CFG(CLK_APB0),
AIC_CLK_CFG(CLK_APB1),
AIC_CLK_CFG(CLK_CPU),
/* Peripheral clock */
AIC_CLK_CFG(CLK_DMA),
AIC_CLK_CFG(CLK_DCE),
AIC_CLK_CFG(CLK_XSPI),
AIC_CLK_CFG(CLK_QSPI0),
AIC_CLK_CFG(CLK_QSPI1),
AIC_CLK_CFG(CLK_SDMC0),
AIC_CLK_CFG(CLK_SDMC1),
AIC_CLK_CFG(CLK_SYSCFG),
AIC_CLK_CFG(CLK_SPIENC),
AIC_CLK_CFG(CLK_AUDIO_SCLK),
AIC_CLK_CFG(CLK_CODEC),
AIC_CLK_CFG(CLK_RGB),
AIC_CLK_CFG(CLK_DE),
AIC_CLK_CFG(CLK_GE),
AIC_CLK_CFG(CLK_VE),
AIC_CLK_CFG(CLK_WDT),
AIC_CLK_CFG(CLK_SID),
AIC_CLK_CFG(CLK_GTC),
AIC_CLK_CFG(CLK_GPIO),
AIC_CLK_CFG(CLK_UART0),
AIC_CLK_CFG(CLK_UART1),
AIC_CLK_CFG(CLK_UART2),
AIC_CLK_CFG(CLK_UART3),
AIC_CLK_CFG(CLK_I2C0),
AIC_CLK_CFG(CLK_I2C1),
AIC_CLK_CFG(CLK_CAN0),
AIC_CLK_CFG(CLK_CAN1),
AIC_CLK_CFG(CLK_PWM),
AIC_CLK_CFG(CLK_ADCIM),
AIC_CLK_CFG(CLK_GPAI),
AIC_CLK_CFG(CLK_RTP),
AIC_CLK_CFG(CLK_TSEN),
AIC_CLK_CFG(CLK_MDI),
AIC_CLK_CFG(CLK_CIR),
AIC_CLK_CFG(CLK_MTOP),
/* Display clock */
AIC_CLK_CFG(CLK_PIX),
AIC_CLK_CFG(CLK_SCLK),
};

56
bsp/artinchip/hal/cmu/aic_hal_cpu_clk.c
View File

@@ -8,8 +8,6 @@
#include <aic_core.h>
#include "aic_hal_clk.h"
#define CPU_CLK_WR_KEY 0x2023
#define to_clk_cpu_mod(_hw) \
container_of(_hw, struct aic_clk_cpu_cfg, comm)
@@ -18,30 +16,55 @@ static u32 clk_cpu_mod_write_enable(struct aic_clk_cpu_cfg *mod, u32 val_tmp)
u32 val = val_tmp;
if (mod->key_bit >= 0) {
val &= ~(mod->key_mask << mod->key_bit);
val |= CPU_CLK_WR_KEY << mod->key_bit;
val |= mod->key_val << mod->key_bit;
}
return val;
}
static int clk_cpu_mod_enable(struct aic_clk_comm_cfg *comm_cfg)
static int
clk_cpu_enable_and_deassert_rst(struct aic_clk_comm_cfg *comm_cfg)
{
struct aic_clk_cpu_cfg *mod = to_clk_cpu_mod(comm_cfg);
u32 val;
/* enbale clk */
val = readl(cmu_reg(mod->offset_reg));
if (mod->gate_bit >= 0)
val |= (1 << mod->gate_bit);
val = clk_cpu_mod_write_enable(mod, val);
writel(val, cmu_reg(mod->offset_reg));
aicos_udelay(30);
/* deassert rst */
val = readl(cmu_reg(mod->offset_reg));
val |= (1 << MOD_RSTN);
val = clk_cpu_mod_write_enable(mod, val);
writel(val, cmu_reg(mod->offset_reg));
aicos_udelay(30);
return 0;
}
static void clk_cpu_mod_disable(struct aic_clk_comm_cfg *comm_cfg)
static void
clk_cpu_disable_and_assert_rst(struct aic_clk_comm_cfg *comm_cfg)
{
struct aic_clk_cpu_cfg *mod = to_clk_cpu_mod(comm_cfg);
u32 val;
/* assert rst */
val = readl(cmu_reg(mod->offset_reg));
val &= ~(1 << MOD_RSTN);
val = clk_cpu_mod_write_enable(mod, val);
writel(val, cmu_reg(mod->offset_reg));
aicos_udelay(30);
/* disbale clk */
val = readl(cmu_reg(mod->offset_reg));
if (mod->gate_bit >= 0)
@@ -49,18 +72,23 @@ static void clk_cpu_mod_disable(struct aic_clk_comm_cfg *comm_cfg)
val = clk_cpu_mod_write_enable(mod, val);
writel(val, cmu_reg(mod->offset_reg));
aicos_udelay(30);
}
static int clk_cpu_mod_is_enabled(struct aic_clk_comm_cfg *comm_cfg)
{
struct aic_clk_cpu_cfg *mod = to_clk_cpu_mod(comm_cfg);
u32 val;
int ret = 0;
val = readl(cmu_reg(mod->offset_reg));
if (mod->gate_bit >= 0)
return val & (1 << mod->gate_bit);
ret = (val & (1 << mod->gate_bit)) ? 1 : 0;
else
ret = 1;
return 1;
return ret;
}
static unsigned long clk_cpu_mod_recalc_rate(struct aic_clk_comm_cfg *comm_cfg,
@@ -74,8 +102,9 @@ static unsigned long clk_cpu_mod_recalc_rate(struct aic_clk_comm_cfg *comm_cfg,
if (parent_index == 1) {
div0 = (readl(cmu_reg(mod->offset_reg)) >> mod->div0_bit) & mod->div0_mask;
rate = parent_rate / (div0 + 1);
} else
} else {
rate = parent_rate;
}
#ifdef CONFIG_DEBUG_ON_FPGA_BOARD_ARTINCHIP
rate = fpga_board_rate[mod->id];
@@ -113,8 +142,13 @@ __out:
static unsigned int clk_cpu_mod_get_parent(struct aic_clk_comm_cfg *comm_cfg)
{
struct aic_clk_cpu_cfg *mod = to_clk_cpu_mod(comm_cfg);
u32 index =
(readl(cmu_reg(mod->offset_reg)) >> mod->mux_bit) & mod->mux_mask;
return (readl(cmu_reg(mod->offset_reg)) >> mod->mux_bit) & mod->mux_mask;
if (index < mod->num_parents)
return mod->parent_ids[index];
else
return 0;
}
static int clk_cpu_mod_set_parent(struct aic_clk_comm_cfg *comm_cfg,
@@ -195,8 +229,8 @@ static long clk_cpu_mod_round_rate(struct aic_clk_comm_cfg *comm_cfg,
const struct aic_clk_ops aic_clk_cpu_ops = {
.enable = clk_cpu_mod_enable,
.disable = clk_cpu_mod_disable,
.enable_clk_deassert_rst = clk_cpu_enable_and_deassert_rst,
.disable_clk_assert_rst = clk_cpu_disable_and_assert_rst,
.is_enabled = clk_cpu_mod_is_enabled,
.recalc_rate = clk_cpu_mod_recalc_rate,
.round_rate = clk_cpu_mod_round_rate,

38
bsp/artinchip/hal/cmu/aic_hal_fpga_clk_def_v12.c Normal file
View File

@@ -0,0 +1,38 @@
/*
* Copyright (c) 2022, Artinchip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <aic_core.h>
#include "aic_hal_clk.h"
#ifdef FPGA_BOARD_ARTINCHIP
const unsigned long fpga_board_rate[] = {
[CLK_OSC24M] = CLOCK_24M, [CLK_OSC32K] = CLOCK_32K,
[CLK_PLL_INT0] = CLOCK_60M, [CLK_PLL_INT1] = CLOCK_60M,
[CLK_PLL_FRA0] = CLOCK_60M, [CLK_PLL_FRA2] = CLOCK_60M,
[CLK_AXI_AHB_SRC1] = CLOCK1_FREQ, [CLK_APB0_SRC1] = CLOCK_30M,
[CLK_CPU_SRC1] = CLOCK_60M, [CLK_AXI0] = CLOCK1_FREQ,
[CLK_AHB0] = CLOCK1_FREQ, [CLK_APB0] = CLOCK_30M,
[CLK_APB1] = CLOCK_24M, [CLK_CPU] = CLOCK_60M,
[CLK_DMA] = CLOCK_60M,
[CLK_XSPI] = CLOCK_24M, [CLK_QSPI0] = CLOCK1_FREQ,
[CLK_QSPI1] = CLOCK1_FREQ, [CLK_SDMC0] = CLOCK1_FREQ,
[CLK_SDMC1] = CLOCK1_FREQ,
[CLK_SYSCFG] = CLOCK_24M, [CLK_GPIO] = CLOCK_24M,
[CLK_CODEC] = CLOCK_AUDIO, [CLK_RGB] = CLOCK_100M,
[CLK_DE] = CLOCK_36M, [CLK_GE] = CLOCK_36M,
[CLK_VE] = CLOCK_36M, [CLK_WDT] = CLOCK_32K,
[CLK_SID] = CLOCK_24M, [CLK_GTC] = CLOCK_24M,
[CLK_UART0] = CLOCK_24M, [CLK_UART1] = CLOCK_24M,
[CLK_UART2] = CLOCK_24M, [CLK_UART3] = CLOCK_24M,
[CLK_I2C0] = CLOCK_24M, [CLK_I2C1] = CLOCK_24M,
[CLK_CAN0] = CLOCK_24M, [CLK_CAN1] = CLOCK_24M,
[CLK_PWM] = CLOCK_24M, [CLK_ADCIM] = CLOCK_24M,
[CLK_GPAI] = CLOCK_24M, [CLK_RTP] = CLOCK_24M,
[CLK_TSEN] = CLOCK_24M,
};
#endif

9
bsp/artinchip/hal/cmu/aic_hal_pll_clk.c
View File

@@ -213,6 +213,9 @@ static int clk_pll_set_rate(struct aic_clk_comm_cfg *comm_cfg,
(factor_n << PLL_FACTORN_BIT) |
(factor_m << PLL_FACTORM_BIT) |
(factor_p << PLL_FACTORP_BIT);
/* If SDM enable, set PLL_ICP = 0 */
if (pll->type == AIC_PLL_SDM)
reg_val &= ~(0x1F << 24);
writel(reg_val, cmu_reg(pll->offset_gen));
if (pll->type == AIC_PLL_FRA) {
@@ -293,7 +296,11 @@ void hal_clk_pll_lowpower(void)
*(volatile uint32_t *)(CMU_BASE+PLL_IN_REG) &= ~(0x7U << 29);
#endif
#elif defined(AIC_CMU_DRV_V11)
*(volatile uint32_t *)(CMU_BASE+PLL_IN_REG) &= ~((0x7U << 29) | (0x1U << 1));
int xtal_en = readl(SID_BASE + 0x1C) & (0x1 << 1);
if (xtal_en)
*(volatile uint32_t *)(CMU_BASE+PLL_IN_REG) &= ~((0x7U << 29) | (0x1U << 1));
else
*(volatile uint32_t *)(CMU_BASE+PLL_IN_REG) &= ~((0x7U << 29) | (0x1U << 28));
#elif defined(AIC_CMU_DRV_V12)
*(volatile uint32_t *)(CMU_BASE+PLL_IN_REG) &= ~((0x7U << 29) | (0x1U << 1));
#endif

47
bsp/artinchip/hal/cmu/aic_hal_reset_def_v12.c Normal file
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/*
* Copyright (c) 2022, Artinchip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <aic_core.h>
#include "aic_hal_clk.h"
#include "aic_hal_reset.h"
const struct aic_reset_signal aic_reset_signals[RESET_NUMBER] = {
[RESET_DMA] = { CLK_DMA_REG, BIT(13) },
[RESET_DCE] = { CLK_DCE_REG, BIT(13) },
[RESET_XSPI] = { CLK_XSPI_REG, BIT(13) },
[RESET_QSPI0] = { CLK_QSPI0_REG, BIT(13) },
[RESET_QSPI1] = { CLK_QSPI1_REG, BIT(13) },
[RESET_SDMMC0] = { CLK_SDMC0_REG, BIT(13) },
[RESET_SDMMC1] = { CLK_SDMC1_REG, BIT(13) },
[RESET_SYSCFG] = { CLK_SYSCFG_REG, BIT(13) },
[RESET_SPIENC] = { CLK_SPIENC_REG, BIT(13) },
[RESET_CODEC] = { CLK_CODEC_REG, BIT(13) },
[RESET_RGB] = { CLK_RGB_REG, BIT(13) },
[RESET_DE] = { CLK_DE_REG, BIT(13) },
[RESET_GE] = { CLK_GE_REG, BIT(13) },
[RESET_VE] = { CLK_VE_REG, BIT(13) },
[RESET_WDT] = { CLK_WDT_REG, BIT(13) },
[RESET_SID] = { CLK_SID_REG, BIT(13) },
[RESET_GTC] = { CLK_GTC_REG, BIT(13) },
[RESET_GPIO] = { CLK_GPIO_REG, BIT(13) },
[RESET_UART0] = { CLK_UART0_REG, BIT(13) },
[RESET_UART1] = { CLK_UART1_REG, BIT(13) },
[RESET_UART2] = { CLK_UART2_REG, BIT(13) },
[RESET_UART3] = { CLK_UART3_REG, BIT(13) },
[RESET_I2C0] = { CLK_I2C0_REG, BIT(13) },
[RESET_I2C1] = { CLK_I2C1_REG, BIT(13) },
[RESET_CAN0] = { CLK_CAN0_REG, BIT(13) },
[RESET_CAN1] = { CLK_CAN1_REG, BIT(13) },
[RESET_PWM] = { CLK_PWM_REG, BIT(13) },
[RESET_ADCIM] = { CLK_ADCIM_REG, BIT(13) },
[RESET_GPAI] = { CLK_GPAI_REG, BIT(13) },
[RESET_RTP] = { CLK_RTP_REG, BIT(13) },
[RESET_TSEN] = { CLK_TSEN_REG, BIT(13) },
[RESET_MDI] = { CLK_MDI_REG, BIT(13) },
[RESET_CIR] = { CLK_CIR_REG, BIT(13) },
[RESET_MTOP] = { CLK_MTOP_REG, BIT(13) },
};