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v1.0.3

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刘可亮
2024-01-27 08:47:24 +08:00
parent d3bd993b5f
commit 9f7ba67007
2345 changed files with 74421 additions and 76616 deletions
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43
bsp/artinchip/hal/display/aic_hal_dbi.c
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@@ -6,9 +6,12 @@
#include <stdint.h>
#include <aic_core.h>
#include <aic_iopoll.h>
#include "aic_hal_dbi.h"
#define DBI_TIMEOUT_US 1000000
void i8080_cmd_ctl(void *base, u32 first_line, u32 other_line)
{
reg_set_bits(base + DBI_I8080_COMMAND_CTL,
@@ -73,7 +76,8 @@ void i8080_wr_fifo_flush(void *base)
void i8080_cmd_wr(void *base, u32 code, u32 count, const u8 *data)
{
int i;
int i, ret;
u32 val;
i8080_wr_cmd(base, code);
@@ -82,9 +86,20 @@ void i8080_cmd_wr(void *base, u32 code, u32 count, const u8 *data)
i8080_wr_ctl(base, count, 1);
while (!reg_rd_bit(base + DBI_I8080_STATUS, DBI_I8080_TX_FIFO_EMPTY,
DBI_I8080_TX_FIFO_EMPTY_SHIFT))
;
#ifdef AIC_DISP_MIPI_DBI_DEBUG
printf("command: %#x, ", code);
printf("data:");
for (i = 0; i < count; i++)
printf(" %#x", *(data + i));
printf("\n");
#endif
ret = readl_poll_timeout(base + DBI_I8080_STATUS, val,
((val & (DBI_I8080_IDEL | DBI_I8080_TX_FIFO_EMPTY)) == 0x2),
DBI_TIMEOUT_US);
if (ret)
pr_err("Timeout during i8080 write command\n");
}
void qspi_code_cfg(void *base, u32 code1, u32 code2, u32 code3)
@@ -186,7 +201,8 @@ void spi_wr_fifo_flush(void *base)
void spi_cmd_wr(void *base, u32 code, u32 count, const u8 *data)
{
int i;
int i, ret;
u32 val;
spi_wr_cmd(base, code);
@@ -195,9 +211,20 @@ void spi_cmd_wr(void *base, u32 code, u32 count, const u8 *data)
spi_wr_ctl(base, count, 1);
while (!reg_rd_bit(base + DBI_SPI_STATUS, DBI_SPI_TX_FIFO_EMPTY,
DBI_SPI_TX_FIFO_EMPTY_SHIFT))
;
#ifdef AIC_DISP_MIPI_DBI_DEBUG
printf("command: %#x, ", code);
printf("data:");
for (i = 0; i < count; i++)
printf(" %#x", *(data + i));
printf("\n");
#endif
ret = readl_poll_timeout(base + DBI_SPI_STATUS, val,
((val & (DBI_SPI_IDEL | DBI_SPI_TX_FIFO_EMPTY)) == 0x2),
DBI_TIMEOUT_US);
if (ret)
pr_err("Timeout during spi write command\n");
}