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v1.0.3
This commit is contained in:
刘可亮
265
bsp/artinchip/hal/dma/hal_dma_reg_v1x.h
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265
bsp/artinchip/hal/dma/hal_dma_reg_v1x.h
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/*
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* Copyright (c) 2022, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ARTINCHIP_HAL_DMA_REG_V1X_H_
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#define _ARTINCHIP_HAL_DMA_REG_V1X_H_
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#include "aic_core.h"
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#include "hal_dma.h"
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#include "aic_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define TASK_MAX_NUM 24
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#define DELAY_DEF_VAL 0x40
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#define DMA_IRQ_CHAN_NR 4
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#define MAX_LEN 0x2000000
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#define DMA_IRQ_EN_REG(x) ((x) * 0x04 + 0x00)
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#define DMA_IRQ_DIS_REG(x) ((x) * 0x04 + 0x20)
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#if defined(AIC_DMA_DRV_V10) || defined(AIC_DMA_DRV_V11) \
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|| defined(AIC_DMA_DRV_V12)
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#define DMA_CHAN_OFFSET (0x40)
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#define DMA_IRQ_STA_REG(x) ((x) * 0x04 + 0x10)
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#define DMA_CH_STA_REG (0x0030)
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#define DMA_LINK_END_FLAG 0xFFFFF800
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#endif
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/*
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* define dma_v1.x register list
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*/
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#define DMA_MEM_CFG (0x0020)
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#define DMA_GATE_REG (0x0028)
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#define DMA_CH_EN_REG (0x0000)
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#define DMA_CH_PAUSE_REG (0x0004)
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#define DMA_CH_TASK_REG (0x0008)
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#define DMA_CH_CFG_REG (0x000C)
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#define DMA_CH_SRC_REG (0x0010)
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#define DMA_CH_SINK_REG (0x0014)
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#define DMA_CH_LEFT_REG (0x0018)
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#define DMA_CH_MODE_REG (0x0028)
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#define DMA_CH_PKG_NUM_REG (0x0030)
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#define DMA_CH_MEMSET_VAL_REG (0x0034)
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/*
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* define macro for access register for specific channel
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*/
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#if defined(AIC_DMA_DRV_V10) || defined(AIC_DMA_DRV_V11) \
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|| defined(AIC_DMA_DRV_V12)
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#define DMA_IRQ_HALF_TASK BIT(0)
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#define DMA_IRQ_ONE_TASK BIT(1)
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#define DMA_IRQ_ALL_TASK BIT(2)
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#define DMA_IRQ_CH_WIDTH (4)
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#define DMA_IRQ_MASK(ch) (GENMASK(2, 0) << DMA_IRQ_SHIFT(ch))
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#endif
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#define DMA_IRQ_SHIFT(ch) (DMA_IRQ_CH_WIDTH * (ch))
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#define AIC_DMA_BUS_WIDTH \
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(BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_16_BYTES))
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/*
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* define bit index in channel configuration register
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*/
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#if defined(AIC_DMA_DRV_V10) || defined(AIC_DMA_DRV_V11) \
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|| defined(AIC_DMA_DRV_V12)
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/* dma_v1.x task config */
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#define DST_WIDTH_BITSHIFT 25
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#define DST_ADDR_BITSHIFT 24
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#define DST_BURST_BITSHIFT 22
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#define DST_PORT_BITSHIFT 16
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#define SRC_WIDTH_BITSHIFT 9
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#define SRC_ADDR_BITSHIFT 8
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#define SRC_BURST_BITSHIFT 6
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#define SRC_PORT_BITSHIFT 0
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#define ADDR_LINEAR_MODE 0
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#define ADDR_FIXED_MODE 1
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#endif
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#define GET_DMA_DST_BURST(x) (((x) << DST_BURST_BITSHIFT) & GENMASK(1, 0))
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#define GET_DMA_SRC_BURST(x) (((x) << DST_BURST_BITSHIFT) & GENMASK(1, 0))
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#define DMA_DRQ_PORT_MASK 0x3F
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#define DMA_WAIT_MODE 0
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#define DMA_HANDSHAKE_MODE 1
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#define DMA_DST_MODE_SHIFT 3
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#define DMA_SRC_MODE_SHIFT 2
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#if defined(AIC_DMA_DRV_V12)
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#define DMA_SRC_HANDSHAKE_ENABLE 5
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#define DMA_DST_HANDSHAKE_ENABLE 6
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#else
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#define DMA_SRC_HANDSHAKE_ENABLE 4
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#define DMA_DST_HANDSHAKE_ENABLE 4
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#endif
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#define DMA_S_WAIT_D_HANDSHAKE (DMA_HANDSHAKE_MODE << DMA_DST_MODE_SHIFT)
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#define DMA_S_HANDSHAKE_D_WAIT (DMA_HANDSHAKE_MODE << DMA_SRC_MODE_SHIFT)
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#define DMA_S_WAIT_D_WAIT (DMA_WAIT_MODE)
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#define DMA_FIFO_SIZE 0x200
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/*
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* define bit index in channel pause register
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*/
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#if defined(AIC_DMA_DRV_V10) || defined(AIC_DMA_DRV_V11) \
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|| defined(AIC_DMA_DRV_V12)
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#define DMA_CH_RESUME 0x00
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#define DMA_CH_PAUSE 0x01
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#endif
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#define DMA_CH_MEMSET 0x10
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#ifdef __cplusplus
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}
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#endif
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#define DMA_SLAVE_DEF(_id, _burst, _width) \
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static const struct dma_slave_table aic_dma_cfg_##_id = { \
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.id = _id, \
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.burst = _burst, \
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.burst_num = ARRAY_SIZE(_burst), \
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.width = _width, \
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.width_num = ARRAY_SIZE(_width), \
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}
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#define AIC_DMA_CFG(_id) [_id] = &(aic_dma_cfg_##_id)
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static const u32 dma_width_1_byte[] = {DMA_SLAVE_BUSWIDTH_1_BYTE};
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static const u32 dma_width_2_bytes[] = {DMA_SLAVE_BUSWIDTH_2_BYTES};
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static const u32 dma_width_4_bytes[] = {DMA_SLAVE_BUSWIDTH_4_BYTES};
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static const u32 dma_width_2_4_bytes[] = {DMA_SLAVE_BUSWIDTH_2_BYTES, DMA_SLAVE_BUSWIDTH_4_BYTES};
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static const u32 dma_width_1_4_bytes[] = {DMA_SLAVE_BUSWIDTH_1_BYTE, DMA_SLAVE_BUSWIDTH_4_BYTES};
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static const u32 dma_burst_1[] = {1};
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static const u32 dma_burst_4[] = {4};
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static const u32 dma_burst_8[] = {8};
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static const u32 dma_burst_16[] = {16};
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static const u32 dma_burst_1_8[] = {1, 8};
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#if defined(AIC_DMA_DRV_V10)
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/* ID burst witdh(byte) */
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DMA_SLAVE_DEF(DMA_ID_PSADC_Q1, dma_burst_1, dma_width_4_bytes);
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DMA_SLAVE_DEF(DMA_ID_PSADC_Q2, dma_burst_1, dma_width_4_bytes);
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DMA_SLAVE_DEF(DMA_ID_SPI2, dma_burst_1_8, dma_width_4_bytes);
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DMA_SLAVE_DEF(DMA_ID_SPI3, dma_burst_1_8, dma_width_4_bytes);
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DMA_SLAVE_DEF(DMA_ID_SPI0, dma_burst_1_8, dma_width_4_bytes);
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DMA_SLAVE_DEF(DMA_ID_SPI1, dma_burst_1_8, dma_width_4_bytes);
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DMA_SLAVE_DEF(DMA_ID_I2S0, dma_burst_1, dma_width_2_4_bytes);
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DMA_SLAVE_DEF(DMA_ID_I2S1, dma_burst_1, dma_width_2_4_bytes);
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DMA_SLAVE_DEF(DMA_ID_AUDIO_DMIC, dma_burst_1, dma_width_2_4_bytes);
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DMA_SLAVE_DEF(DMA_ID_AUDIO_ADC, dma_burst_1, dma_width_2_4_bytes);
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DMA_SLAVE_DEF(DMA_ID_UART0, dma_burst_1, dma_width_1_byte);
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DMA_SLAVE_DEF(DMA_ID_UART1, dma_burst_1, dma_width_1_byte);
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DMA_SLAVE_DEF(DMA_ID_UART2, dma_burst_1, dma_width_1_byte);
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DMA_SLAVE_DEF(DMA_ID_UART3, dma_burst_1, dma_width_1_byte);
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DMA_SLAVE_DEF(DMA_ID_UART4, dma_burst_1, dma_width_1_byte);
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DMA_SLAVE_DEF(DMA_ID_UART5, dma_burst_1, dma_width_1_byte);
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DMA_SLAVE_DEF(DMA_ID_UART6, dma_burst_1, dma_width_1_byte);
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DMA_SLAVE_DEF(DMA_ID_UART7, dma_burst_1, dma_width_1_byte);
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static const struct dma_slave_table *aic_dma_slave_table[AIC_DMA_PORTS] = {
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AIC_DMA_CFG(DMA_ID_PSADC_Q1),
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AIC_DMA_CFG(DMA_ID_PSADC_Q2),
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AIC_DMA_CFG(DMA_ID_SPI2),
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AIC_DMA_CFG(DMA_ID_SPI3),
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AIC_DMA_CFG(DMA_ID_SPI0),
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AIC_DMA_CFG(DMA_ID_SPI1),
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AIC_DMA_CFG(DMA_ID_I2S0),
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AIC_DMA_CFG(DMA_ID_I2S1),
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AIC_DMA_CFG(DMA_ID_AUDIO_DMIC),
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AIC_DMA_CFG(DMA_ID_AUDIO_ADC),
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AIC_DMA_CFG(DMA_ID_UART0),
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AIC_DMA_CFG(DMA_ID_UART1),
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AIC_DMA_CFG(DMA_ID_UART2),
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AIC_DMA_CFG(DMA_ID_UART3),
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AIC_DMA_CFG(DMA_ID_UART4),
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AIC_DMA_CFG(DMA_ID_UART5),
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AIC_DMA_CFG(DMA_ID_UART6),
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AIC_DMA_CFG(DMA_ID_UART7),
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};
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#elif defined(AIC_DMA_DRV_V11)
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/* ID burst witdh(byte)*/
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DMA_SLAVE_DEF(DMA_ID_PSADC_Q1, dma_burst_1, dma_width_4_bytes);
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DMA_SLAVE_DEF(DMA_ID_PSADC_Q2, dma_burst_1, dma_width_4_bytes);
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DMA_SLAVE_DEF(DMA_ID_SPI2, dma_burst_8, dma_width_4_bytes);
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DMA_SLAVE_DEF(DMA_ID_SPI3, dma_burst_8, dma_width_4_bytes);
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DMA_SLAVE_DEF(DMA_ID_SPI0, dma_burst_8, dma_width_4_bytes);
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DMA_SLAVE_DEF(DMA_ID_SPI1, dma_burst_8, dma_width_4_bytes);
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DMA_SLAVE_DEF(DMA_ID_I2S0, dma_burst_1, dma_width_2_4_bytes);
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DMA_SLAVE_DEF(DMA_ID_I2S1, dma_burst_1, dma_width_2_4_bytes);
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DMA_SLAVE_DEF(DMA_ID_AUDIO_DMIC, dma_burst_1, dma_width_2_4_bytes);
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DMA_SLAVE_DEF(DMA_ID_UART0, dma_burst_1, dma_width_1_byte);
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DMA_SLAVE_DEF(DMA_ID_UART1, dma_burst_1, dma_width_1_byte);
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DMA_SLAVE_DEF(DMA_ID_UART2, dma_burst_1, dma_width_1_byte);
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DMA_SLAVE_DEF(DMA_ID_UART3, dma_burst_1, dma_width_1_byte);
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DMA_SLAVE_DEF(DMA_ID_UART4, dma_burst_1, dma_width_1_byte);
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DMA_SLAVE_DEF(DMA_ID_UART5, dma_burst_1, dma_width_1_byte);
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DMA_SLAVE_DEF(DMA_ID_UART6, dma_burst_1, dma_width_1_byte);
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DMA_SLAVE_DEF(DMA_ID_UART7, dma_burst_1, dma_width_1_byte);
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DMA_SLAVE_DEF(DMA_ID_XSPI, dma_burst_16, dma_width_1_byte);
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static const struct dma_slave_table *aic_dma_slave_table[AIC_DMA_PORTS] = {
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AIC_DMA_CFG(DMA_ID_PSADC_Q1),
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AIC_DMA_CFG(DMA_ID_PSADC_Q2),
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AIC_DMA_CFG(DMA_ID_SPI2),
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AIC_DMA_CFG(DMA_ID_SPI3),
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AIC_DMA_CFG(DMA_ID_SPI0),
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AIC_DMA_CFG(DMA_ID_SPI1),
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AIC_DMA_CFG(DMA_ID_I2S0),
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AIC_DMA_CFG(DMA_ID_I2S1),
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AIC_DMA_CFG(DMA_ID_AUDIO_DMIC),
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AIC_DMA_CFG(DMA_ID_UART0),
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AIC_DMA_CFG(DMA_ID_UART1),
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AIC_DMA_CFG(DMA_ID_UART2),
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AIC_DMA_CFG(DMA_ID_UART3),
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AIC_DMA_CFG(DMA_ID_UART4),
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AIC_DMA_CFG(DMA_ID_UART5),
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AIC_DMA_CFG(DMA_ID_UART6),
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AIC_DMA_CFG(DMA_ID_UART7),
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AIC_DMA_CFG(DMA_ID_XSPI),
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};
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#elif defined(AIC_DMA_DRV_V12)
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/* ID burst witdh(byte)*/
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DMA_SLAVE_DEF(DMA_ID_SPI0, dma_burst_8, dma_width_4_bytes);
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DMA_SLAVE_DEF(DMA_ID_SPI1, dma_burst_8, dma_width_4_bytes);
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DMA_SLAVE_DEF(DMA_ID_AUDIO_DMIC, dma_burst_1, dma_width_2_4_bytes);
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DMA_SLAVE_DEF(DMA_ID_UART0, dma_burst_1, dma_width_1_byte);
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DMA_SLAVE_DEF(DMA_ID_UART1, dma_burst_1, dma_width_1_byte);
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DMA_SLAVE_DEF(DMA_ID_UART2, dma_burst_1, dma_width_1_byte);
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DMA_SLAVE_DEF(DMA_ID_UART3, dma_burst_1, dma_width_1_byte);
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DMA_SLAVE_DEF(DMA_ID_XSPI, dma_burst_16, dma_width_1_byte);
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static const struct dma_slave_table *aic_dma_slave_table[AIC_DMA_PORTS] = {
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AIC_DMA_CFG(DMA_ID_SPI0),
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AIC_DMA_CFG(DMA_ID_SPI1),
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AIC_DMA_CFG(DMA_ID_AUDIO_DMIC),
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AIC_DMA_CFG(DMA_ID_UART0),
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AIC_DMA_CFG(DMA_ID_UART1),
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AIC_DMA_CFG(DMA_ID_UART2),
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AIC_DMA_CFG(DMA_ID_UART3),
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AIC_DMA_CFG(DMA_ID_XSPI),
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};
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#endif /* DMA_SLAVE_TABLE */
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struct aic_dma_dev {
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struct aic_dma_task task[TASK_MAX_NUM];
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s32 inited;
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unsigned long base;
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u32 burst_length; /* burst length capacity */
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u32 addr_widths; /* address width support capacity */
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struct aic_dma_chan dma_chan[AIC_DMA_CH_NUM];
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struct aic_dma_task *freetask;
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const struct dma_slave_table **slave_table;
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} __ALIGNED(CACHE_LINE_SIZE);
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struct aic_dma_dev *get_aic_dma_dev(void);
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void *aic_dma_task_add(struct aic_dma_task *prev,
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struct aic_dma_task *next,
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struct aic_dma_chan *chan);
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int aic_set_burst(struct dma_slave_config *sconfig,
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enum dma_transfer_direction direction,
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u32 *p_cfg);
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struct aic_dma_task *aic_dma_task_alloc(void);
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void aic_dma_free_desc(struct aic_dma_chan *chan);
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#endif /*_ARTINCHIP_HAL_DMA_REG_V1X_H_ */
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