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v1.0.3

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刘可亮
2024-01-27 08:47:24 +08:00
parent d3bd993b5f
commit 9f7ba67007
2345 changed files with 74421 additions and 76616 deletions
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18
kernel/rt-thread/libcpu/risc-v/artinchip/c906/context_gcc.S
View File

@@ -31,6 +31,16 @@ vPortYield:
or t1, t1, t2
sb t1, (t0)
/* make sure wite instruction is complete */
fence
lw t1, (t0)
fence
#ifdef __riscv_xthead
sync.is
#else
.long 0x01b0000b
#endif
ret
/*
@@ -67,7 +77,11 @@ rt_hw_context_switch_to:
fence
lw t1, (t0)
fence
#ifdef __riscv_xthead
sync.is
#else
.long 0x01b0000b
#endif
/* enable global interrup */
csrsi mstatus, 8
@@ -120,7 +134,11 @@ rt_hw_context_switch_interrupt:
fence
lw t1, (t0)
fence
#ifdef __riscv_xthead
sync.is
#else
.long 0x01b0000b
#endif
LOAD t0, 0 * REGBYTES(sp)
LOAD t1, 1 * REGBYTES(sp)

18
kernel/rt-thread/libcpu/risc-v/artinchip/e9xx/context_gcc.S
View File

@@ -31,6 +31,16 @@ vPortYield:
or t1, t1, t2
sb t1, (t0)
/* make sure wite instruction is complete */
fence
lb t1, (t0)
fence
#ifdef __riscv_xthead
sync.i
#else
.long 0x01a0000b
#endif
ret
/*
@@ -75,7 +85,11 @@ rt_hw_context_switch_to:
fence
lb t1, (t0)
fence
#ifdef __riscv_xthead
sync.i
#else
.long 0x01a0000b
#endif
/* enable global interrup */
csrsi mstatus, 8
@@ -130,7 +144,11 @@ rt_hw_context_switch_interrupt:
fence
lb t1, (t0)
fence
#ifdef __riscv_xthead
sync.i
#else
.long 0x01a0000b
#endif
LOAD t0, 0 * REGBYTES(sp)
LOAD t1, 1 * REGBYTES(sp)