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v1.0.3

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刘可亮
2024-01-27 08:47:24 +08:00
parent d3bd993b5f
commit 9f7ba67007
2345 changed files with 74421 additions and 76616 deletions
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207
packages/third-party/cherryusb/port/dwc2/usb_dc_dwc2.c vendored
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@@ -51,28 +51,19 @@
#endif
// clang-format on
#define FS_PORT 0
#define HS_PORT 1
#ifndef CONFIG_USB_DWC2_PORT
#error "please select CONFIG_USB_DWC2_PORT with FS_PORT or HS_PORT"
#endif
#if CONFIG_USB_DWC2_PORT == FS_PORT
#ifndef USBD_IRQHandler
#define USBD_IRQHandler OTG_FS_IRQHandler
#error "please define USBD_IRQHandler in usb_config.h"
#endif
#ifndef USB_BASE
#ifdef STM32H7
#define USB_BASE (0x40080000UL)
#else
#define USB_BASE (0x50000000UL)
#endif
#ifndef USBD_BASE
#error "please define USBD_BASE in usb_config.h"
#endif
#define USB_RAM_SIZE 1280 /* define with minimum value*/
#ifndef CONFIG_USB_DWC2_RAM_SIZE
#error "please define CONFIG_USB_DWC2_RAM_SIZE in usb_config.h, only support 1280 or 4096"
#endif
#if CONFIG_USB_DWC2_RAM_SIZE == 1280
/*FIFO sizes in bytes (total available memory for FIFOs is 1.25KB )*/
#ifndef CONFIG_USB_DWC2_RX_FIFO_SIZE
#define CONFIG_USB_DWC2_RX_FIFO_SIZE (512)
@@ -102,29 +93,17 @@
#define CONFIG_USB_DWC2_TX5_FIFO_SIZE (128)
#endif
#ifndef USB_NUM_BIDIR_ENDPOINTS
#define USB_NUM_BIDIR_ENDPOINTS 4 /* define with minimum value*/
#ifndef CONFIG_USBDEV_EP_NUM
#define CONFIG_USBDEV_EP_NUM 4 /* define with minimum value*/
#endif
#else
#elif CONFIG_USB_DWC2_RAM_SIZE == 4096
#ifndef USBD_IRQHandler
#define USBD_IRQHandler OTG_HS_IRQHandler
#endif
#ifndef USB_BASE
#define USB_BASE (0x40040000UL)
#endif
#define USB_RAM_SIZE 4096 /* define with minimum value*/
#define CONFIG_USB_DWC2_DMA_ENABLE
//#define CONFIG_USB_DWC2_DMA_ENABLE
#ifdef CONFIG_USB_DWC2_DMA_ENABLE
#if defined(STM32F7) || defined(STM32H7)
#warning "if you enable dcache,please add .nocacheble section in your sct or ld or icf"
#endif
#endif
/*FIFO sizes in bytes (total available memory for FIFOs is 4KB )*/
#ifndef CONFIG_USB_DWC2_RX_FIFO_SIZE
@@ -155,18 +134,20 @@
#define CONFIG_USB_DWC2_TX5_FIFO_SIZE (256)
#endif
#ifndef USB_NUM_BIDIR_ENDPOINTS
#define USB_NUM_BIDIR_ENDPOINTS 6 /* define with minimum value*/
#ifndef CONFIG_USBDEV_EP_NUM
#define CONFIG_USBDEV_EP_NUM 6 /* define with minimum value*/
#endif
#else
#error "Unsupported CONFIG_USB_DWC2_RAM_SIZE value"
#endif
#define USB_OTG_GLB ((USB_OTG_GlobalTypeDef *)(USB_BASE))
#define USB_OTG_DEV ((USB_OTG_DeviceTypeDef *)(USB_BASE + USB_OTG_DEVICE_BASE))
#define USB_OTG_PCGCCTL *(__IO uint32_t *)((uint32_t)USB_BASE + USB_OTG_PCGCCTL_BASE)
#define USB_OTG_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USB_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i)*USB_OTG_EP_REG_SIZE)))
#define USB_OTG_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USB_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i)*USB_OTG_EP_REG_SIZE)))
#define USB_OTG_FIFO(i) *(__IO uint32_t *)(USB_BASE + USB_OTG_FIFO_BASE + ((i)*USB_OTG_FIFO_SIZE))
#define USB_OTG_GLB ((USB_OTG_GlobalTypeDef *)(USBD_BASE))
#define USB_OTG_DEV ((USB_OTG_DeviceTypeDef *)(USBD_BASE + USB_OTG_DEVICE_BASE))
#define USB_OTG_PCGCCTL *(__IO uint32_t *)((uint32_t)USBD_BASE + USB_OTG_PCGCCTL_BASE)
#define USB_OTG_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBD_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i)*USB_OTG_EP_REG_SIZE)))
#define USB_OTG_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBD_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i)*USB_OTG_EP_REG_SIZE)))
#define USB_OTG_FIFO(i) *(__IO uint32_t *)(USBD_BASE + USB_OTG_FIFO_BASE + ((i)*USB_OTG_FIFO_SIZE))
extern uint32_t SystemCoreClock;
@@ -183,8 +164,8 @@ struct dwc2_ep_state {
/* Driver state */
USB_NOCACHE_RAM_SECTION struct dwc2_udc {
__attribute__((aligned(32))) struct usb_setup_packet setup;
struct dwc2_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters*/
struct dwc2_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */
struct dwc2_ep_state in_ep[CONFIG_USBDEV_EP_NUM]; /*!< IN endpoint parameters*/
struct dwc2_ep_state out_ep[CONFIG_USBDEV_EP_NUM]; /*!< OUT endpoint parameters */
} g_dwc2_udc;
static inline int dwc2_reset(void)
@@ -215,8 +196,6 @@ static inline int dwc2_core_init(void)
{
int ret;
#if defined(CONFIG_USB_HS)
USB_OTG_GLB->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
/* Init The ULPI Interface */
USB_OTG_GLB->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
@@ -231,8 +210,6 @@ static inline int dwc2_core_init(void)
/* Reset after a PHY select */
ret = dwc2_reset();
/* Activate the USB Transceiver */
USB_OTG_GLB->GCCFG |= USB_OTG_GCCFG_PWRDWN;
#endif
return ret;
}
@@ -325,14 +302,17 @@ static void dwc2_set_turnaroundtime(uint32_t hclk, uint8_t speed)
UsbTrd = USBD_DEFAULT_TRDT_VALUE;
}
USB_OTG_GLB->GUSBCFG |= USB_OTG_GUSBCFG_TOCAL;
USB_OTG_GLB->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
USB_OTG_GLB->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT);
USB_OTG_GLB->GUSBCFG |= (uint32_t)((UsbTrd << USB_OTG_GUSBCFG_TRDT_Pos) & USB_OTG_GUSBCFG_TRDT);
}
static void dwc2_set_txfifo(uint8_t fifo, uint16_t size)
{
uint8_t i;
uint32_t Tx_Offset;
uint32_t Tx_Size;
/* TXn min size = 16 words. (n : Transmit FIFO index)
When a TxFIFO is not used, the Configuration should be as follows:
@@ -348,6 +328,7 @@ static void dwc2_set_txfifo(uint8_t fifo, uint16_t size)
if (fifo == 0U) {
USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;
Tx_Size = USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ;
} else {
Tx_Offset += (USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ) >> 16;
for (i = 0U; i < (fifo - 1U); i++) {
@@ -356,7 +337,11 @@ static void dwc2_set_txfifo(uint8_t fifo, uint16_t size)
/* Multiply Tx_Size by 2 to get higher performance */
USB_OTG_GLB->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;
Tx_Size = USB_OTG_GLB->DIEPTXF[fifo - 1U];
}
USB_LOG_INFO("fifo-%02d size:%04d %08x\n", fifo, size, Tx_Size);
}
static uint8_t dwc2_get_devspeed(void)
@@ -567,6 +552,7 @@ int usb_dc_init(void)
endpoints = ((USB_OTG_GLB->GHWCFG2 & (0x0f << 10)) >> 10) + 1;
USB_LOG_INFO("========== dwc2 udc params ==========\r\n");
USB_LOG_INFO("GCCFG:%08x\r\n", USB_OTG_GLB->GCCFG);
USB_LOG_INFO("CID:%08x\r\n", USB_OTG_GLB->CID);
USB_LOG_INFO("GSNPSID:%08x\r\n", USB_OTG_GLB->GSNPSID);
USB_LOG_INFO("GHWCFG1:%08x\r\n", USB_OTG_GLB->GHWCFG1);
@@ -575,69 +561,54 @@ int usb_dc_init(void)
USB_LOG_INFO("GHWCFG4:%08x\r\n", USB_OTG_GLB->GHWCFG4);
USB_LOG_INFO("dwc2 fsphy type:%d, hsphy type:%d, dma support:%d\r\n", fsphy_type, hsphy_type, dma_support);
USB_LOG_INFO("dwc2 has %d endpoints, default config: %d endpoints\r\n", endpoints, USB_NUM_BIDIR_ENDPOINTS);
USB_LOG_INFO("dwc2 has %d endpoints, default config: %d endpoints\r\n", endpoints, CONFIG_USBDEV_EP_NUM);
USB_LOG_INFO("=================================\r\n");
if (endpoints < CONFIG_USBDEV_EP_NUM) {
USB_LOG_ERR("dwc2 has less endpoints than config, please check\r\n");
while (1) {
}
}
if ((hsphy_type == 0) && (CONFIG_USB_DWC2_RAM_SIZE != 1280)) {
USB_LOG_ERR("dwc2 hsphy type is 0, but ram size is not 1280, please check\r\n");
while (1) {
}
}
USB_OTG_DEV->DCTL |= USB_OTG_DCTL_SDIS;
USB_OTG_GLB->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
/* This is vendor register */
USB_OTG_GLB->GCCFG = usbd_get_dwc2_gccfg_conf();
ret = dwc2_core_init();
/* Force Device Mode*/
dwc2_set_mode(USB_OTG_MODE_DEVICE);
/* B-peripheral session valid override enable */
// USB_OTG_GLB->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
// USB_OTG_GLB->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
for (uint8_t i = 0U; i < 15U; i++) {
USB_OTG_GLB->DIEPTXF[i] = 0U;
}
#if defined(STM32F7) || defined(STM32H7) || defined(STM32L4)
#ifdef CONFIG_DWC2_VBUS_SENSING_ENABLE
/* Enable HW VBUS sensing */
USB_OTG_GLB->GCCFG |= USB_OTG_GCCFG_VBDEN;
#else
/* Deactivate VBUS Sensing B */
USB_OTG_GLB->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
/* B-peripheral session valid override enable */
USB_OTG_GLB->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
USB_OTG_GLB->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
#endif
#else
#ifdef CONFIG_DWC2_VBUS_SENSING_ENABLE
/* Enable HW VBUS sensing */
USB_OTG_GLB->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
USB_OTG_GLB->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
#else
#ifdef CONFIG_DWC2_GD32
USB_OTG_GLB->GCCFG |= USB_OTG_GCCFG_VBUSBSEN | USB_OTG_GCCFG_VBUSASEN;
#else
/*
* Disable HW VBUS sensing. VBUS is internally considered to be always
* at VBUS-Valid level (5V).
*/
USB_OTG_GLB->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
USB_OTG_GLB->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
USB_OTG_GLB->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
#endif
#endif
#endif
/* Restart the Phy Clock */
USB_OTG_PCGCCTL = 0U;
/* Device mode configuration */
USB_OTG_DEV->DCFG |= DCFG_FRAME_INTERVAL_80;
#if CONFIG_USB_DWC2_PORT == HS_PORT
/* Device speed configuration */
USB_OTG_DEV->DCFG &= ~USB_OTG_DCFG_DSPD;
#if defined(CONFIG_USB_HS)
/* Set Core speed to High speed mode */
USB_OTG_DEV->DCFG |= USB_OTG_SPEED_HIGH;
#else
USB_OTG_DEV->DCFG |= USB_OTG_SPEED_HIGH_IN_FULL;
#endif
#else
USB_OTG_DEV->DCFG |= USB_OTG_SPEED_FULL;
if (hsphy_type == 0) {
USB_OTG_DEV->DCFG |= USB_OTG_SPEED_FULL;
} else {
USB_OTG_DEV->DCFG |= USB_OTG_SPEED_HIGH_IN_FULL;
}
#endif
ret = dwc2_flush_txfifo(0x10U);
@@ -665,8 +636,9 @@ int usb_dc_init(void)
}
}
USB_OTG_GLB->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
USB_OTG_GLB->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
USB_OTG_DEV->DCFG &= ~USB_OTG_DCFG_DESCDMA;
USB_OTG_GLB->GAHBCFG |= (USB_OTG_GAHBCFG_DMAEN | USB_OTG_GAHBCFG_HBSTLEN_2);
#else
USB_OTG_GLB->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
#endif
@@ -683,11 +655,20 @@ int usb_dc_init(void)
dwc2_set_txfifo(1, CONFIG_USB_DWC2_TX1_FIFO_SIZE / 4);
dwc2_set_txfifo(2, CONFIG_USB_DWC2_TX2_FIFO_SIZE / 4);
dwc2_set_txfifo(3, CONFIG_USB_DWC2_TX3_FIFO_SIZE / 4);
#if USB_NUM_BIDIR_ENDPOINTS > 4
#if CONFIG_USBDEV_EP_NUM > 4
dwc2_set_txfifo(4, CONFIG_USB_DWC2_TX4_FIFO_SIZE / 4);
#endif
#if USB_NUM_BIDIR_ENDPOINTS > 5
#if CONFIG_USBDEV_EP_NUM > 5
dwc2_set_txfifo(5, CONFIG_USB_DWC2_TX5_FIFO_SIZE / 4);
#endif
#if CONFIG_USBDEV_EP_NUM > 6
dwc2_set_txfifo(6, CONFIG_USB_DWC2_TX6_FIFO_SIZE / 4);
#endif
#if CONFIG_USBDEV_EP_NUM > 7
dwc2_set_txfifo(7, CONFIG_USB_DWC2_TX7_FIFO_SIZE / 4);
#endif
#if CONFIG_USBDEV_EP_NUM > 8
dwc2_set_txfifo(8, CONFIG_USB_DWC2_TX8_FIFO_SIZE / 4);
#endif
USB_OTG_GLB->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
USB_OTG_DEV->DCTL &= ~USB_OTG_DCTL_SDIS;
@@ -697,7 +678,6 @@ int usb_dc_init(void)
int usb_dc_deinit(void)
{
usb_dc_low_level_deinit();
/* Clear Pending interrupt */
for (uint8_t i = 0U; i < 15U; i++) {
USB_OTG_INEP(i)->DIEPINT = 0xFB7FU;
@@ -715,6 +695,7 @@ int usb_dc_deinit(void)
USB_OTG_DEV->DCTL |= USB_OTG_DCTL_SDIS;
usb_dc_low_level_deinit();
return 0;
}
@@ -742,36 +723,36 @@ uint8_t usbd_get_port_speed(const uint8_t port)
return speed;
}
int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg)
int usbd_ep_open(const struct usb_endpoint_descriptor *ep)
{
uint8_t ep_idx = USB_EP_GET_IDX(ep_cfg->ep_addr);
uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress);
if (ep_idx > (USB_NUM_BIDIR_ENDPOINTS - 1)) {
USB_LOG_ERR("Ep addr %d overflow\r\n", ep_cfg->ep_addr);
if (ep_idx > (CONFIG_USBDEV_EP_NUM - 1)) {
USB_LOG_ERR("Ep addr %02x overflow\r\n", ep->bEndpointAddress);
return -1;
}
if (USB_EP_DIR_IS_OUT(ep_cfg->ep_addr)) {
g_dwc2_udc.out_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
g_dwc2_udc.out_ep[ep_idx].ep_type = ep_cfg->ep_type;
if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) {
g_dwc2_udc.out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
g_dwc2_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes);
USB_OTG_DEV->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & (uint32_t)(1UL << (16 + ep_idx));
if ((USB_OTG_OUTEP(ep_idx)->DOEPCTL & USB_OTG_DOEPCTL_USBAEP) == 0) {
USB_OTG_OUTEP(ep_idx)->DOEPCTL |= (ep_cfg->ep_mps & USB_OTG_DOEPCTL_MPSIZ) |
((uint32_t)ep_cfg->ep_type << 18) |
USB_OTG_OUTEP(ep_idx)->DOEPCTL |= (USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize) & USB_OTG_DOEPCTL_MPSIZ) |
((uint32_t)USB_GET_ENDPOINT_TYPE(ep->bmAttributes) << 18) |
USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
USB_OTG_DOEPCTL_USBAEP;
}
} else {
g_dwc2_udc.in_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
g_dwc2_udc.in_ep[ep_idx].ep_type = ep_cfg->ep_type;
g_dwc2_udc.in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
g_dwc2_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes);
USB_OTG_DEV->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << ep_idx);
if ((USB_OTG_INEP(ep_idx)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0) {
USB_OTG_INEP(ep_idx)->DIEPCTL |= (ep_cfg->ep_mps & USB_OTG_DIEPCTL_MPSIZ) |
((uint32_t)ep_cfg->ep_type << 18) | (ep_idx << 22) |
USB_OTG_INEP(ep_idx)->DIEPCTL |= (USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize) & USB_OTG_DIEPCTL_MPSIZ) |
((uint32_t)USB_GET_ENDPOINT_TYPE(ep->bmAttributes) << 18) | (ep_idx << 22) |
USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
USB_OTG_DIEPCTL_USBAEP;
}
@@ -821,7 +802,7 @@ int usbd_ep_close(const uint8_t ep)
/* Clear and unmask endpoint disabled interrupt */
USB_OTG_INEP(ep_idx)->DIEPINT |= USB_OTG_DIEPINT_EPDISD;
}
USB_OTG_DEV->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep_idx & 0x07)));
USB_OTG_DEV->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep_idx & 0x07)));
USB_OTG_INEP(ep_idx)->DIEPCTL = 0;
@@ -888,9 +869,11 @@ int usbd_ep_start_write(const uint8_t ep, const uint8_t *data, uint32_t data_len
if (!data && data_len) {
return -1;
}
#if 0 /* some chips have confused with this, so disable as default */
if (USB_OTG_INEP(ep_idx)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) {
return -2;
}
#endif
if (ep_idx && !(USB_OTG_INEP(ep_idx)->DIEPCTL & USB_OTG_DIEPCTL_MPSIZ)) {
return -3;
}
@@ -959,9 +942,11 @@ int usbd_ep_start_read(const uint8_t ep, uint8_t *data, uint32_t data_len)
if (!data && data_len) {
return -1;
}
#if 0 /* some chips have confused with this, so disable as default */
if (USB_OTG_OUTEP(ep_idx)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) {
return -2;
}
#endif
if (ep_idx && !(USB_OTG_OUTEP(ep_idx)->DOEPCTL & USB_OTG_DOEPCTL_MPSIZ)) {
return -3;
}
@@ -1123,7 +1108,7 @@ void USBD_IRQHandler(void)
dwc2_flush_txfifo(0x10U);
dwc2_flush_rxfifo();
for (uint8_t i = 0U; i < USB_NUM_BIDIR_ENDPOINTS; i++) {
for (uint8_t i = 0U; i < CONFIG_USBDEV_EP_NUM; i++) {
if (i == 0U) {
USB_OTG_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
USB_OTG_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
@@ -1167,7 +1152,7 @@ void USBD_IRQHandler(void)
daintmask = USB_OTG_DEV->DAINTMSK;
daintmask >>= 16;
for (ep_idx = 1; ep_idx < USB_NUM_BIDIR_ENDPOINTS; ep_idx++) {
for (ep_idx = 1; ep_idx < CONFIG_USBDEV_EP_NUM; ep_idx++) {
if ((BIT(ep_idx) & ~daintmask) || (g_dwc2_udc.out_ep[ep_idx].ep_type != USB_ENDPOINT_TYPE_ISOCHRONOUS))
continue;
if (!(USB_OTG_OUTEP(ep_idx)->DOEPCTL & USB_OTG_DOEPCTL_USBAEP))
@@ -1189,7 +1174,7 @@ void USBD_IRQHandler(void)
daintmask = USB_OTG_DEV->DAINTMSK;
daintmask >>= 16;
for (ep_idx = 1; ep_idx < USB_NUM_BIDIR_ENDPOINTS; ep_idx++) {
for (ep_idx = 1; ep_idx < CONFIG_USBDEV_EP_NUM; ep_idx++) {
if (((BIT(ep_idx) & ~daintmask)) || (g_dwc2_udc.in_ep[ep_idx].ep_type != USB_ENDPOINT_TYPE_ISOCHRONOUS))
continue;