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V1.0.5

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刘可亮
2024-07-09 15:46:51 +08:00
parent ac4afe16c9
commit cf270df8d6
3 changed files with 0 additions and 3 deletions
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1
bsp/artinchip/sys/d12x/vectors.S
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@@ -154,7 +154,6 @@ Default_IRQHandler:
.type trap, %function .type trap, %function
trap: trap:
/* Check for interrupt */ /* Check for interrupt */
j .
addi sp, sp, -4 addi sp, sp, -4
sw t0, 0x0(sp) sw t0, 0x0(sp)
csrr t0, mcause csrr t0, mcause

1
bsp/artinchip/sys/d13x/vectors.S
View File

@@ -154,7 +154,6 @@ Default_IRQHandler:
.type trap, %function .type trap, %function
trap: trap:
/* Check for interrupt */ /* Check for interrupt */
j .
addi sp, sp, -4 addi sp, sp, -4
sw t0, 0x0(sp) sw t0, 0x0(sp)
csrr t0, mcause csrr t0, mcause

1
bsp/artinchip/sys/g73x/vectors.S
View File

@@ -154,7 +154,6 @@ Default_IRQHandler:
.type trap, %function .type trap, %function
trap: trap:
/* Check for interrupt */ /* Check for interrupt */
j .
addi sp, sp, -4 addi sp, sp, -4
sw t0, 0x0(sp) sw t0, 0x0(sp)
csrr t0, mcause csrr t0, mcause