/*
 * Copyright (C) 2025, ArtInChip Technology Co., Ltd
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Authors:  Huahui <huahui.mai@artinchip.com>
 */

#include <rtdevice.h>
#include "lv_aic_spi.h"

#define GC9D01N_RST_PIN  "PB.11"

void lv_spi_panel_enable(struct lv_spi_dev *dev)
{
    u32 rst_pin;

    rst_pin = rt_pin_get(GC9D01N_RST_PIN);
    rt_pin_mode(rst_pin, PIN_MODE_OUTPUT);

    rt_pin_write(rst_pin, 1);
    rt_thread_mdelay(120);

    lv_spi_write_seq(dev, 0xFE);
    lv_spi_write_seq(dev, 0xEF);
    lv_spi_write_seq(dev, 0x80, 0xFF);
    lv_spi_write_seq(dev, 0x81, 0xFF);
    lv_spi_write_seq(dev, 0x82, 0xFF);
    lv_spi_write_seq(dev, 0x83, 0xFF);
    lv_spi_write_seq(dev, 0x84, 0xFF);
    lv_spi_write_seq(dev, 0x85, 0xFF);
    lv_spi_write_seq(dev, 0x86, 0xFF);
    lv_spi_write_seq(dev, 0x87, 0xFF);
    lv_spi_write_seq(dev, 0x88, 0xFF);
    lv_spi_write_seq(dev, 0x89, 0xFF);
    lv_spi_write_seq(dev, 0x8A, 0xFF);
    lv_spi_write_seq(dev, 0x8B, 0xFF);
    lv_spi_write_seq(dev, 0x8C, 0xFF);
    lv_spi_write_seq(dev, 0x8D, 0xFF);
    lv_spi_write_seq(dev, 0x8E, 0xFF);
    lv_spi_write_seq(dev, 0x8F, 0xFF);
    lv_spi_write_seq(dev, 0x3A, 0x05);
    lv_spi_write_seq(dev, 0xEC, 0x01);
    lv_spi_write_seq(dev, 0x74, 0x02, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00);
    lv_spi_write_seq(dev, 0x98, 0x3E);
    lv_spi_write_seq(dev, 0x99, 0x3E);
    lv_spi_write_seq(dev, 0xB5, 0x0D, 0x0D);
    lv_spi_write_seq(dev, 0x60, 0x38, 0x0F, 0x79, 0x67);
    lv_spi_write_seq(dev, 0x61, 0x38, 0x11, 0x79, 0x67);
    lv_spi_write_seq(dev, 0x64, 0x38, 0x17, 0x71, 0x5F, 0x79, 0x67);
    lv_spi_write_seq(dev, 0x65, 0x38, 0x13, 0x71, 0x5B, 0x79, 0x67);
    lv_spi_write_seq(dev, 0x6A, 0x00, 0x00);
    lv_spi_write_seq(dev, 0x6C, 0x22, 0x02, 0x22, 0x02, 0x22, 0x22, 0x50);
    lv_spi_write_seq(dev, 0x6E, 0x03, 0x03, 0x01, 0x01, 0x00, 0x00, 0x0f, 0x0f, 0x0d, 0x0d, 0x0b,
                          0x0b, 0x09, 0x09, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x0a, 0x0c, 0x0c, 0x0e,
                          0x0e, 0x10, 0x10, 0x00, 0x00, 0x02, 0x02, 0x04, 0x04);
    lv_spi_write_seq(dev, 0xbf, 0x01);
    lv_spi_write_seq(dev, 0xF9, 0x40);
    lv_spi_write_seq(dev, 0x9b, 0x3b);
    lv_spi_write_seq(dev, 0x93, 0x33, 0x7f, 0x00);
    lv_spi_write_seq(dev, 0x7E, 0x30);
    lv_spi_write_seq(dev, 0x70, 0x0d, 0x02, 0x08, 0x0d, 0x02, 0x08);
    lv_spi_write_seq(dev, 0x71, 0x0d, 0x02, 0x08);
    lv_spi_write_seq(dev, 0x91, 0x0E, 0x09);
    lv_spi_write_seq(dev, 0xc3, 0x18);
    lv_spi_write_seq(dev, 0xc4, 0x18);
    lv_spi_write_seq(dev, 0xc9, 0x3c);
    lv_spi_write_seq(dev, 0xf0, 0x13, 0x15, 0x04, 0x05, 0x01, 0x38);
    lv_spi_write_seq(dev, 0xf2, 0x13, 0x15, 0x04, 0x05, 0x01, 0x34);
    lv_spi_write_seq(dev, 0xf1, 0x4b, 0xb8, 0x7b, 0x34, 0x35, 0xef);
    lv_spi_write_seq(dev, 0xf3, 0x47, 0xb4, 0x72, 0x34, 0x35, 0xda);
    lv_spi_write_seq(dev, 0x36, 0x00);

    lv_spi_write_seq(dev, 0x11);
    rt_thread_mdelay(120);
    lv_spi_write_seq(dev, 0x29);
    rt_thread_mdelay(20);
}