/**************************************************************** ** ** COMPONENT: Master_register_map ** ** MODULE: $Workfile: phy_regs.h $ ** ** SCRIPT VERSION: $Revision: 1.14 n** ** MASTER SPREADSHEET VERSION: 1.134 ** ** DATED: $Date: 2008/07/02 15:40:32 $ ** ** AUTHOR: Auto-generated ** ** DESCRIPTION: Auto-generated headers for PHY setup ** ** ** LAST MODIFIED BY: $ Author: argbdemi $ ** ****************************************************************** * * Copyright (c) 2008 altobeam R & D Ltd. * *****************************************************************/ #ifndef __PHY_REGS_H__ #define __PHY_REGS_H__ #define PHY_RDT_BASE_ADDR 0x0ac00000 #define PHY_RDF_BASE_ADDR 0x0ac00000 #define PHY_RDC_BASE_ADDR 0x0ac00000 #define PHY_BBDIG_BASE_ADDR 0x0ac00000 #define PHY_PRM_BASE_ADDR 0x0ac00000 #define PHY_RRM_BASE_ADDR 0x0ac00000 #define PHY_PHY_BASE_ADDR 0x0ac00000 #define BBDIG_BASE_ADDR (PHY_PHY_BASE_ADDR + 0x0038000) #define RFIP_BASE_ADDR (PHY_PHY_BASE_ADDR + 0x00c0000) #define PHY_RDT_NRDTCTRL (0x00000000 + PHY_RDT_BASE_ADDR) // Receive Time Synchronizer Control Register #define PHY_RDT_NRCFOEST (0x00000030 + PHY_RDT_BASE_ADDR) // Receive CFO Estimate Register #define PHY_RDT_NRDCEST (0x00000038 + PHY_RDT_BASE_ADDR) // Receive DC Offset Estimate Register #define PHY_RDT_NRDAGCGAIN (0x0000004c + PHY_RDT_BASE_ADDR) // Receive Digital AGC Gain Register #define PHY_RDT_NRSYNCFCM_1 (0x0000011c + PHY_RDT_BASE_ADDR) // Receive Sync. Frame Capture Metrics Register_1 TEST #define PHY_RDT_NRSYNCFCM_2 (0x00000120 + PHY_RDT_BASE_ADDR) // Receive Sync. Frame Capture Metrics Register_2 TEST #define PHY_RDT_NRSYNCFCM_3 (0x00000124 + PHY_RDT_BASE_ADDR) // Receive Sync. Frame Capture Metrics Register_3 TEST #define PHY_RDT_NRSYNCFCM_4 (0x00000128 + PHY_RDT_BASE_ADDR) // Receive Sync. Frame Capture Metrics Register_4 TEST #define PHY_RDT_NRSYNCFCM_5 (0x0000012c + PHY_RDT_BASE_ADDR) // Receive Sync. Frame Capture Metrics Register_5 TEST #define PHY_RDT_NRSYNCFCM_6 (0x00000130 + PHY_RDT_BASE_ADDR) // Receive Sync. Frame Capture Metrics Register_6 TEST #define PHY_RDT_NRAGCFCMAG (0x00000420 + PHY_RDT_BASE_ADDR) // AGC Frame Capture Metrics Analog Gain Register TEST #define PHY_RDT_NRCCAFCM_1 (0x00000c40 + PHY_RDT_BASE_ADDR) // CCA Frame Capture Metrics Register TEST #define PHY_RDF_NREVM (0x00008054 + PHY_RDF_BASE_ADDR) // Receive EVM Measurement Register TEST #define PHY_RDC_NRFCMRDC1 (0x0001004c | PHY_RDC_BASE_ADDR) // Receive Frame Capture Metrics Register_1 TEST #define PHY_RDC_NRFCMRDC2 (0x00010050 | PHY_RDC_BASE_ADDR) // Receive Frame Capture Metrics Register_2 TEST #define PHY_RDT_NRGAINIMB (0x00080234 + PHY_RDT_BASE_ADDR) // Receive I/Q Update Gain Imbalance Register AC80234[9:0] #define PHY_RDT_NRPHASEIMB (0x00080234 + PHY_RDT_BASE_ADDR) // Receive I/Q Update Phase Imbalance Register AC80234[19:10] #define PHY_RDT_NRAGCGAIN_BASE_ADDR (0x00080800 + PHY_RDT_BASE_ADDR) // Receive AGC Gains Lookup Table /*如果使用table中的配置的mode. 需要配置force_response_mode[6:2]相应bit为1’h1 0 GF_MODE 1:MM_MODE 2: LEG_MODE 3: DSSS_LONG 4: DSSS_SHORT*/ #define PHY_FORCE_RESPONSE_MODE (0x9c00820) //for athenaB #define PHY_PARAMS_PRIMARY_CHANNEL_IS_UPPER_FLAG (0xAC3894C) //prc_coeff_imag[11:0],prc_coeff_real[11:0] #define PHY_PRC_COEFF_BASE_ADDR (0xACA2000) #define PHY_BBDIG_APB_MEM (0xACB89AC) #define PHY_BBDIG_APB_RAM_BASE_ADDR (0xACBD000) //siir_search min_correlation_thr，减少虚警 #define PHY_MIN_CORRELATION_THR (0xAC801C0) #define PHY_RDT_NRCCACFG (0x00000c00 + PHY_RDT_BASE_ADDR) // Receive CCA Configuration Register #define PHY_RDT_NRDFRTHR (0x00000c08 + PHY_RDT_BASE_ADDR) // Receive Defer Threshold Register #define PHY_RDT_NRRSSI (0x00000c18 + PHY_RDT_BASE_ADDR) // Receive Signal Strength Register TEST #define PHY_RDT_NRNEFILT (0x00000c1c + PHY_RDT_BASE_ADDR) // Receive Noise Estimation Filter Register #define PHY_RDT_NRNECFG (0x00000c24 + PHY_RDT_BASE_ADDR) // Receive Noise Estimator Configuration Register #define PHY_RDT_NRNLEVEL (0x00000c28 + PHY_RDT_BASE_ADDR) // Receive Noise Level Estimate Register #define PHY_RDT_NRNLEVELDBM (0x00000c50 + PHY_RDT_BASE_ADDR) // Instantaneous noise level in dBm #define PHY_RDF_NRDPLLCFOINITVALST (0x0000802c + PHY_RDF_BASE_ADDR) // Receive DPLL CFO Initial Value Status Register TEST #define PHY_RDF_NRFDMCTRL (0x00008048 + PHY_RDF_BASE_ADDR) // Receive Frequency Domain Monitor Control Register #define PHY_RDF_NRFDMST (0x0000804c + PHY_RDF_BASE_ADDR) // Receive Frequency Domain Monitor Status Register #define PHY_RDF_NRMDETST (0x00008060 + PHY_RDF_BASE_ADDR) // Receive Mode Detector Status Register TEST #define PHY_RDF_NRDPLLEVMN21ST (0x0000806c + PHY_RDF_BASE_ADDR) // Receive DPLL EVM N21 Status Register TEST #define PHY_RDF_NRDPLLEVMN7ST (0x00008070 + PHY_RDF_BASE_ADDR) // Receive DPLL EVM N7 Status Register TEST #define PHY_RDF_NRDPLLEVMP7ST (0x00008074 + PHY_RDF_BASE_ADDR) // Receive DPLL EVM P7 Status Register TEST #define PHY_RDF_NRDPLLEVMP21ST (0x00008078 + PHY_RDF_BASE_ADDR) // Receive DPLL EVM P21 Status Register TEST #define PHY_RDC_NRRDCCTRL (0x00010004 + PHY_RDC_BASE_ADDR) // #define PHY_RDC_NRDESCRSEED (0x00010010 + PHY_RDC_BASE_ADDR) // Receive DeScrambler Seed #define PHY_RDC_NRERRST (0x0001001c + PHY_RDC_BASE_ADDR) // Receive Error Status Register TEST #define PHY_BBDIG_RICTRL (0x00038004 + PHY_BBDIG_BASE_ADDR) // Radio Interface control register #define PHY_BBDIG_RITXCTRL (0x00038008 + PHY_BBDIG_BASE_ADDR) // Transmit Controller register #define PHY_BBDIG_RIALCCTL (0x0003800c + PHY_BBDIG_BASE_ADDR) // Transmit ALC Control register #define PHY_BBDIG_RIALCDSSS (0x00038010 + PHY_BBDIG_BASE_ADDR) // Transmit ALC DSSS Accumulator register #define PHY_BBDIG_RIALCOFDM (0x00038014 + PHY_BBDIG_BASE_ADDR) // Transmit ALC OFDM Accumulator register #define PHY_BBDIG_RITONECTL (0x0003805c + PHY_BBDIG_BASE_ADDR) // Tone Generator Control register #define PHY_BBDIG_RITONEGEN_0 (0x00038060 + PHY_BBDIG_BASE_ADDR) // Tone Generator 1 Configuration register #define PHY_BBDIG_RITONEGEN_1 (0x00038064 + PHY_BBDIG_BASE_ADDR) // Tone Generator 2 Configuration register #define PHY_BBDIG_RITXOFFSET_15 (0x000380e4 + PHY_BBDIG_BASE_ADDR) // Transmit I/Q Offset register #define PHY_BBDIG_RIRXCTRL (0x000380e8 + PHY_BBDIG_BASE_ADDR) // Receive Controller register #define PHY_BBDIG_RIRXENDDELAY (0x000380ec + PHY_BBDIG_BASE_ADDR) // Receive Controller End delay register #define PHY_BBDIG_RIRXIQCTRL (0x000380f0 + PHY_BBDIG_BASE_ADDR) // Receive I/Q Offset Control register #define PHY_BBDIG_RIRXIQTMR (0x000380f4 + PHY_BBDIG_BASE_ADDR) // Receive I/Q Offset Start Timer register #define PHY_BBDIG_RIRXIQPRD (0x000380f8 + PHY_BBDIG_BASE_ADDR) // Receive I/Q Offset Period Timer register #define PHY_BBDIG_RIDCTRKCFG (0x000380fc + PHY_BBDIG_BASE_ADDR) // Receive I/Q Offset Tracking Configuration register #define PHY_BBDIG_RIRXIEST (0x0003810c + PHY_BBDIG_BASE_ADDR) // Receive I Offset Estimate register #define PHY_BBDIG_RIRXQEST (0x00038110 + PHY_BBDIG_BASE_ADDR) // Receive Q Offset Estimate register #define PHY_BBDIG_RIRXDCERR (0x00038114 + PHY_BBDIG_BASE_ADDR) // Receive DC Offset Error register #define PHY_BBDIG_RIRXBBDC_0 (0x00038118 + PHY_BBDIG_BASE_ADDR) // Receive Baseband DC Offset 0 register #define PHY_BBDIG_RIRXRFDC_HI (0x00038198 + PHY_BBDIG_BASE_ADDR) // Receive RF DC Offset High Gain register #define PHY_BBDIG_RIRXRFDC_LO (0x0003819c + PHY_BBDIG_BASE_ADDR) // Receive RF DC Offset Low Gain register #define PHY_BBDIG_RIRXIQIMB (0x000381a0 + PHY_BBDIG_BASE_ADDR) // Receive I/Q Imbalance register #define PHY_BBDIG_RIRXAGC (0x000381a4 + PHY_BBDIG_BASE_ADDR) // Receive AGC register #define PHY_BBDIG_RIQMEASCTRL (0x000381ac + PHY_BBDIG_BASE_ADDR) // Receive Quadrature Measurement Control register #define PHY_BBDIG_RIFEMPAEN2GHZ (0x000382c4 + PHY_BBDIG_BASE_ADDR) // Front-End module PAEN 2GHz delay register #define PHY_BBDIG_RIFEMPAEN5GHZ (0x000382c8 + PHY_BBDIG_BASE_ADDR) // Front-End module PAEN 5GHz delay register #define PHY_BBDIG_RIFEMTXEN (0x000382cc + PHY_BBDIG_BASE_ADDR) // Front-End module TXEN 5GHz delay register #define PHY_BBDIG_RIFEMRXEN (0x000382d0 + PHY_BBDIG_BASE_ADDR) // Front-End module TXEN 2GHz delay register #define PHY_BBDIG_RIFEMCTRL (0x000382d4 + PHY_BBDIG_BASE_ADDR) // Front-End module Control Register #define PHY_BBDIG_RIRXRFDC_LOWER (0x000382dc + PHY_BBDIG_BASE_ADDR) // Receive RF DC Offset Lowwe Gain register #define PHY_BBDIG_FEM_CTRL_MATRIX_0 (0x00038300 + PHY_BBDIG_BASE_ADDR) // FEM control LUT #define PHY_BBDIG_FEM_CTRL_READY (0x00038388 + PHY_BBDIG_BASE_ADDR) // FEM controller ready register. It indicates FEM is fully programmed and ready when it's set to '1' #define PHY_BBDIG_RITXCLIP_0 (0x00038400 + PHY_BBDIG_BASE_ADDR ) #define PHY_RI_TEMPDSSS_ADDR (0x00038440 + PHY_BBDIG_BASE_ADDR) #define PHY_RI_TEMPOFDM_ADDR (0x00038444 + PHY_BBDIG_BASE_ADDR) #define PHY_RI_VOLTDSSS_ADDR (0x00038448 + PHY_BBDIG_BASE_ADDR) #define PHY_RI_VOLTOFDM_ADDR (0x0003844C + PHY_BBDIG_BASE_ADDR) #define PHY_RI_TEMPMEAS_ADDR (0x00038450 + PHY_BBDIG_BASE_ADDR) #define PHY_RI_VOLTMEAS_ADDR (0x00038454 + PHY_BBDIG_BASE_ADDR) #define PHY_RI_RITXPATRIM_0 (0x00038460 + PHY_BBDIG_BASE_ADDR) #define PHY_RI_RITXPATRIM_1 (0x00038464 + PHY_BBDIG_BASE_ADDR) #define PHY_RI_RITXPATRIM_2 (0x00038468 + PHY_BBDIG_BASE_ADDR) #define PHY_RI_RITXPATRIM_3 (0x0003846C + PHY_BBDIG_BASE_ADDR) #define PHY_RI_RITXPATRIM_4 (0x00038470 + PHY_BBDIG_BASE_ADDR) #define PHY_RI_RITXPATRIM_5 (0x00038474 + PHY_BBDIG_BASE_ADDR) #define PHY_RI_RITXPATRIM_6 (0x00038478 + PHY_BBDIG_BASE_ADDR) #define PHY_RI_RITXPATRIM_7 (0x0003847C + PHY_BBDIG_BASE_ADDR) #define PHY_RI_RITXPATRIM_8 (0x00038480 + PHY_BBDIG_BASE_ADDR) #define PHY_RI_RITXPATRIM_9 (0x00038484 + PHY_BBDIG_BASE_ADDR) #define PHY_RI_RITXPATRIM_10 (0x00038488 + PHY_BBDIG_BASE_ADDR) #define PHY_RI_RITXPATRIM_11 (0x0003848C + PHY_BBDIG_BASE_ADDR) #define PHY_RI_RITXPATRIM_12 (0x00038490 + PHY_BBDIG_BASE_ADDR) #define PHY_RI_RITXPATRIM_13 (0x00038494 + PHY_BBDIG_BASE_ADDR) #define PHY_RI_RITXPATRIM_14 (0x00038498 + PHY_BBDIG_BASE_ADDR) #define PHY_RI_RITXPATRIM_15 (0x0003849C + PHY_BBDIG_BASE_ADDR) #define PHY_BBDIG_RITXGAIN_FORCE (0x00038904 + PHY_BBDIG_BASE_ADDR) // Transmit Gain Control force register #define PHY_BBDIG_RITXIQIMB_0 (0x00038908 + PHY_BBDIG_BASE_ADDR) // Transmit I/Q Imbalance Pre-compensation register #define PHY_BBDIG_RITXOFFSET_0 (0x0003890c + PHY_BBDIG_BASE_ADDR) // Transmit I/Q Offset register #define PHY_RI_DCTRKGAIN_0_ADDR (0x00038600 + PHY_BBDIG_BASE_ADDR) #define PHY_RI_DCTRKEXP_0_ADDR (0x00038680 + PHY_BBDIG_BASE_ADDR) #define PHY_BBDIG_RIFCM_1 (0x0003c104 + PHY_BBDIG_BASE_ADDR) // Receive Frame Capture Metrics Register_1 TEST #define PHY_BBDIG_RIFCM_2 (0x0003c108 + PHY_BBDIG_BASE_ADDR) // Receive Frame Capture Metrics Register_1 TEST #define PHY_RRM_RMCCACTRL (0x00048014 + PHY_PRM_BASE_ADDR) // CCA Report Control Register #define PHY_RRM_RMCCASTAT (0x00048018 + PHY_PRM_BASE_ADDR) // CCA Report Status Register #define PHY_RRM_RMCCADUR (0x0004801c + PHY_PRM_BASE_ADDR) // CCA Report Measurement Duration Register #define PHY_RRM_RMCCABF (0x00048020 + PHY_PRM_BASE_ADDR) // CCA Busy Fraction Register #define PHY_RRM_RMHISTCTRL (0x00048024 + PHY_PRM_BASE_ADDR) // Histogram Control Register #define PHY_RRM_RMHISTSTAT (0x00048028 + PHY_PRM_BASE_ADDR) // Histogram Status Register #define PHY_RRM_RMHISTDUR (0x0004802c + PHY_PRM_BASE_ADDR) // Histogram Measurement Duration Register #define PHY_RRM_RMHISTREP_0 (0x00048074 + PHY_PRM_BASE_ADDR) // Histogram Density #1 Register #define PHY_RRM_RMHISTREP_1 (0x00048078 + PHY_PRM_BASE_ADDR) // Histogram Density #2 Register #define PHY_RRM_RMHISTREP_2 (0x0004807c + PHY_PRM_BASE_ADDR) // Histogram Density #3 Register #define PHY_RRM_RMHISTREP_3 (0x00048080 + PHY_PRM_BASE_ADDR) // Histogram Density #4 Register #define PHY_RRM_RMHISTREP_4 (0x00048084 + PHY_PRM_BASE_ADDR) // Histogram Density #5 Register #define PHY_RRM_RMHISTREP_5 (0x00048088 + PHY_PRM_BASE_ADDR) // Histogram Density #6 Register #define PHY_RRM_RMHISTREP_6 (0x0004808c + PHY_PRM_BASE_ADDR) // Histogram Density #7 Register #define PHY_RRM_RMHISTREP_7 (0x00048090 + PHY_PRM_BASE_ADDR) // Histogram Density #8 Register #define PHY_RRM_RMHISTREP_8 (0x00048094 + PHY_PRM_BASE_ADDR) // Histogram Density #9 Register #define PHY_RRM_RMHISTREP_9 (0x00048098 + PHY_PRM_BASE_ADDR) // Histogram Density #10 Register #define PHY_RRM_RMHISTREP_10 (0x0004809c + PHY_PRM_BASE_ADDR) // Histogram Density #11 Register // RRM (RM) #define PHY_RRM_RMRCPCTRL (0x0004800c + PHY_RRM_BASE_ADDR) // RCPI Control Register #define PHY_RRM_RMRCPSTAT (0x00048010 + PHY_BBDIG_BASE_ADDR) // RCPI Status Register TEST #define PHY_RRM_RMIPITHR_0 (0x0004804c + PHY_RRM_BASE_ADDR) // IPI Histogram Threshold #1 Register #define PHY_RRM_RMIPITHR_1 (0x00048050 + PHY_RRM_BASE_ADDR) // IPI Histogram Threshold #2 Register #define PHY_RRM_RMIPITHR_2 (0x00048054 + PHY_RRM_BASE_ADDR) // IPI Histogram Threshold #3 Register #define PHY_RRM_RMIPITHR_3 (0x00048058 + PHY_RRM_BASE_ADDR) // IPI Histogram Threshold #4 Register #define PHY_RRM_RMIPITHR_4 (0x0004805c + PHY_RRM_BASE_ADDR) // IPI Histogram Threshold #5 Register #define PHY_RRM_RMIPITHR_5 (0x00048060 + PHY_RRM_BASE_ADDR) // IPI Histogram Threshold #6 Register #define PHY_RRM_RMIPITHR_6 (0x00048064 + PHY_RRM_BASE_ADDR) // IPI Histogram Threshold #7 Register #define PHY_RRM_RMIPITHR_7 (0x00048068 + PHY_RRM_BASE_ADDR) // IPI Histogram Threshold #8 Register #define PHY_RRM_RMIPITHR_8 (0x0004806c + PHY_RRM_BASE_ADDR) // IPI Histogram Threshold #9 Register #define PHY_RRM_RMIPITHR_9 (0x00048070 + PHY_RRM_BASE_ADDR) // IPI Histogram Threshold #10 Register #define PHY_RRM_RMFCM_1 (0x000480a0 | PHY_BBDIG_BASE_ADDR) // Receive Frame Capture Metrics Register TEST #define PHY_PHY_PHYSOFTRSTN (0x00050008 + PHY_PHY_BASE_ADDR) // PHY Soft Reset Register // RFIP /* This is automatically generated RFIP register addresses */ #define DCXO_TRIM_ADDR 0x1610100c #define PHY_RFIP_INVALID 0xFFFFFFFF #define PHY_RFIP_TESTMODE_ADDR (RFIP_BASE_ADDR+0x0) #define PHY_RFIP_CTRL_ADDR (RFIP_BASE_ADDR+0x4) #define PHY_RFIP_CLOCKCFG_ADDR (RFIP_BASE_ADDR+0x8) #define PHY_RFIP_RXPSDELAY_ADDR (RFIP_BASE_ADDR+0xc) #define PHY_RFIP_RXFONDELAY_ADDR (RFIP_BASE_ADDR+0x10) #define PHY_RFIP_TXPSDELAY_ADDR (RFIP_BASE_ADDR+0x14) #define PHY_RFIP_RXLDOCFG_ADDR (RFIP_BASE_ADDR+0x18) #define PHY_RFIP_TXLDOCFG_ADDR (RFIP_BASE_ADDR+0x1c) #define PHY_RFIP_RXCFG_ADDR (RFIP_BASE_ADDR+0x20) #define PHY_RFIP_RXCFG2_ADDR (RFIP_BASE_ADDR+0x24) #define PHY_RFIP_TXCFG_ADDR (RFIP_BASE_ADDR+0x28) #define PHY_RFIP_TXRFCFG_ADDR (RFIP_BASE_ADDR+0x2c) #define PHY_RFIP_TXCALCFG_ADDR (RFIP_BASE_ADDR+0x30) #define PHY_RFIP_RXLDOOFFPS_ADDR (RFIP_BASE_ADDR+0x34) #define PHY_RFIP_RXLDOBIASPS_ADDR (RFIP_BASE_ADDR+0x38) #define PHY_RFIP_RXLDOANAPS_ADDR (RFIP_BASE_ADDR+0x3c) #define PHY_RFIP_RXLDOLQPS_ADDR (RFIP_BASE_ADDR+0x40) #define PHY_RFIP_RXLDOIDLEPS_ADDR (RFIP_BASE_ADDR+0x44) #define PHY_RFIP_RXLDOACTIVEPS_ADDR (RFIP_BASE_ADDR+0x48) #define PHY_RFIP_RXLDOFASTONPS_ADDR (RFIP_BASE_ADDR+0x4c) #define PHY_RFIP_RXOFFPS_ADDR (RFIP_BASE_ADDR+0x50) #define PHY_RFIP_RXBIASPS_ADDR (RFIP_BASE_ADDR+0x54) #define PHY_RFIP_RXANAPS_ADDR (RFIP_BASE_ADDR+0x58) #define PHY_RFIP_RXLQPS_ADDR (RFIP_BASE_ADDR+0x5c) #define PHY_RFIP_RXIDLEPS_ADDR (RFIP_BASE_ADDR+0x60) #define PHY_RFIP_RXACTIVEPS_ADDR (RFIP_BASE_ADDR+0x64) #define PHY_RFIP_RXFASTONPS_ADDR (RFIP_BASE_ADDR+0x68) #define PHY_RFIP_TXLDOOFFPS_ADDR (RFIP_BASE_ADDR+0x6c) #define PHY_RFIP_TXLDOBIASPS_ADDR (RFIP_BASE_ADDR+0x70) #define PHY_RFIP_TXLDOANAPS_ADDR (RFIP_BASE_ADDR+0x74) #define PHY_RFIP_TXLDOLQPS_ADDR (RFIP_BASE_ADDR+0x78) #define PHY_RFIP_TXLDOONPS_ADDR (RFIP_BASE_ADDR+0x7c) #define PHY_RFIP_TXLDOSUPPLIEDPS_ADDR (RFIP_BASE_ADDR+0x80) #define PHY_RFIP_TXOFFPS_ADDR (RFIP_BASE_ADDR+0x84) #define PHY_RFIP_TXBIASPS_ADDR (RFIP_BASE_ADDR+0x88) #define PHY_RFIP_TXANAPS_ADDR (RFIP_BASE_ADDR+0x8c) #define PHY_RFIP_TXLQPS_ADDR (RFIP_BASE_ADDR+0x90) #define PHY_RFIP_TXONPS_ADDR (RFIP_BASE_ADDR+0x94) #define PHY_RFIP_TXSUPPLIEDPS_ADDR (RFIP_BASE_ADDR+0x98) #define PHY_RFIP_RCCALCTRL_ADDR (RFIP_BASE_ADDR+0x9c) #define PHY_RFIP_RCCALDELAY_ADDR (RFIP_BASE_ADDR+0xa0) #define PHY_RFIP_RCCALOFFSET_ADDR (RFIP_BASE_ADDR+0xa4) #define PHY_RFIP_RCCALTEST_ADDR (RFIP_BASE_ADDR+0xa8) #define PHY_RFIP_RFPLLCFG_ADDR (RFIP_BASE_ADDR+0xac) #define PHY_RFIP_RFPLLCFG2_ADDR (RFIP_BASE_ADDR+0xb0) #define PHY_RFIP_RFPLLFRACINT_ADDR (RFIP_BASE_ADDR+0xb4) #define PHY_RFIP_VCOCFG_ADDR (RFIP_BASE_ADDR+0xb8) #define PHY_RFIP_VCOCAL_ADDR (RFIP_BASE_ADDR+0xbc) #define PHY_RFIP_ADCCAL_CFG_ADDR (RFIP_BASE_ADDR+0xc0) #define PHY_RFIP_RCCALIN_ADDR (RFIP_BASE_ADDR+0xc4) #define PHY_RFIP_VCOCALIN_ADDR (RFIP_BASE_ADDR+0xc8) #define PHY_RFIP_STATE_ADDR (RFIP_BASE_ADDR+0xcc) #define PHY_RFIP_ADCCALIN_ADDR (RFIP_BASE_ADDR+0xd0) #define PHY_RFIP_TXRFLDOHBCFG_ADDR (RFIP_BASE_ADDR+0xd4) #define PHY_RFIP_TXRFLDOHBCFG2_ADDR (RFIP_BASE_ADDR+0xd8) #define PHY_RFIP_TXRFLDOLBCFG_ADDR (RFIP_BASE_ADDR+0xdc) #define PHY_RFIP_TXRFLDOLBCFG2_ADDR (RFIP_BASE_ADDR+0xe0) #define PHY_RFIP_TXRFLDOHBLBCFG_ADDR (RFIP_BASE_ADDR+0xe4) #define PHY_RFIP_PLLDEBUGCFG_ADDR (RFIP_BASE_ADDR+0xe8) #define PHY_RFIP_PLLDEBUGCFG2_ADDR (RFIP_BASE_ADDR+0xec) #define PHY_RFIP_TXRFOFFDELAY_ADDR (RFIP_BASE_ADDR+0xf0) #define PHY_RFIP_TXRFOFFPS_ADDR (RFIP_BASE_ADDR+0xf4) #define PHY_RFIP_TXLDORFOFFPS_ADDR (RFIP_BASE_ADDR+0xf8) #define PHY_RFIP_TXPACFG_ADDR (RFIP_BASE_ADDR+0xfc) #define PHY_RFIP_TOP_CTRL_ADDR (RFIP_BASE_ADDR+0x104) #define PHY_RFIP_ADX_ADC_ADDR (RFIP_BASE_ADDR+0x10c) #define PHY_RFIP_RFPLL_REG0_ADDR (RFIP_BASE_ADDR+0x114) #define PHY_RFIP_RFPLL_REG3_ADDR (RFIP_BASE_ADDR+0x120) #define PHY_RFIP_RXABB_REG0_ADDR (RFIP_BASE_ADDR+0x130) #define PHY_RFIP_RXABB_REG1_ADDR (RFIP_BASE_ADDR+0x134) #define PHY_RFIP_RCCCAL_REG0_ADDR (RFIP_BASE_ADDR+0x138) #define PHY_RFIP_RXADC_REG0_ADDR (RFIP_BASE_ADDR+0x13c) #define PHY_RFIP_RXADC_REG1_ADDR (RFIP_BASE_ADDR+0x140) #define PHY_RFIP_RXRF_REG0_ADDR (RFIP_BASE_ADDR+0x148) #define PHY_RFIP_RXRF_REG1_ADDR (RFIP_BASE_ADDR+0x14c) #define PHY_RFIP_TXABB_REG1_ADDR (RFIP_BASE_ADDR+0x158) #define PHY_RFIP_TXPA_REG0_ADDR (RFIP_BASE_ADDR+0x160) #define PHY_RFIP_TXPA_REG1_ADDR (RFIP_BASE_ADDR+0x164) #define PHY_RFIP_TXRF_REG0_ADDR (RFIP_BASE_ADDR+0x168) #define PHY_RFIP_TXRF_REG1_ADDR (RFIP_BASE_ADDR+0x16c) #define PHY_RFIP_TXRF_REG2_ADDR (RFIP_BASE_ADDR+0x170) #define PHY_RFIP_TOP_LEVEL_ADDR (RFIP_BASE_ADDR+0x178) #define PHY_RFIP_RSV_RW0_ADDR (RFIP_BASE_ADDR+0x180) #define PHY_RFIP_RSV_RW1_ADDR (RFIP_BASE_ADDR+0x184) #define PHY_RFIP_RXOFF0_PSM_ADDR_BIAS (0x1a0) #define PHY_RFIP_RXOFF1_PSM_ADDR_BIAS (0x1a4) #define PHY_RFIP_RX_BIAS_ON0_PSM_BIAS (0x1a8) #define PHY_RFIP_RX_BIAS_ON1_PSM_BIAS (0x1ac) #define PHY_RFIP_RX_ANA_ON0_PSM_BIAS (0x1b0) #define PHY_RFIP_RX_ANA_ON1_PSM_BIAS (0x1b4) #define PHY_RFIP_RX_LDO_LQ0_PSM_BIAS (0x1b8) #define PHY_RFIP_RX_LDO_LQ1_PSM_BIAS (0x1bc) #define PHY_RFIP_RX_IDLE0_PSM_BIAS (0x1c0) #define PHY_RFIP_RX_IDLE1_PSM_BIAS (0x1c4) #define PHY_RFIP_RX_ACTIVE0_PSM_BIAS (0x1c8) #define PHY_RFIP_RX_ACTIVE1_PSM_BIAS (0x1cc) #define PHY_RFIP_RX_FAST_ON0_PSM_BIAS (0x1d0) #define PHY_RFIP_RX_FAST_ON1_PSM_BIAS (0x1d4) #define PHY_RFIP_RXOFF0_PSM_ADDR (RFIP_BASE_ADDR+PHY_RFIP_RXOFF0_PSM_ADDR_BIAS) #define PHY_RFIP_RXOFF1_PSM_ADDR (RFIP_BASE_ADDR+PHY_RFIP_RXOFF1_PSM_ADDR_BIAS) #define PHY_RFIP_RX_BIAS_ON0_PSM (RFIP_BASE_ADDR+PHY_RFIP_RX_BIAS_ON0_PSM_BIAS) #define PHY_RFIP_RX_BIAS_ON1_PSM (RFIP_BASE_ADDR+PHY_RFIP_RX_BIAS_ON1_PSM_BIAS) #define PHY_RFIP_RX_ANA_ON0_PSM (RFIP_BASE_ADDR+PHY_RFIP_RX_ANA_ON0_PSM_BIAS) #define PHY_RFIP_RX_ANA_ON1_PSM (RFIP_BASE_ADDR+PHY_RFIP_RX_ANA_ON1_PSM_BIAS) #define PHY_RFIP_RX_LDO_LQ0_PSM (RFIP_BASE_ADDR+PHY_RFIP_RX_LDO_LQ0_PSM_BIAS) #define PHY_RFIP_RX_LDO_LQ1_PSM (RFIP_BASE_ADDR+PHY_RFIP_RX_LDO_LQ1_PSM_BIAS) #define PHY_RFIP_RX_IDLE0_PSM (RFIP_BASE_ADDR+PHY_RFIP_RX_IDLE0_PSM_BIAS) #define PHY_RFIP_RX_IDLE1_PSM (RFIP_BASE_ADDR+PHY_RFIP_RX_IDLE1_PSM_BIAS) #define PHY_RFIP_RX_ACTIVE0_PSM (RFIP_BASE_ADDR+PHY_RFIP_RX_ACTIVE0_PSM_BIAS) #define PHY_RFIP_RX_ACTIVE1_PSM (RFIP_BASE_ADDR+PHY_RFIP_RX_ACTIVE1_PSM_BIAS) #define PHY_RFIP_RX_FAST_ON0_PSM (RFIP_BASE_ADDR+PHY_RFIP_RX_FAST_ON0_PSM_BIAS) #define PHY_RFIP_RX_FAST_ON1_PSM (RFIP_BASE_ADDR+PHY_RFIP_RX_FAST_ON1_PSM_BIAS) #define PHY_RFIP_TX_OFF0_PSM_OFFSET (0x1d8) #define PHY_RFIP_TX_OFF1_PSM_OFFSET (0x1dc) #define PHY_RFIP_TX_LDO_ON0_PSM_OFFSET (0x1e0) #define PHY_RFIP_TX_LDO_ON1_PSM_OFFSET (0x1e4) #define PHY_RFIP_TX_BIAS_ON0_PSM_OFFSET (0x1e8) #define PHY_RFIP_TX_BIAS_ON1_PSM_OFFSET (0x1ec) #define PHY_RFIP_TX_ANA_ON0_PSM_OFFSET (0x1f0) #define PHY_RFIP_TX_ANA_ON1_PSM_OFFSET (0x1f4) #define PHY_RFIP_TX_LDO_LQ0_PSM_OFFSET (0x1f8) #define PHY_RFIP_TX_LDO_LQ1_PSM_OFFSET (0x1fc) #define PHY_RFIP_TX_ACTIVE0_PSM_OFFSET (0x200) #define PHY_RFIP_TX_ACTIVE1_PSM_OFFSET (0x204) #define PHY_RFIP_TX_RF_OFF0_PSM_OFFSET (0x208) #define PHY_RFIP_TX_RF_OFF1_PSM_OFFSET (0x20c) #define PHY_RFIP_TX_OFF0_PSM (RFIP_BASE_ADDR+PHY_RFIP_TX_OFF0_PSM_OFFSET ) #define PHY_RFIP_TX_OFF1_PSM (RFIP_BASE_ADDR+PHY_RFIP_TX_OFF1_PSM_OFFSET ) #define PHY_RFIP_TX_LDO_ON0_PSM (RFIP_BASE_ADDR+PHY_RFIP_TX_LDO_ON0_PSM_OFFSET ) #define PHY_RFIP_TX_LDO_ON1_PSM (RFIP_BASE_ADDR+PHY_RFIP_TX_LDO_ON1_PSM_OFFSET ) #define PHY_RFIP_TX_BIAS_ON0_PSM (RFIP_BASE_ADDR+PHY_RFIP_TX_BIAS_ON0_PSM_OFFSET ) #define PHY_RFIP_TX_BIAS_ON1_PSM (RFIP_BASE_ADDR+PHY_RFIP_TX_BIAS_ON1_PSM_OFFSET ) #define PHY_RFIP_TX_ANA_ON0_PSM (RFIP_BASE_ADDR+PHY_RFIP_TX_ANA_ON0_PSM_OFFSET ) #define PHY_RFIP_TX_ANA_ON1_PSM (RFIP_BASE_ADDR+PHY_RFIP_TX_ANA_ON1_PSM_OFFSET ) #define PHY_RFIP_TX_LDO_LQ0_PSM (RFIP_BASE_ADDR+PHY_RFIP_TX_LDO_LQ0_PSM_OFFSET ) #define PHY_RFIP_TX_LDO_LQ1_PSM (RFIP_BASE_ADDR+PHY_RFIP_TX_LDO_LQ1_PSM_OFFSET ) #define PHY_RFIP_TX_ACTIVE0_PSM (RFIP_BASE_ADDR+PHY_RFIP_TX_ACTIVE0_PSM_OFFSET ) #define PHY_RFIP_TX_ACTIVE1_PSM (RFIP_BASE_ADDR+PHY_RFIP_TX_ACTIVE1_PSM_OFFSET ) #define PHY_RFIP_TX_RF_OFF0_PSM (RFIP_BASE_ADDR+PHY_RFIP_TX_RF_OFF0_PSM_OFFSET ) #define PHY_RFIP_TX_RF_OFF1_PSM (RFIP_BASE_ADDR+PHY_RFIP_TX_RF_OFF1_PSM_OFFSET ) #define PHY_RFIP_RXLO_PUP_DOWN_DELAY0 (RFIP_BASE_ADDR+0x218) #define PHY_RFIP_RXLO_PUP_DOWN_DELAY1 (RFIP_BASE_ADDR+0x21c) #define PHY_RFIP_TXLO_PUP_DOWN_DELAY0 (RFIP_BASE_ADDR+0x220) #define PHY_RFIP_TXLO_PUP_DOWN_DELAY1 (RFIP_BASE_ADDR+0x224) #define PHY_RFIP_TXRXLDO_LQ_DELAY (RFIP_BASE_ADDR+0x214) #define PHY_RFIP_TX_RX_PSM_CON (RFIP_BASE_ADDR+0x210) #define PHY_RFIP_RXADC_REG2 (RFIP_BASE_ADDR+0x150) #define PHY_RFIP_TXABB_REG2_ADDR (RFIP_BASE_ADDR+0x154) #define PHY_RFIP_TXDAC_REG0_ADDR (RFIP_BASE_ADDR+0x15c) #define PHY_RFIP_TX_OFF0_PSM1 (RFIP_BASE_ADDR+0x1dB) #define PHY_RFIP_RXADC_REG3 (RFIP_BASE_ADDR+0x144) // RRM (RM) #define PHY_RRM_RMDBM2DIG (PHY_RRM_BASE_ADDR+0x00048004 ) // Conversion dBm to Digit Register #define AUX_ADC_INSEL (BBDIG_BASE_ADDR +0xc) #define PHY_RFIP_DPLL (RFIP_BASE_ADDR+0x110) #define PHY_RFIP_AUXADC_OUTPUT (RFIP_BASE_ADDR+0x108) #define PHY_RFIP_SOFT_CFG_TXLO_ADD (RFIP_BASE_ADDR+0x230) #define PHY_RFIP_MIXER_LOAD_FREQ_TUNE_ADDR (RFIP_BASE_ADDR+0x274) #define PHY_RFIP_DRIVER_LOAD_FREQ_TUNE_ADDR (RFIP_BASE_ADDR+0x278) //add rfpll reg #define PHY_RFIP_TXPA_REG2_ADDR (RFIP_BASE_ADDR+0x28c) #define PHY_RFIP_RF_PLL_REG7 (RFIP_BASE_ADDR+0x288) #define PHY_RFIP_RF_PLL_REG8 (RFIP_BASE_ADDR+0x290) #define PHY_RFIP_RXLO_PUP (RFIP_BASE_ADDR+0x264) #define PHY_RFIP_TXPA_VSWR (RFIP_BASE_ADDR+0x2a0) // PHY General Purpose /* This is automatically generated description for register: RFIP_CTRL */ #define PHY_RFIP_CTRL_BANDWIDTH_POS 0 #define PHY_RFIP_CTRL_BANDWIDTH_LEN 1 #define PHY_RFIP_CTRL_BANDWIDTH_MSK 0x1 #define PHY_RFIP_CTRL_BANDWIDTH_EN 0x1 #define PHY_RFIP_CTRL_FORCESTATE_POS 1 #define PHY_RFIP_CTRL_FORCESTATE_LEN 1 #define PHY_RFIP_CTRL_FORCESTATE_MSK 0x2 #define PHY_RFIP_CTRL_FORCESTATE_EN 0x2 #define PHY_RFIP_CTRL_RC_AUTOCLKGATE_POS 2 #define PHY_RFIP_CTRL_RC_AUTOCLKGATE_LEN 1 #define PHY_RFIP_CTRL_RC_AUTOCLKGATE_MSK 0x4 #define PHY_RFIP_CTRL_RC_AUTOCLKGATE_EN 0x4 #define PHY_RFIP_CTRL_RXDIVIDERINIT_POS 3 #define PHY_RFIP_CTRL_RXDIVIDERINIT_LEN 3 #define PHY_RFIP_CTRL_RXDIVIDERINIT_MSK 0x38 #define PHY_RFIP_CTRL_SOFT_RESET_POS 6 #define PHY_RFIP_CTRL_SOFT_RESET_LEN 1 #define PHY_RFIP_CTRL_SOFT_RESET_MSK 0x40 #define PHY_RFIP_CTRL_SOFT_RESET_EN 0x40 #define PHY_RFIP_CTRL_TEST_LDO_EN_POS 7 #define PHY_RFIP_CTRL_TEST_LDO_EN_LEN 1 #define PHY_RFIP_CTRL_TEST_LDO_EN_MSK 0x80 #define PHY_RFIP_CTRL_TEST_LDO_EN_EN 0x80 #define PHY_RFIP_CTRL_RXCICEN_CFG_POS 8 #define PHY_RFIP_CTRL_RXCICEN_CFG_LEN 1 #define PHY_RFIP_CTRL_RXCICEN_CFG_MSK 0x100 #define PHY_RFIP_CTRL_RXCICEN_CFG_EN 0x100 #define PHY_RFIP_CTRL_CTRL_BIAS_PUP_POS 9 #define PHY_RFIP_CTRL_CTRL_BIAS_PUP_LEN 1 #define PHY_RFIP_CTRL_CTRL_BIAS_PUP_MSK 0x200 #define PHY_RFIP_CTRL_CTRL_BIAS_PUP_EN 0x1 #define PHY_RFIP_CTRL_V2I_CTRL_POS 10 #define PHY_RFIP_CTRL_V2I_CTRL_LEN 4 #define PHY_RFIP_CTRL_V2I_CTRL_MSK 0x3c00 #define PHY_RFIP_CTRL_V2I_PUP_POS 14 #define PHY_RFIP_CTRL_V2I_PUP_LEN 1 #define PHY_RFIP_CTRL_V2I_PUP_MSK 0x4000 #define PHY_RFIP_CTRL_V2I_PUP_EN 0x4000 #define PHY_RFIP_CTRL_RX_SPARE_POS 15 #define PHY_RFIP_CTRL_RX_SPARE_LEN 4 #define PHY_RFIP_CTRL_RX_SPARE_MSK 0x78000 #define PHY_RFIP_CTRL_LOBUF_ON_PUP_POS 19 #define PHY_RFIP_CTRL_LOBUF_ON_PUP_LEN 1 #define PHY_RFIP_CTRL_LOBUF_ON_PUP_MSK 0x80000 #define PHY_RFIP_CTRL_LOBUF_ON_PUP_EN 0x80000 #define PHY_RFIP_CTRL_TX_SPARE_POS 20 #define PHY_RFIP_CTRL_TX_SPARE_LEN 12 #define PHY_RFIP_CTRL_TX_SPARE_MSK 0xfff00000 #define PHY_RFIP_CTRL_CONFIG_MODE_ADC_CAL 0x00000306 #define PHY_RFIP_CTRL_CONFIG_MODE_RC_CAL_ENABLED 0x00000206 #define PHY_RFIP_CTRL_CONFIG_MODE_LDO_TEST_ENABLED 0x00000286 #define PHY_RFIP_CTRL_CONFIG_MODE_TX_FORCE_STATE 0x00000306 #define PHY_RFIP_CTRL_CONFIG_MODE_RX_ADC_TEST 0x00000306 #define PHY_RFIP_CTRL_CONFIG_MODE_GP_ADC_TEST 0x00000206 #define PHY_RFIP_CTRL_CONFIG_MODE_RXTX_ACTIVE_20MHZ 0x00000304 /* This is automatically generated description for register: RFIP_CLOCKCFG */ #define PHY_RFIP_CLOCKCFG_DPLL_EN_160B_POS 0 #define PHY_RFIP_CLOCKCFG_DPLL_EN_160B_LEN 1 #define PHY_RFIP_CLOCKCFG_DPLL_EN_160B_MSK 0x1 #define PHY_RFIP_CLOCKCFG_DPLL_EN_160B_EN 0x1 #define PHY_RFIP_CLOCKCFG_DPLL_EN_RC160_POS 1 #define PHY_RFIP_CLOCKCFG_DPLL_EN_RC160_LEN 1 #define PHY_RFIP_CLOCKCFG_DPLL_EN_RC160_MSK 0x2 #define PHY_RFIP_CLOCKCFG_DPLL_EN_RC160_EN 0x2 #define PHY_RFIP_CLOCKCFG_CLKTEST_POS 2 #define PHY_RFIP_CLOCKCFG_CLKTEST_LEN 3 #define PHY_RFIP_CLOCKCFG_CLKTEST_MSK 0x1c #define PHY_RFIP_CLOCKCFG_DPLL_TM_POS 5 #define PHY_RFIP_CLOCKCFG_DPLL_TM_LEN 3 #define PHY_RFIP_CLOCKCFG_DPLL_TM_MSK 0xe0 #define PHY_RFIP_CLOCKCFG_DPLL_LDO_TST_POS 8 #define PHY_RFIP_CLOCKCFG_DPLL_LDO_TST_LEN 1 #define PHY_RFIP_CLOCKCFG_DPLL_LDO_TST_MSK 0x100 #define PHY_RFIP_CLOCKCFG_DPLL_LDO_TST_EN 0x100 #define PHY_RFIP_CLOCKCFG_DCXO_LDO_TM_POS 9 #define PHY_RFIP_CLOCKCFG_DCXO_LDO_TM_LEN 1 #define PHY_RFIP_CLOCKCFG_DCXO_LDO_TM_MSK 0x200 #define PHY_RFIP_CLOCKCFG_DCXO_LDO_TM_EN 0x200 #define PHY_RFIP_CLOCKCFG_DCXO_TM_POS 10 #define PHY_RFIP_CLOCKCFG_DCXO_TM_LEN 2 #define PHY_RFIP_CLOCKCFG_DCXO_TM_MSK 0xc00 #define PHY_RFIP_CLOCKCFG_ADCAUX_CLKEN_POS 12 #define PHY_RFIP_CLOCKCFG_ADCAUX_CLKEN_LEN 1 #define PHY_RFIP_CLOCKCFG_ADCAUX_CLKEN_MSK 0x1000 #define PHY_RFIP_CLOCKCFG_ADCAUX_CLKEN_EN 0x1000 #define PHY_RFIP_CLOCKCFG_RXINVADCCLK_POS 13 #define PHY_RFIP_CLOCKCFG_RXINVADCCLK_LEN 1 #define PHY_RFIP_CLOCKCFG_RXINVADCCLK_MSK 0x2000 #define PHY_RFIP_CLOCKCFG_RXINVADCCLK_EN 0x2000 #define PHY_RFIP_CLOCKCFG_ADC_CK_SEL_POS 14 #define PHY_RFIP_CLOCKCFG_ADC_CK_SEL_LEN 1 #define PHY_RFIP_CLOCKCFG_ADC_CK_SEL_MSK 0x4000 #define PHY_RFIP_CLOCKCFG_ADC_CK_SEL_EN 0x4000 #define PHY_RFIP_CLOCKCFG_ADCAUX_CLK_DIV_INIT_POS 15 #define PHY_RFIP_CLOCKCFG_ADCAUX_CLK_DIV_INIT_LEN 17 #define PHY_RFIP_CLOCKCFG_ADCAUX_CLK_DIV_INIT_MSK 0xffff8000 #define PHY_RFIP_CLOCKCFG_CONFIG_MODE_RC_CAL_ENABLED 0x0000A002 #define PHY_RFIP_CLOCKCFG_CONFIG_MODE_DEFAULT 0x0000B200 /* This is automatically generated description for register: RFIP_RXCFG */ #define PHY_RFIP_RXCFG_RX_ADC_DEMEN_POS 1 #define PHY_RFIP_RXCFG_RX_ADC_DEMEN_LEN 2 #define PHY_RFIP_RXCFG_RX_ADC_DEMEN_MSK 0x6 #define PHY_RFIP_RXCFG_RX_ADC_DEMSEL_POS 2 #define PHY_RFIP_RXCFG_RX_ADC_DEMSEL_LEN 1 #define PHY_RFIP_RXCFG_RX_ADC_DEMSEL_MSK 0x4 #define PHY_RFIP_RXCFG_RX_ADC_DEMSEL_EN 0x4 #define PHY_RFIP_RXCFG_RX_RF_BANDSEL_POS 3 #define PHY_RFIP_RXCFG_RX_RF_BANDSEL_LEN 1 #define PHY_RFIP_RXCFG_RX_RF_BANDSEL_MSK 0x8 #define PHY_RFIP_RXCFG_RX_RF_BANDSEL_EN 0x8 #define PHY_RFIP_RXCFG_RX_PTAT_B_POS 4 #define PHY_RFIP_RXCFG_RX_PTAT_B_LEN 3 #define PHY_RFIP_RXCFG_RX_PTAT_B_MSK 0x70 #define PHY_RFIP_RXCFG_RX_BGAP_B_POS 7 #define PHY_RFIP_RXCFG_RX_BGAP_B_LEN 5 #define PHY_RFIP_RXCFG_RX_BGAP_B_MSK 0xf80 #define PHY_RFIP_RXCFG_RX_ABB_TESTI_EN_POS 12 #define PHY_RFIP_RXCFG_RX_ABB_TESTI_EN_LEN 1 #define PHY_RFIP_RXCFG_RX_ABB_TESTI_EN_MSK 0x1000 #define PHY_RFIP_RXCFG_RX_ABB_TESTI_EN_EN 0x1000 #define PHY_RFIP_RXCFG_RX_ABB_TESTQ_EN_POS 13 #define PHY_RFIP_RXCFG_RX_ABB_TESTQ_EN_LEN 1 #define PHY_RFIP_RXCFG_RX_ABB_TESTQ_EN_MSK 0x2000 #define PHY_RFIP_RXCFG_RX_ABB_TESTQ_EN_EN 0x2000 #define PHY_RFIP_RXCFG_RX_DACI_EN_CFG_POS 14 #define PHY_RFIP_RXCFG_RX_DACI_EN_CFG_LEN 1 #define PHY_RFIP_RXCFG_RX_DACI_EN_CFG_MSK 0x4000 #define PHY_RFIP_RXCFG_RX_DACI_EN_CFG_EN 0x4000 #define PHY_RFIP_RXCFG_RX_DACQ_EN_CFG_POS 15 #define PHY_RFIP_RXCFG_RX_DACQ_EN_CFG_LEN 1 #define PHY_RFIP_RXCFG_RX_DACQ_EN_CFG_MSK 0x8000 #define PHY_RFIP_RXCFG_RX_DACQ_EN_CFG_EN 0x8000 #define PHY_RFIP_RXCFG_RX_LNA_HB_PUP_CFG_POS 16 #define PHY_RFIP_RXCFG_RX_LNA_HB_PUP_CFG_LEN 1 #define PHY_RFIP_RXCFG_RX_LNA_HB_PUP_CFG_MSK 0x10000 #define PHY_RFIP_RXCFG_RX_LNA_HB_PUP_CFG_EN 0x10000 #define PHY_RFIP_RXCFG_RX_LNA_LB_PUP_CFG_POS 17 #define PHY_RFIP_RXCFG_RX_LNA_LB_PUP_CFG_LEN 1 #define PHY_RFIP_RXCFG_RX_LNA_LB_PUP_CFG_MSK 0x20000 #define PHY_RFIP_RXCFG_RX_LNA_LB_PUP_CFG_EN 0x20000 #define PHY_RFIP_RXCFG_RX_LNABUFF_HB_PUP_CFG_POS 18 #define PHY_RFIP_RXCFG_RX_LNABUFF_HB_PUP_CFG_LEN 1 #define PHY_RFIP_RXCFG_RX_LNABUFF_HB_PUP_CFG_MSK 0x40000 #define PHY_RFIP_RXCFG_RX_LNABUFF_HB_PUP_CFG_EN 0x40000 #define PHY_RFIP_RXCFG_RX_LNABUFF_LB_PUP_CFG_POS 19 #define PHY_RFIP_RXCFG_RX_LNABUFF_LB_PUP_CFG_LEN 1 #define PHY_RFIP_RXCFG_RX_LNABUFF_LB_PUP_CFG_MSK 0x80000 #define PHY_RFIP_RXCFG_RX_LNABUFF_LB_PUP_CFG_EN 0x80000 #define PHY_RFIP_RXCFG_RX_LO_HB_PUP_CFG_POS 20 #define PHY_RFIP_RXCFG_RX_LO_HB_PUP_CFG_LEN 2 #define PHY_RFIP_RXCFG_RX_LO_HB_PUP_CFG_MSK 0x300000 #define PHY_RFIP_RXCFG_RX_LO_LB_PUP_CFG_POS 22 #define PHY_RFIP_RXCFG_RX_LO_LB_PUP_CFG_LEN 2 #define PHY_RFIP_RXCFG_RX_LO_LB_PUP_CFG_MSK 0xc00000 #define PHY_RFIP_RXCFG_RX_ABBI_PUP_CFG_POS 24 #define PHY_RFIP_RXCFG_RX_ABBI_PUP_CFG_LEN 1 #define PHY_RFIP_RXCFG_RX_ABBI_PUP_CFG_MSK 0x1000000 #define PHY_RFIP_RXCFG_RX_ABBI_PUP_CFG_EN 0x1000000 #define PHY_RFIP_RXCFG_RX_ABBQ_PUP_CFG_POS 25 #define PHY_RFIP_RXCFG_RX_ABBQ_PUP_CFG_LEN 1 #define PHY_RFIP_RXCFG_RX_ABBQ_PUP_CFG_MSK 0x2000000 #define PHY_RFIP_RXCFG_RX_ABBQ_PUP_CFG_EN 0x2000000 #define PHY_RFIP_RXCFG_RX_ADCCOREI_PUP_CFG_POS 26 #define PHY_RFIP_RXCFG_RX_ADCCOREI_PUP_CFG_LEN 1 #define PHY_RFIP_RXCFG_RX_ADCCOREI_PUP_CFG_MSK 0x4000000 #define PHY_RFIP_RXCFG_RX_ADCCOREI_PUP_CFG_EN 0x4000000 #define PHY_RFIP_RXCFG_RX_ADCCOREQ_PUP_CFG_POS 27 #define PHY_RFIP_RXCFG_RX_ADCCOREQ_PUP_CFG_LEN 1 #define PHY_RFIP_RXCFG_RX_ADCCOREQ_PUP_CFG_MSK 0x8000000 #define PHY_RFIP_RXCFG_RX_ADCCOREQ_PUP_CFG_EN 0x8000000 #define PHY_RFIP_RXCFG_RX_TEST_SEL_POS 28 #define PHY_RFIP_RXCFG_RX_TEST_SEL_LEN 1 #define PHY_RFIP_RXCFG_RX_TEST_SEL_MSK 0x10000000 #define PHY_RFIP_RXCFG_RX_TEST_SEL_EN 0x10000000 #define PHY_RFIP_RXCFG_RX_ADC_REF_BCK_POS 29 #define PHY_RFIP_RXCFG_RX_ADC_REF_BCK_LEN 1 #define PHY_RFIP_RXCFG_RX_ADC_REF_BCK_MSK 0x20000000 #define PHY_RFIP_RXCFG_RX_ADC_REF_BCK_EN 0x20000000 #define PHY_RFIP_RXCFG_RX_PTAT_START_POS 30 #define PHY_RFIP_RXCFG_RX_PTAT_START_LEN 1 #define PHY_RFIP_RXCFG_RX_PTAT_START_MSK 0x40000000 #define PHY_RFIP_RXCFG_RX_PTAT_START_EN 0x40000000 #define PHY_RFIP_RXCFG_RX_BGAP_START_POS 31 #define PHY_RFIP_RXCFG_RX_BGAP_START_LEN 1 #define PHY_RFIP_RXCFG_RX_BGAP_START_MSK 0x80000000 #define PHY_RFIP_RXCFG_CONFIG_VALUE_ABB_OUTQ_TEST_ADC 0x0C003000 #define PHY_RFIP_RXCFG_CONFIG_VALUE_ADC_OUT_RX_HIGH_BAND_20MHZ 0x0F15C000 #define PHY_RFIP_RXCFG_CONFIG_VALUE_ABB_OUTQ_LDO_TEST 0x0FCAC008 #define PHY_RFIP_RXCFG_CONFIG_VALUE_ABB_OUTI_LOW_BAND_20MHZ 0x1F4AD008 #define PHY_RFIP_RXCFG_CONFIG_VALUE_ABB_OUTI_RX_HIGH_BAND_20MHZ4 0x1F15D000 #define PHY_RFIP_RXCFG_CONFIG_VALUE_ABB_OUTQ_LOW_BAND_20MHZ5 0x1F4AE008 #define PHY_RFIP_RXCFG_CONFIG_VALUE_ABB_OUTQ_RX_DCOFFSET_I 0x1F00D080 #define PHY_RFIP_RXCFG_CONFIG_VALUE_ABB_OUTQ_RX_HIGH_BAND_20MHZ7 0x1F15E000 #define PHY_RFIP_RXCFG_CONFIG_VALUE_ABB_OUTQ_RX_DCOFFSET_Q 0x1F00E080 #define PHY_RFIP_RXCFG_CONFIG_VALUE_ABB_OUTQ_IQCAL_MODE 0x1F00D000 #define PHY_RFIP_RXCFG_CONFIG_VALUE_ADC_OUT_LOW_BAND_20MHZ10 0x0F4AC008 /* This is automatically generated description for register: RFIP_RXCFG2 */ #define PHY_RFIP_RXCFG2_RX_TESTI_EN_POS 0 #define PHY_RFIP_RXCFG2_RX_TESTI_EN_LEN 1 #define PHY_RFIP_RXCFG2_RX_TESTI_EN_MSK 0x1 #define PHY_RFIP_RXCFG2_RX_TESTI_EN_EN 0x1 #define PHY_RFIP_RXCFG2_RX_TESTQ_EN_POS 1 #define PHY_RFIP_RXCFG2_RX_TESTQ_EN_LEN 1 #define PHY_RFIP_RXCFG2_RX_TESTQ_EN_MSK 0x2 #define PHY_RFIP_RXCFG2_RX_TESTQ_EN_EN 0x2 #define PHY_RFIP_RXCFG2_RX_LO_LB_2_5_CTRL_POS 2 #define PHY_RFIP_RXCFG2_RX_LO_LB_2_5_CTRL_LEN 9 #define PHY_RFIP_RXCFG2_RX_LO_LB_2_5_CTRL_MSK 0x7fc #define PHY_RFIP_RXCFG2_RX_ADC_ICW_POS 11 #define PHY_RFIP_RXCFG2_RX_ADC_ICW_LEN 3 #define PHY_RFIP_RXCFG2_RX_ADC_ICW_MSK 0x3800 #define PHY_RFIP_RXCFG2_RX_ADCCMP_ICW_POS 14 #define PHY_RFIP_RXCFG2_RX_ADCCMP_ICW_LEN 3 #define PHY_RFIP_RXCFG2_RX_ADCCMP_ICW_MSK 0x1c000 #define PHY_RFIP_RXCFG2_RX_ADCCAL_CALSEL_POS 17 #define PHY_RFIP_RXCFG2_RX_ADCCAL_CALSEL_LEN 1 #define PHY_RFIP_RXCFG2_RX_ADCCAL_CALSEL_MSK 0x20000 #define PHY_RFIP_RXCFG2_RX_ADCCAL_CALSEL_EN 0x20000 #define PHY_RFIP_RXCFG2_RXCICRESETEN_POS 18 #define PHY_RFIP_RXCFG2_RXCICRESETEN_LEN 1 #define PHY_RFIP_RXCFG2_RXCICRESETEN_MSK 0x40000 #define PHY_RFIP_RXCFG2_RXCICRESETEN_EN 0x40000 #define PHY_RFIP_RXCFG2_RXCICSATTHRESHOLD_POS 19 #define PHY_RFIP_RXCFG2_RXCICSATTHRESHOLD_LEN 8 #define PHY_RFIP_RXCFG2_RXCICSATTHRESHOLD_MSK 0x7f80000 #define PHY_RFIP_RXCFG2_RXCICOFFSET_EN_POS 27 #define PHY_RFIP_RXCFG2_RXCICOFFSET_EN_LEN 1 #define PHY_RFIP_RXCFG2_RXCICOFFSET_EN_MSK 0x8000000 #define PHY_RFIP_RXCFG2_RXCICOFFSET_EN_EN 0x8000000 #define PHY_RFIP_RXCFG2_RX_ICTRL_LNABUFLB_POS 28 #define PHY_RFIP_RXCFG2_RX_ICTRL_LNABUFLB_LEN 2 #define PHY_RFIP_RXCFG2_RX_ICTRL_LNABUFLB_MSK 0x30000000 #define PHY_RFIP_RXCFG2_RX_ICTRL_LNABUFHB_POS 30 #define PHY_RFIP_RXCFG2_RX_ICTRL_LNABUFHB_LEN 2 #define PHY_RFIP_RXCFG2_RX_ICTRL_LNABUFHB_MSK 0xc0000000 #define PHY_RFIP_RXCFG2_CONFIG_RX_ABB_OUT_ACTIVE_DC_OFFSET 0x23350803 #define PHY_RFIP_RXCFG2_CONFIG_RX_ADC_OUT_ACTIVE_RX_HIGH_BAND_20MHZ 0x89371800 #define PHY_RFIP_RXCFG2_CONFIG_RX_ABB_OUT_ACTIVE_LOW_BAND_20MHZ 0x29371803 #define PHY_RFIP_RXCFG2_CONFIG_RX_ABB_OUT_ACTIVE_RX_HIGH_BAND_20MHZ3 0x09371803 #define PHY_RFIP_RXCFG2_CONFIG_RX_ABB_OUT_ACTIVE_IQCAL_MODE 0x09371803 #define PHY_RFIP_RXCFG2_CONFIG_RX_ABB_OUT_ACTIVE_TEST_ADC 0x29371803 #define PHY_RFIP_RXCFG2_CONFIG_RX_ABB_OUT_ACTIVE_LDO_TEST 0x23350800 #define PHY_RFIP_RXCFG2_CONFIG_RX_ADC_OUT_ACTIVE_LOW_BAND_20MHZ7 0x29371800 /* This is automatically generated description for register: RX_POWER_STATE */ #define PHY_RFIP_RXOFFPS_RX_DPLL_EN320_POS 0 #define PHY_RFIP_RXOFFPS_RX_DPLL_EN320_LEN 1 #define PHY_RFIP_RXOFFPS_RX_DPLL_EN320_MSK 0x1 #define PHY_RFIP_RXOFFPS_RX_DPLL_EN320_EN 0x1 #define PHY_RFIP_RXBIASPS_RX_DPLL_EN320_POS 0 #define PHY_RFIP_RXBIASPS_RX_DPLL_EN320_LEN 1 #define PHY_RFIP_RXBIASPS_RX_DPLL_EN320_MSK 0x1 #define PHY_RFIP_RXBIASPS_RX_DPLL_EN320_EN 0x1 #define PHY_RFIP_RXANAPS_RX_DPLL_EN320_POS 0 #define PHY_RFIP_RXANAPS_RX_DPLL_EN320_LEN 1 #define PHY_RFIP_RXANAPS_RX_DPLL_EN320_MSK 0x1 #define PHY_RFIP_RXANAPS_RX_DPLL_EN320_EN 0x1 #define PHY_RFIP_RXLQPS_RX_DPLL_EN320_POS 0 #define PHY_RFIP_RXLQPS_RX_DPLL_EN320_LEN 1 #define PHY_RFIP_RXLQPS_RX_DPLL_EN320_MSK 0x1 #define PHY_RFIP_RXLQPS_RX_DPLL_EN320_EN 0x1 #define PHY_RFIP_RXIDLEPS_RX_DPLL_EN320_POS 0 #define PHY_RFIP_RXIDLEPS_RX_DPLL_EN320_LEN 1 #define PHY_RFIP_RXIDLEPS_RX_DPLL_EN320_MSK 0x1 #define PHY_RFIP_RXIDLEPS_RX_DPLL_EN320_EN 0x1 #define PHY_RFIP_RXACTIVEPS_RX_DPLL_EN320_POS 0 #define PHY_RFIP_RXACTIVEPS_RX_DPLL_EN320_LEN 1 #define PHY_RFIP_RXACTIVEPS_RX_DPLL_EN320_MSK 0x1 #define PHY_RFIP_RXACTIVEPS_RX_DPLL_EN320_EN 0x1 #define PHY_RFIP_RXFASTONPS_RX_DPLL_EN320_POS 0 #define PHY_RFIP_RXFASTONPS_RX_DPLL_EN320_LEN 1 #define PHY_RFIP_RXFASTONPS_RX_DPLL_EN320_MSK 0x1 #define PHY_RFIP_RXFASTONPS_RX_DPLL_EN320_EN 0x1 #define PHY_RFIP_RXOFFPS_RX_DPLL_EN960_POS 1 #define PHY_RFIP_RXOFFPS_RX_DPLL_EN960_LEN 2 #define PHY_RFIP_RXOFFPS_RX_DPLL_EN960_MSK 0x6 #define PHY_RFIP_RXBIASPS_RX_DPLL_EN960_POS 1 #define PHY_RFIP_RXBIASPS_RX_DPLL_EN960_LEN 2 #define PHY_RFIP_RXBIASPS_RX_DPLL_EN960_MSK 0x6 #define PHY_RFIP_RXANAPS_RX_DPLL_EN960_POS 1 #define PHY_RFIP_RXANAPS_RX_DPLL_EN960_LEN 2 #define PHY_RFIP_RXANAPS_RX_DPLL_EN960_MSK 0x6 #define PHY_RFIP_RXLQPS_RX_DPLL_EN960_POS 1 #define PHY_RFIP_RXLQPS_RX_DPLL_EN960_LEN 2 #define PHY_RFIP_RXLQPS_RX_DPLL_EN960_MSK 0x6 #define PHY_RFIP_RXIDLEPS_RX_DPLL_EN960_POS 1 #define PHY_RFIP_RXIDLEPS_RX_DPLL_EN960_LEN 2 #define PHY_RFIP_RXIDLEPS_RX_DPLL_EN960_MSK 0x6 #define PHY_RFIP_RXACTIVEPS_RX_DPLL_EN960_POS 1 #define PHY_RFIP_RXACTIVEPS_RX_DPLL_EN960_LEN 2 #define PHY_RFIP_RXACTIVEPS_RX_DPLL_EN960_MSK 0x6 #define PHY_RFIP_RXFASTONPS_RX_DPLL_EN960_POS 1 #define PHY_RFIP_RXFASTONPS_RX_DPLL_EN960_LEN 2 #define PHY_RFIP_RXFASTONPS_RX_DPLL_EN960_MSK 0x6 #define PHY_RFIP_RXOFFPS_RX_DPLL_EN480_POS 3 #define PHY_RFIP_RXOFFPS_RX_DPLL_EN480_LEN 1 #define PHY_RFIP_RXOFFPS_RX_DPLL_EN480_MSK 0x8 #define PHY_RFIP_RXOFFPS_RX_DPLL_EN480_EN 0x8 #define PHY_RFIP_RXBIASPS_RX_DPLL_EN480_POS 3 #define PHY_RFIP_RXBIASPS_RX_DPLL_EN480_LEN 1 #define PHY_RFIP_RXBIASPS_RX_DPLL_EN480_MSK 0x8 #define PHY_RFIP_RXBIASPS_RX_DPLL_EN480_EN 0x8 #define PHY_RFIP_RXANAPS_RX_DPLL_EN480_POS 3 #define PHY_RFIP_RXANAPS_RX_DPLL_EN480_LEN 1 #define PHY_RFIP_RXANAPS_RX_DPLL_EN480_MSK 0x8 #define PHY_RFIP_RXANAPS_RX_DPLL_EN480_EN 0x8 #define PHY_RFIP_RXLQPS_RX_DPLL_EN480_POS 3 #define PHY_RFIP_RXLQPS_RX_DPLL_EN480_LEN 1 #define PHY_RFIP_RXLQPS_RX_DPLL_EN480_MSK 0x8 #define PHY_RFIP_RXLQPS_RX_DPLL_EN480_EN 0x8 #define PHY_RFIP_RXIDLEPS_RX_DPLL_EN480_POS 3 #define PHY_RFIP_RXIDLEPS_RX_DPLL_EN480_LEN 1 #define PHY_RFIP_RXIDLEPS_RX_DPLL_EN480_MSK 0x8 #define PHY_RFIP_RXIDLEPS_RX_DPLL_EN480_EN 0x8 #define PHY_RFIP_RXACTIVEPS_RX_DPLL_EN480_POS 3 #define PHY_RFIP_RXACTIVEPS_RX_DPLL_EN480_LEN 1 #define PHY_RFIP_RXACTIVEPS_RX_DPLL_EN480_MSK 0x8 #define PHY_RFIP_RXACTIVEPS_RX_DPLL_EN480_EN 0x8 #define PHY_RFIP_RXFASTONPS_RX_DPLL_EN480_POS 3 #define PHY_RFIP_RXFASTONPS_RX_DPLL_EN480_LEN 1 #define PHY_RFIP_RXFASTONPS_RX_DPLL_EN480_MSK 0x8 #define PHY_RFIP_RXFASTONPS_RX_DPLL_EN480_EN 0x8 #define PHY_RFIP_RXOFFPS_RX_PTAT_PUP_POS 4 #define PHY_RFIP_RXOFFPS_RX_PTAT_PUP_LEN 1 #define PHY_RFIP_RXOFFPS_RX_PTAT_PUP_MSK 0x10 #define PHY_RFIP_RXOFFPS_RX_PTAT_PUP_EN 0x10 #define PHY_RFIP_RXBIASPS_RX_PTAT_PUP_POS 4 #define PHY_RFIP_RXBIASPS_RX_PTAT_PUP_LEN 1 #define PHY_RFIP_RXBIASPS_RX_PTAT_PUP_MSK 0x10 #define PHY_RFIP_RXBIASPS_RX_PTAT_PUP_EN 0x10 #define PHY_RFIP_RXANAPS_RX_PTAT_PUP_POS 4 #define PHY_RFIP_RXANAPS_RX_PTAT_PUP_LEN 1 #define PHY_RFIP_RXANAPS_RX_PTAT_PUP_MSK 0x10 #define PHY_RFIP_RXANAPS_RX_PTAT_PUP_EN 0x10 #define PHY_RFIP_RXLQPS_RX_PTAT_PUP_POS 4 #define PHY_RFIP_RXLQPS_RX_PTAT_PUP_LEN 1 #define PHY_RFIP_RXLQPS_RX_PTAT_PUP_MSK 0x10 #define PHY_RFIP_RXLQPS_RX_PTAT_PUP_EN 0x10 #define PHY_RFIP_RXIDLEPS_RX_PTAT_PUP_POS 4 #define PHY_RFIP_RXIDLEPS_RX_PTAT_PUP_LEN 1 #define PHY_RFIP_RXIDLEPS_RX_PTAT_PUP_MSK 0x10 #define PHY_RFIP_RXIDLEPS_RX_PTAT_PUP_EN 0x10 #define PHY_RFIP_RXACTIVEPS_RX_PTAT_PUP_POS 4 #define PHY_RFIP_RXACTIVEPS_RX_PTAT_PUP_LEN 1 #define PHY_RFIP_RXACTIVEPS_RX_PTAT_PUP_MSK 0x10 #define PHY_RFIP_RXACTIVEPS_RX_PTAT_PUP_EN 0x10 #define PHY_RFIP_RXFASTONPS_RX_PTAT_PUP_POS 4 #define PHY_RFIP_RXFASTONPS_RX_PTAT_PUP_LEN 1 #define PHY_RFIP_RXFASTONPS_RX_PTAT_PUP_MSK 0x10 #define PHY_RFIP_RXFASTONPS_RX_PTAT_PUP_EN 0x10 #define PHY_RFIP_RXOFFPS_RX_BGAP_PUP_POS 5 #define PHY_RFIP_RXOFFPS_RX_BGAP_PUP_LEN 1 #define PHY_RFIP_RXOFFPS_RX_BGAP_PUP_MSK 0x20 #define PHY_RFIP_RXOFFPS_RX_BGAP_PUP_EN 0x20 #define PHY_RFIP_RXBIASPS_RX_BGAP_PUP_POS 5 #define PHY_RFIP_RXBIASPS_RX_BGAP_PUP_LEN 1 #define PHY_RFIP_RXBIASPS_RX_BGAP_PUP_MSK 0x20 #define PHY_RFIP_RXBIASPS_RX_BGAP_PUP_EN 0x20 #define PHY_RFIP_RXANAPS_RX_BGAP_PUP_POS 5 #define PHY_RFIP_RXANAPS_RX_BGAP_PUP_LEN 1 #define PHY_RFIP_RXANAPS_RX_BGAP_PUP_MSK 0x20 #define PHY_RFIP_RXANAPS_RX_BGAP_PUP_EN 0x20 #define PHY_RFIP_RXLQPS_RX_BGAP_PUP_POS 5 #define PHY_RFIP_RXLQPS_RX_BGAP_PUP_LEN 1 #define PHY_RFIP_RXLQPS_RX_BGAP_PUP_MSK 0x20 #define PHY_RFIP_RXLQPS_RX_BGAP_PUP_EN 0x20 #define PHY_RFIP_RXIDLEPS_RX_BGAP_PUP_POS 5 #define PHY_RFIP_RXIDLEPS_RX_BGAP_PUP_LEN 1 #define PHY_RFIP_RXIDLEPS_RX_BGAP_PUP_MSK 0x20 #define PHY_RFIP_RXIDLEPS_RX_BGAP_PUP_EN 0x20 #define PHY_RFIP_RXACTIVEPS_RX_BGAP_PUP_POS 5 #define PHY_RFIP_RXACTIVEPS_RX_BGAP_PUP_LEN 1 #define PHY_RFIP_RXACTIVEPS_RX_BGAP_PUP_MSK 0x20 #define PHY_RFIP_RXACTIVEPS_RX_BGAP_PUP_EN 0x20 #define PHY_RFIP_RXFASTONPS_RX_BGAP_PUP_POS 5 #define PHY_RFIP_RXFASTONPS_RX_BGAP_PUP_LEN 1 #define PHY_RFIP_RXFASTONPS_RX_BGAP_PUP_MSK 0x20 #define PHY_RFIP_RXFASTONPS_RX_BGAP_PUP_EN 0x20 #define PHY_RFIP_RXOFFPS_RX_DAC_EN_POS 6 #define PHY_RFIP_RXOFFPS_RX_DAC_EN_LEN 1 #define PHY_RFIP_RXOFFPS_RX_DAC_EN_MSK 0x40 #define PHY_RFIP_RXOFFPS_RX_DAC_EN_EN 0x40 #define PHY_RFIP_RXBIASPS_RX_DAC_EN_POS 6 #define PHY_RFIP_RXBIASPS_RX_DAC_EN_LEN 1 #define PHY_RFIP_RXBIASPS_RX_DAC_EN_MSK 0x40 #define PHY_RFIP_RXBIASPS_RX_DAC_EN_EN 0x40 #define PHY_RFIP_RXANAPS_RX_DAC_EN_POS 6 #define PHY_RFIP_RXANAPS_RX_DAC_EN_LEN 1 #define PHY_RFIP_RXANAPS_RX_DAC_EN_MSK 0x40 #define PHY_RFIP_RXANAPS_RX_DAC_EN_EN 0x40 #define PHY_RFIP_RXLQPS_RX_DAC_EN_POS 6 #define PHY_RFIP_RXLQPS_RX_DAC_EN_LEN 1 #define PHY_RFIP_RXLQPS_RX_DAC_EN_MSK 0x40 #define PHY_RFIP_RXLQPS_RX_DAC_EN_EN 0x40 #define PHY_RFIP_RXIDLEPS_RX_DAC_EN_POS 6 #define PHY_RFIP_RXIDLEPS_RX_DAC_EN_LEN 1 #define PHY_RFIP_RXIDLEPS_RX_DAC_EN_MSK 0x40 #define PHY_RFIP_RXIDLEPS_RX_DAC_EN_EN 0x40 #define PHY_RFIP_RXACTIVEPS_RX_DAC_EN_POS 6 #define PHY_RFIP_RXACTIVEPS_RX_DAC_EN_LEN 1 #define PHY_RFIP_RXACTIVEPS_RX_DAC_EN_MSK 0x40 #define PHY_RFIP_RXACTIVEPS_RX_DAC_EN_EN 0x40 #define PHY_RFIP_RXFASTONPS_RX_DAC_EN_POS 6 #define PHY_RFIP_RXFASTONPS_RX_DAC_EN_LEN 1 #define PHY_RFIP_RXFASTONPS_RX_DAC_EN_MSK 0x40 #define PHY_RFIP_RXFASTONPS_RX_DAC_EN_EN 0x40 #define PHY_RFIP_RXOFFPS_RX_LNA_PUP_POS 7 #define PHY_RFIP_RXOFFPS_RX_LNA_PUP_LEN 1 #define PHY_RFIP_RXOFFPS_RX_LNA_PUP_MSK 0x80 #define PHY_RFIP_RXOFFPS_RX_LNA_PUP_EN 0x80 #define PHY_RFIP_RXBIASPS_RX_LNA_PUP_POS 7 #define PHY_RFIP_RXBIASPS_RX_LNA_PUP_LEN 1 #define PHY_RFIP_RXBIASPS_RX_LNA_PUP_MSK 0x80 #define PHY_RFIP_RXBIASPS_RX_LNA_PUP_EN 0x80 #define PHY_RFIP_RXANAPS_RX_LNA_PUP_POS 7 #define PHY_RFIP_RXANAPS_RX_LNA_PUP_LEN 1 #define PHY_RFIP_RXANAPS_RX_LNA_PUP_MSK 0x80 #define PHY_RFIP_RXANAPS_RX_LNA_PUP_EN 0x80 #define PHY_RFIP_RXLQPS_RX_LNA_PUP_POS 7 #define PHY_RFIP_RXLQPS_RX_LNA_PUP_LEN 1 #define PHY_RFIP_RXLQPS_RX_LNA_PUP_MSK 0x80 #define PHY_RFIP_RXLQPS_RX_LNA_PUP_EN 0x80 #define PHY_RFIP_RXIDLEPS_RX_LNA_PUP_POS 7 #define PHY_RFIP_RXIDLEPS_RX_LNA_PUP_LEN 1 #define PHY_RFIP_RXIDLEPS_RX_LNA_PUP_MSK 0x80 #define PHY_RFIP_RXIDLEPS_RX_LNA_PUP_EN 0x80 #define PHY_RFIP_RXACTIVEPS_RX_LNA_PUP_POS 7 #define PHY_RFIP_RXACTIVEPS_RX_LNA_PUP_LEN 1 #define PHY_RFIP_RXACTIVEPS_RX_LNA_PUP_MSK 0x80 #define PHY_RFIP_RXACTIVEPS_RX_LNA_PUP_EN 0x80 #define PHY_RFIP_RXFASTONPS_RX_LNA_PUP_POS 7 #define PHY_RFIP_RXFASTONPS_RX_LNA_PUP_LEN 1 #define PHY_RFIP_RXFASTONPS_RX_LNA_PUP_MSK 0x80 #define PHY_RFIP_RXFASTONPS_RX_LNA_PUP_EN 0x80 #define PHY_RFIP_RXOFFPS_RX_LNABUFF_PUP_POS 8 #define PHY_RFIP_RXOFFPS_RX_LNABUFF_PUP_LEN 1 #define PHY_RFIP_RXOFFPS_RX_LNABUFF_PUP_MSK 0x100 #define PHY_RFIP_RXOFFPS_RX_LNABUFF_PUP_EN 0x100 #define PHY_RFIP_RXBIASPS_RX_LNABUFF_PUP_POS 8 #define PHY_RFIP_RXBIASPS_RX_LNABUFF_PUP_LEN 1 #define PHY_RFIP_RXBIASPS_RX_LNABUFF_PUP_MSK 0x100 #define PHY_RFIP_RXBIASPS_RX_LNABUFF_PUP_EN 0x100 #define PHY_RFIP_RXANAPS_RX_LNABUFF_PUP_POS 8 #define PHY_RFIP_RXANAPS_RX_LNABUFF_PUP_LEN 1 #define PHY_RFIP_RXANAPS_RX_LNABUFF_PUP_MSK 0x100 #define PHY_RFIP_RXANAPS_RX_LNABUFF_PUP_EN 0x100 #define PHY_RFIP_RXLQPS_RX_LNABUFF_PUP_POS 8 #define PHY_RFIP_RXLQPS_RX_LNABUFF_PUP_LEN 1 #define PHY_RFIP_RXLQPS_RX_LNABUFF_PUP_MSK 0x100 #define PHY_RFIP_RXLQPS_RX_LNABUFF_PUP_EN 0x100 #define PHY_RFIP_RXIDLEPS_RX_LNABUFF_PUP_POS 8 #define PHY_RFIP_RXIDLEPS_RX_LNABUFF_PUP_LEN 1 #define PHY_RFIP_RXIDLEPS_RX_LNABUFF_PUP_MSK 0x100 #define PHY_RFIP_RXIDLEPS_RX_LNABUFF_PUP_EN 0x100 #define PHY_RFIP_RXACTIVEPS_RX_LNABUFF_PUP_POS 8 #define PHY_RFIP_RXACTIVEPS_RX_LNABUFF_PUP_LEN 1 #define PHY_RFIP_RXACTIVEPS_RX_LNABUFF_PUP_MSK 0x100 #define PHY_RFIP_RXACTIVEPS_RX_LNABUFF_PUP_EN 0x100 #define PHY_RFIP_RXFASTONPS_RX_LNABUFF_PUP_POS 8 #define PHY_RFIP_RXFASTONPS_RX_LNABUFF_PUP_LEN 1 #define PHY_RFIP_RXFASTONPS_RX_LNABUFF_PUP_MSK 0x100 #define PHY_RFIP_RXFASTONPS_RX_LNABUFF_PUP_EN 0x100 #define PHY_RFIP_RXOFFPS_RX_LO_PUP_POS 9 #define PHY_RFIP_RXOFFPS_RX_LO_PUP_LEN 1 #define PHY_RFIP_RXOFFPS_RX_LO_PUP_MSK 0x200 #define PHY_RFIP_RXOFFPS_RX_LO_PUP_EN 0x200 #define PHY_RFIP_RXBIASPS_RX_LO_PUP_POS 9 #define PHY_RFIP_RXBIASPS_RX_LO_PUP_LEN 1 #define PHY_RFIP_RXBIASPS_RX_LO_PUP_MSK 0x200 #define PHY_RFIP_RXBIASPS_RX_LO_PUP_EN 0x200 #define PHY_RFIP_RXANAPS_RX_LO_PUP_POS 9 #define PHY_RFIP_RXANAPS_RX_LO_PUP_LEN 1 #define PHY_RFIP_RXANAPS_RX_LO_PUP_MSK 0x200 #define PHY_RFIP_RXANAPS_RX_LO_PUP_EN 0x200 #define PHY_RFIP_RXLQPS_RX_LO_PUP_POS 9 #define PHY_RFIP_RXLQPS_RX_LO_PUP_LEN 1 #define PHY_RFIP_RXLQPS_RX_LO_PUP_MSK 0x200 #define PHY_RFIP_RXLQPS_RX_LO_PUP_EN 0x200 #define PHY_RFIP_RXIDLEPS_RX_LO_PUP_POS 9 #define PHY_RFIP_RXIDLEPS_RX_LO_PUP_LEN 1 #define PHY_RFIP_RXIDLEPS_RX_LO_PUP_MSK 0x200 #define PHY_RFIP_RXIDLEPS_RX_LO_PUP_EN 0x200 #define PHY_RFIP_RXACTIVEPS_RX_LO_PUP_POS 9 #define PHY_RFIP_RXACTIVEPS_RX_LO_PUP_LEN 1 #define PHY_RFIP_RXACTIVEPS_RX_LO_PUP_MSK 0x200 #define PHY_RFIP_RXACTIVEPS_RX_LO_PUP_EN 0x200 #define PHY_RFIP_RXFASTONPS_RX_LO_PUP_POS 9 #define PHY_RFIP_RXFASTONPS_RX_LO_PUP_LEN 1 #define PHY_RFIP_RXFASTONPS_RX_LO_PUP_MSK 0x200 #define PHY_RFIP_RXFASTONPS_RX_LO_PUP_EN 0x200 #define PHY_RFIP_RXOFFPS_RX_ABB_PUP_POS 10 #define PHY_RFIP_RXOFFPS_RX_ABB_PUP_LEN 1 #define PHY_RFIP_RXOFFPS_RX_ABB_PUP_MSK 0x400 #define PHY_RFIP_RXOFFPS_RX_ABB_PUP_EN 0x400 #define PHY_RFIP_RXBIASPS_RX_ABB_PUP_POS 10 #define PHY_RFIP_RXBIASPS_RX_ABB_PUP_LEN 1 #define PHY_RFIP_RXBIASPS_RX_ABB_PUP_MSK 0x400 #define PHY_RFIP_RXBIASPS_RX_ABB_PUP_EN 0x400 #define PHY_RFIP_RXANAPS_RX_ABB_PUP_POS 10 #define PHY_RFIP_RXANAPS_RX_ABB_PUP_LEN 1 #define PHY_RFIP_RXANAPS_RX_ABB_PUP_MSK 0x400 #define PHY_RFIP_RXANAPS_RX_ABB_PUP_EN 0x400 #define PHY_RFIP_RXLQPS_RX_ABB_PUP_POS 10 #define PHY_RFIP_RXLQPS_RX_ABB_PUP_LEN 1 #define PHY_RFIP_RXLQPS_RX_ABB_PUP_MSK 0x400 #define PHY_RFIP_RXLQPS_RX_ABB_PUP_EN 0x400 #define PHY_RFIP_RXIDLEPS_RX_ABB_PUP_POS 10 #define PHY_RFIP_RXIDLEPS_RX_ABB_PUP_LEN 1 #define PHY_RFIP_RXIDLEPS_RX_ABB_PUP_MSK 0x400 #define PHY_RFIP_RXIDLEPS_RX_ABB_PUP_EN 0x400 #define PHY_RFIP_RXACTIVEPS_RX_ABB_PUP_POS 10 #define PHY_RFIP_RXACTIVEPS_RX_ABB_PUP_LEN 1 #define PHY_RFIP_RXACTIVEPS_RX_ABB_PUP_MSK 0x400 #define PHY_RFIP_RXACTIVEPS_RX_ABB_PUP_EN 0x400 #define PHY_RFIP_RXFASTONPS_RX_ABB_PUP_POS 10 #define PHY_RFIP_RXFASTONPS_RX_ABB_PUP_LEN 1 #define PHY_RFIP_RXFASTONPS_RX_ABB_PUP_MSK 0x400 #define PHY_RFIP_RXFASTONPS_RX_ABB_PUP_EN 0x400 #define PHY_RFIP_RXOFFPS_RX_ADCCORE_PUP_POS 11 #define PHY_RFIP_RXOFFPS_RX_ADCCORE_PUP_LEN 1 #define PHY_RFIP_RXOFFPS_RX_ADCCORE_PUP_MSK 0x800 #define PHY_RFIP_RXOFFPS_RX_ADCCORE_PUP_EN 0x800 #define PHY_RFIP_RXBIASPS_RX_ADCCORE_PUP_POS 11 #define PHY_RFIP_RXBIASPS_RX_ADCCORE_PUP_LEN 1 #define PHY_RFIP_RXBIASPS_RX_ADCCORE_PUP_MSK 0x800 #define PHY_RFIP_RXBIASPS_RX_ADCCORE_PUP_EN 0x800 #define PHY_RFIP_RXANAPS_RX_ADCCORE_PUP_POS 11 #define PHY_RFIP_RXANAPS_RX_ADCCORE_PUP_LEN 1 #define PHY_RFIP_RXANAPS_RX_ADCCORE_PUP_MSK 0x800 #define PHY_RFIP_RXANAPS_RX_ADCCORE_PUP_EN 0x800 #define PHY_RFIP_RXLQPS_RX_ADCCORE_PUP_POS 11 #define PHY_RFIP_RXLQPS_RX_ADCCORE_PUP_LEN 1 #define PHY_RFIP_RXLQPS_RX_ADCCORE_PUP_MSK 0x800 #define PHY_RFIP_RXLQPS_RX_ADCCORE_PUP_EN 0x800 #define PHY_RFIP_RXIDLEPS_RX_ADCCORE_PUP_POS 11 #define PHY_RFIP_RXIDLEPS_RX_ADCCORE_PUP_LEN 1 #define PHY_RFIP_RXIDLEPS_RX_ADCCORE_PUP_MSK 0x800 #define PHY_RFIP_RXIDLEPS_RX_ADCCORE_PUP_EN 0x800 #define PHY_RFIP_RXACTIVEPS_RX_ADCCORE_PUP_POS 11 #define PHY_RFIP_RXACTIVEPS_RX_ADCCORE_PUP_LEN 1 #define PHY_RFIP_RXACTIVEPS_RX_ADCCORE_PUP_MSK 0x800 #define PHY_RFIP_RXACTIVEPS_RX_ADCCORE_PUP_EN 0x800 #define PHY_RFIP_RXFASTONPS_RX_ADCCORE_PUP_POS 11 #define PHY_RFIP_RXFASTONPS_RX_ADCCORE_PUP_LEN 1 #define PHY_RFIP_RXFASTONPS_RX_ADCCORE_PUP_MSK 0x800 #define PHY_RFIP_RXFASTONPS_RX_ADCCORE_PUP_EN 0x800 #define PHY_RFIP_RXOFFPS_RX_ADCVREF_PUP_POS 12 #define PHY_RFIP_RXOFFPS_RX_ADCVREF_PUP_LEN 1 #define PHY_RFIP_RXOFFPS_RX_ADCVREF_PUP_MSK 0x1000 #define PHY_RFIP_RXOFFPS_RX_ADCVREF_PUP_EN 0x1000 #define PHY_RFIP_RXBIASPS_RX_ADCVREF_PUP_POS 12 #define PHY_RFIP_RXBIASPS_RX_ADCVREF_PUP_LEN 1 #define PHY_RFIP_RXBIASPS_RX_ADCVREF_PUP_MSK 0x1000 #define PHY_RFIP_RXBIASPS_RX_ADCVREF_PUP_EN 0x1000 #define PHY_RFIP_RXANAPS_RX_ADCVREF_PUP_POS 12 #define PHY_RFIP_RXANAPS_RX_ADCVREF_PUP_LEN 1 #define PHY_RFIP_RXANAPS_RX_ADCVREF_PUP_MSK 0x1000 #define PHY_RFIP_RXANAPS_RX_ADCVREF_PUP_EN 0x1000 #define PHY_RFIP_RXLQPS_RX_ADCVREF_PUP_POS 12 #define PHY_RFIP_RXLQPS_RX_ADCVREF_PUP_LEN 1 #define PHY_RFIP_RXLQPS_RX_ADCVREF_PUP_MSK 0x1000 #define PHY_RFIP_RXLQPS_RX_ADCVREF_PUP_EN 0x1000 #define PHY_RFIP_RXIDLEPS_RX_ADCVREF_PUP_POS 12 #define PHY_RFIP_RXIDLEPS_RX_ADCVREF_PUP_LEN 1 #define PHY_RFIP_RXIDLEPS_RX_ADCVREF_PUP_MSK 0x1000 #define PHY_RFIP_RXIDLEPS_RX_ADCVREF_PUP_EN 0x1000 #define PHY_RFIP_RXACTIVEPS_RX_ADCVREF_PUP_POS 12 #define PHY_RFIP_RXACTIVEPS_RX_ADCVREF_PUP_LEN 1 #define PHY_RFIP_RXACTIVEPS_RX_ADCVREF_PUP_MSK 0x1000 #define PHY_RFIP_RXACTIVEPS_RX_ADCVREF_PUP_EN 0x1000 #define PHY_RFIP_RXFASTONPS_RX_ADCVREF_PUP_POS 12 #define PHY_RFIP_RXFASTONPS_RX_ADCVREF_PUP_LEN 1 #define PHY_RFIP_RXFASTONPS_RX_ADCVREF_PUP_MSK 0x1000 #define PHY_RFIP_RXFASTONPS_RX_ADCVREF_PUP_EN 0x1000 #define PHY_RFIP_RXOFFPS_RX_DAC_PUP_POS 13 #define PHY_RFIP_RXOFFPS_RX_DAC_PUP_LEN 1 #define PHY_RFIP_RXOFFPS_RX_DAC_PUP_MSK 0x2000 #define PHY_RFIP_RXOFFPS_RX_DAC_PUP_EN 0x2000 #define PHY_RFIP_RXBIASPS_RX_DAC_PUP_POS 13 #define PHY_RFIP_RXBIASPS_RX_DAC_PUP_LEN 1 #define PHY_RFIP_RXBIASPS_RX_DAC_PUP_MSK 0x2000 #define PHY_RFIP_RXBIASPS_RX_DAC_PUP_EN 0x2000 #define PHY_RFIP_RXANAPS_RX_DAC_PUP_POS 13 #define PHY_RFIP_RXANAPS_RX_DAC_PUP_LEN 1 #define PHY_RFIP_RXANAPS_RX_DAC_PUP_MSK 0x2000 #define PHY_RFIP_RXANAPS_RX_DAC_PUP_EN 0x2000 #define PHY_RFIP_RXLQPS_RX_DAC_PUP_POS 13 #define PHY_RFIP_RXLQPS_RX_DAC_PUP_LEN 1 #define PHY_RFIP_RXLQPS_RX_DAC_PUP_MSK 0x2000 #define PHY_RFIP_RXLQPS_RX_DAC_PUP_EN 0x2000 #define PHY_RFIP_RXIDLEPS_RX_DAC_PUP_POS 13 #define PHY_RFIP_RXIDLEPS_RX_DAC_PUP_LEN 1 #define PHY_RFIP_RXIDLEPS_RX_DAC_PUP_MSK 0x2000 #define PHY_RFIP_RXIDLEPS_RX_DAC_PUP_EN 0x2000 #define PHY_RFIP_RXACTIVEPS_RX_DAC_PUP_POS 13 #define PHY_RFIP_RXACTIVEPS_RX_DAC_PUP_LEN 1 #define PHY_RFIP_RXACTIVEPS_RX_DAC_PUP_MSK 0x2000 #define PHY_RFIP_RXACTIVEPS_RX_DAC_PUP_EN 0x2000 #define PHY_RFIP_RXFASTONPS_RX_DAC_PUP_POS 13 #define PHY_RFIP_RXFASTONPS_RX_DAC_PUP_LEN 1 #define PHY_RFIP_RXFASTONPS_RX_DAC_PUP_MSK 0x2000 #define PHY_RFIP_RXFASTONPS_RX_DAC_PUP_EN 0x2000 #define PHY_RFIP_RXOFFPS_RX_ADC_CLKEN_POS 14 #define PHY_RFIP_RXOFFPS_RX_ADC_CLKEN_LEN 1 #define PHY_RFIP_RXOFFPS_RX_ADC_CLKEN_MSK 0x4000 #define PHY_RFIP_RXOFFPS_RX_ADC_CLKEN_EN 0x4000 #define PHY_RFIP_RXBIASPS_RX_ADC_CLKEN_POS 14 #define PHY_RFIP_RXBIASPS_RX_ADC_CLKEN_LEN 1 #define PHY_RFIP_RXBIASPS_RX_ADC_CLKEN_MSK 0x4000 #define PHY_RFIP_RXBIASPS_RX_ADC_CLKEN_EN 0x4000 #define PHY_RFIP_RXANAPS_RX_ADC_CLKEN_POS 14 #define PHY_RFIP_RXANAPS_RX_ADC_CLKEN_LEN 1 #define PHY_RFIP_RXANAPS_RX_ADC_CLKEN_MSK 0x4000 #define PHY_RFIP_RXANAPS_RX_ADC_CLKEN_EN 0x4000 #define PHY_RFIP_RXLQPS_RX_ADC_CLKEN_POS 14 #define PHY_RFIP_RXLQPS_RX_ADC_CLKEN_LEN 1 #define PHY_RFIP_RXLQPS_RX_ADC_CLKEN_MSK 0x4000 #define PHY_RFIP_RXLQPS_RX_ADC_CLKEN_EN 0x4000 #define PHY_RFIP_RXIDLEPS_RX_ADC_CLKEN_POS 14 #define PHY_RFIP_RXIDLEPS_RX_ADC_CLKEN_LEN 1 #define PHY_RFIP_RXIDLEPS_RX_ADC_CLKEN_MSK 0x4000 #define PHY_RFIP_RXIDLEPS_RX_ADC_CLKEN_EN 0x4000 #define PHY_RFIP_RXACTIVEPS_RX_ADC_CLKEN_POS 14 #define PHY_RFIP_RXACTIVEPS_RX_ADC_CLKEN_LEN 1 #define PHY_RFIP_RXACTIVEPS_RX_ADC_CLKEN_MSK 0x4000 #define PHY_RFIP_RXACTIVEPS_RX_ADC_CLKEN_EN 0x4000 #define PHY_RFIP_RXFASTONPS_RX_ADC_CLKEN_POS 14 #define PHY_RFIP_RXFASTONPS_RX_ADC_CLKEN_LEN 1 #define PHY_RFIP_RXFASTONPS_RX_ADC_CLKEN_MSK 0x4000 #define PHY_RFIP_RXFASTONPS_RX_ADC_CLKEN_EN 0x4000 #define PHY_RFIP_RXOFFPS_RX_ADC_GAIN_POS 15 #define PHY_RFIP_RXOFFPS_RX_ADC_GAIN_LEN 1 #define PHY_RFIP_RXOFFPS_RX_ADC_GAIN_MSK 0x8000 #define PHY_RFIP_RXOFFPS_RX_ADC_GAIN_EN 0x8000 #define PHY_RFIP_RXBIASPS_RX_ADC_GAIN_POS 15 #define PHY_RFIP_RXBIASPS_RX_ADC_GAIN_LEN 1 #define PHY_RFIP_RXBIASPS_RX_ADC_GAIN_MSK 0x8000 #define PHY_RFIP_RXBIASPS_RX_ADC_GAIN_EN 0x8000 #define PHY_RFIP_RXANAPS_RX_ADC_GAIN_POS 15 #define PHY_RFIP_RXANAPS_RX_ADC_GAIN_LEN 1 #define PHY_RFIP_RXANAPS_RX_ADC_GAIN_MSK 0x8000 #define PHY_RFIP_RXANAPS_RX_ADC_GAIN_EN 0x8000 #define PHY_RFIP_RXLQPS_RX_ADC_GAIN_POS 15 #define PHY_RFIP_RXLQPS_RX_ADC_GAIN_LEN 1 #define PHY_RFIP_RXLQPS_RX_ADC_GAIN_MSK 0x8000 #define PHY_RFIP_RXLQPS_RX_ADC_GAIN_EN 0x8000 #define PHY_RFIP_RXIDLEPS_RX_ADC_GAIN_POS 15 #define PHY_RFIP_RXIDLEPS_RX_ADC_GAIN_LEN 1 #define PHY_RFIP_RXIDLEPS_RX_ADC_GAIN_MSK 0x8000 #define PHY_RFIP_RXIDLEPS_RX_ADC_GAIN_EN 0x8000 #define PHY_RFIP_RXACTIVEPS_RX_ADC_GAIN_POS 15 #define PHY_RFIP_RXACTIVEPS_RX_ADC_GAIN_LEN 1 #define PHY_RFIP_RXACTIVEPS_RX_ADC_GAIN_MSK 0x8000 #define PHY_RFIP_RXACTIVEPS_RX_ADC_GAIN_EN 0x8000 #define PHY_RFIP_RXFASTONPS_RX_ADC_GAIN_POS 15 #define PHY_RFIP_RXFASTONPS_RX_ADC_GAIN_LEN 1 #define PHY_RFIP_RXFASTONPS_RX_ADC_GAIN_MSK 0x8000 #define PHY_RFIP_RXFASTONPS_RX_ADC_GAIN_EN 0x8000 #define PHY_RFIP_RXOFFPS_RX_ADC_RST_POS 16 #define PHY_RFIP_RXOFFPS_RX_ADC_RST_LEN 1 #define PHY_RFIP_RXOFFPS_RX_ADC_RST_MSK 0x10000 #define PHY_RFIP_RXOFFPS_RX_ADC_RST_EN 0x10000 #define PHY_RFIP_RXBIASPS_RX_ADC_RST_POS 16 #define PHY_RFIP_RXBIASPS_RX_ADC_RST_LEN 1 #define PHY_RFIP_RXBIASPS_RX_ADC_RST_MSK 0x10000 #define PHY_RFIP_RXBIASPS_RX_ADC_RST_EN 0x10000 #define PHY_RFIP_RXANAPS_RX_ADC_RST_POS 16 #define PHY_RFIP_RXANAPS_RX_ADC_RST_LEN 1 #define PHY_RFIP_RXANAPS_RX_ADC_RST_MSK 0x10000 #define PHY_RFIP_RXANAPS_RX_ADC_RST_EN 0x10000 #define PHY_RFIP_RXLQPS_RX_ADC_RST_POS 16 #define PHY_RFIP_RXLQPS_RX_ADC_RST_LEN 1 #define PHY_RFIP_RXLQPS_RX_ADC_RST_MSK 0x10000 #define PHY_RFIP_RXLQPS_RX_ADC_RST_EN 0x10000 #define PHY_RFIP_RXIDLEPS_RX_ADC_RST_POS 16 #define PHY_RFIP_RXIDLEPS_RX_ADC_RST_LEN 1 #define PHY_RFIP_RXIDLEPS_RX_ADC_RST_MSK 0x10000 #define PHY_RFIP_RXIDLEPS_RX_ADC_RST_EN 0x10000 #define PHY_RFIP_RXACTIVEPS_RX_ADC_RST_POS 16 #define PHY_RFIP_RXACTIVEPS_RX_ADC_RST_LEN 1 #define PHY_RFIP_RXACTIVEPS_RX_ADC_RST_MSK 0x10000 #define PHY_RFIP_RXACTIVEPS_RX_ADC_RST_EN 0x10000 #define PHY_RFIP_RXFASTONPS_RX_ADC_RST_POS 16 #define PHY_RFIP_RXFASTONPS_RX_ADC_RST_LEN 1 #define PHY_RFIP_RXFASTONPS_RX_ADC_RST_MSK 0x10000 #define PHY_RFIP_RXFASTONPS_RX_ADC_RST_EN 0x10000 #define PHY_RFIP_RXOFFPS_RX_ICTRL_LNALB_POS 17 #define PHY_RFIP_RXOFFPS_RX_ICTRL_LNALB_LEN 2 #define PHY_RFIP_RXOFFPS_RX_ICTRL_LNALB_MSK 0x60000 #define PHY_RFIP_RXBIASPS_RX_ICTRL_LNALB_POS 17 #define PHY_RFIP_RXBIASPS_RX_ICTRL_LNALB_LEN 2 #define PHY_RFIP_RXBIASPS_RX_ICTRL_LNALB_MSK 0x60000 #define PHY_RFIP_RXANAPS_RX_ICTRL_LNALB_POS 17 #define PHY_RFIP_RXANAPS_RX_ICTRL_LNALB_LEN 2 #define PHY_RFIP_RXANAPS_RX_ICTRL_LNALB_MSK 0x60000 #define PHY_RFIP_RXLQPS_RX_ICTRL_LNALB_POS 17 #define PHY_RFIP_RXLQPS_RX_ICTRL_LNALB_LEN 2 #define PHY_RFIP_RXLQPS_RX_ICTRL_LNALB_MSK 0x60000 #define PHY_RFIP_RXIDLEPS_RX_ICTRL_LNALB_POS 17 #define PHY_RFIP_RXIDLEPS_RX_ICTRL_LNALB_LEN 2 #define PHY_RFIP_RXIDLEPS_RX_ICTRL_LNALB_MSK 0x60000 #define PHY_RFIP_RXACTIVEPS_RX_ICTRL_LNALB_POS 17 #define PHY_RFIP_RXACTIVEPS_RX_ICTRL_LNALB_LEN 2 #define PHY_RFIP_RXACTIVEPS_RX_ICTRL_LNALB_MSK 0x60000 #define PHY_RFIP_RXFASTONPS_RX_ICTRL_LNALB_POS 17 #define PHY_RFIP_RXFASTONPS_RX_ICTRL_LNALB_LEN 2 #define PHY_RFIP_RXFASTONPS_RX_ICTRL_LNALB_MSK 0x60000 #define PHY_RFIP_RXOFFPS_RX_ICTRL_LNAHB_POS 19 #define PHY_RFIP_RXOFFPS_RX_ICTRL_LNAHB_LEN 2 #define PHY_RFIP_RXOFFPS_RX_ICTRL_LNAHB_MSK 0x180000 #define PHY_RFIP_RXBIASPS_RX_ICTRL_LNAHB_POS 19 #define PHY_RFIP_RXBIASPS_RX_ICTRL_LNAHB_LEN 2 #define PHY_RFIP_RXBIASPS_RX_ICTRL_LNAHB_MSK 0x180000 #define PHY_RFIP_RXANAPS_RX_ICTRL_LNAHB_POS 19 #define PHY_RFIP_RXANAPS_RX_ICTRL_LNAHB_LEN 2 #define PHY_RFIP_RXANAPS_RX_ICTRL_LNAHB_MSK 0x180000 #define PHY_RFIP_RXLQPS_RX_ICTRL_LNAHB_POS 19 #define PHY_RFIP_RXLQPS_RX_ICTRL_LNAHB_LEN 2 #define PHY_RFIP_RXLQPS_RX_ICTRL_LNAHB_MSK 0x180000 #define PHY_RFIP_RXIDLEPS_RX_ICTRL_LNAHB_POS 19 #define PHY_RFIP_RXIDLEPS_RX_ICTRL_LNAHB_LEN 2 #define PHY_RFIP_RXIDLEPS_RX_ICTRL_LNAHB_MSK 0x180000 #define PHY_RFIP_RXACTIVEPS_RX_ICTRL_LNAHB_POS 19 #define PHY_RFIP_RXACTIVEPS_RX_ICTRL_LNAHB_LEN 2 #define PHY_RFIP_RXACTIVEPS_RX_ICTRL_LNAHB_MSK 0x180000 #define PHY_RFIP_RXFASTONPS_RX_ICTRL_LNAHB_POS 19 #define PHY_RFIP_RXFASTONPS_RX_ICTRL_LNAHB_LEN 2 #define PHY_RFIP_RXFASTONPS_RX_ICTRL_LNAHB_MSK 0x180000 #define PHY_RFIP_RXOFFPS_RX_ADC_BIAS_PUP_POS 21 #define PHY_RFIP_RXOFFPS_RX_ADC_BIAS_PUP_LEN 1 #define PHY_RFIP_RXOFFPS_RX_ADC_BIAS_PUP_MSK 0x200000 #define PHY_RFIP_RXOFFPS_RX_ADC_BIAS_PUP_EN 0x200000 #define PHY_RFIP_RXBIASPS_RX_ADC_BIAS_PUP_POS 21 #define PHY_RFIP_RXBIASPS_RX_ADC_BIAS_PUP_LEN 1 #define PHY_RFIP_RXBIASPS_RX_ADC_BIAS_PUP_MSK 0x200000 #define PHY_RFIP_RXBIASPS_RX_ADC_BIAS_PUP_EN 0x200000 #define PHY_RFIP_RXANAPS_RX_ADC_BIAS_PUP_POS 21 #define PHY_RFIP_RXANAPS_RX_ADC_BIAS_PUP_LEN 1 #define PHY_RFIP_RXANAPS_RX_ADC_BIAS_PUP_MSK 0x200000 #define PHY_RFIP_RXANAPS_RX_ADC_BIAS_PUP_EN 0x200000 #define PHY_RFIP_RXLQPS_RX_ADC_BIAS_PUP_POS 21 #define PHY_RFIP_RXLQPS_RX_ADC_BIAS_PUP_LEN 1 #define PHY_RFIP_RXLQPS_RX_ADC_BIAS_PUP_MSK 0x200000 #define PHY_RFIP_RXLQPS_RX_ADC_BIAS_PUP_EN 0x200000 #define PHY_RFIP_RXIDLEPS_RX_ADC_BIAS_PUP_POS 21 #define PHY_RFIP_RXIDLEPS_RX_ADC_BIAS_PUP_LEN 1 #define PHY_RFIP_RXIDLEPS_RX_ADC_BIAS_PUP_MSK 0x200000 #define PHY_RFIP_RXIDLEPS_RX_ADC_BIAS_PUP_EN 0x200000 #define PHY_RFIP_RXACTIVEPS_RX_ADC_BIAS_PUP_POS 21 #define PHY_RFIP_RXACTIVEPS_RX_ADC_BIAS_PUP_LEN 1 #define PHY_RFIP_RXACTIVEPS_RX_ADC_BIAS_PUP_MSK 0x200000 #define PHY_RFIP_RXACTIVEPS_RX_ADC_BIAS_PUP_EN 0x200000 #define PHY_RFIP_RXFASTONPS_RX_ADC_BIAS_PUP_POS 21 #define PHY_RFIP_RXFASTONPS_RX_ADC_BIAS_PUP_LEN 1 #define PHY_RFIP_RXFASTONPS_RX_ADC_BIAS_PUP_MSK 0x200000 #define PHY_RFIP_RXFASTONPS_RX_ADC_BIAS_PUP_EN 0x200000 #define PHY_RFIP_RXOFFPS_RX_LO_HB_BUF_PUP_POS 22 #define PHY_RFIP_RXOFFPS_RX_LO_HB_BUF_PUP_LEN 1 #define PHY_RFIP_RXOFFPS_RX_LO_HB_BUF_PUP_MSK 0x400000 #define PHY_RFIP_RXOFFPS_RX_LO_HB_BUF_PUP_EN 0x400000 #define PHY_RFIP_RXBIASPS_RX_LO_HB_BUF_PUP_POS 22 #define PHY_RFIP_RXBIASPS_RX_LO_HB_BUF_PUP_LEN 1 #define PHY_RFIP_RXBIASPS_RX_LO_HB_BUF_PUP_MSK 0x400000 #define PHY_RFIP_RXBIASPS_RX_LO_HB_BUF_PUP_EN 0x400000 #define PHY_RFIP_RXANAPS_RX_LO_HB_BUF_PUP_POS 22 #define PHY_RFIP_RXANAPS_RX_LO_HB_BUF_PUP_LEN 1 #define PHY_RFIP_RXANAPS_RX_LO_HB_BUF_PUP_MSK 0x400000 #define PHY_RFIP_RXANAPS_RX_LO_HB_BUF_PUP_EN 0x400000 #define PHY_RFIP_RXLQPS_RX_LO_HB_BUF_PUP_POS 22 #define PHY_RFIP_RXLQPS_RX_LO_HB_BUF_PUP_LEN 1 #define PHY_RFIP_RXLQPS_RX_LO_HB_BUF_PUP_MSK 0x400000 #define PHY_RFIP_RXLQPS_RX_LO_HB_BUF_PUP_EN 0x400000 #define PHY_RFIP_RXIDLEPS_RX_LO_HB_BUF_PUP_POS 22 #define PHY_RFIP_RXIDLEPS_RX_LO_HB_BUF_PUP_LEN 1 #define PHY_RFIP_RXIDLEPS_RX_LO_HB_BUF_PUP_MSK 0x400000 #define PHY_RFIP_RXIDLEPS_RX_LO_HB_BUF_PUP_EN 0x400000 #define PHY_RFIP_RXACTIVEPS_RX_LO_HB_BUF_PUP_POS 22 #define PHY_RFIP_RXACTIVEPS_RX_LO_HB_BUF_PUP_LEN 1 #define PHY_RFIP_RXACTIVEPS_RX_LO_HB_BUF_PUP_MSK 0x400000 #define PHY_RFIP_RXACTIVEPS_RX_LO_HB_BUF_PUP_EN 0x400000 #define PHY_RFIP_RXFASTONPS_RX_LO_HB_BUF_PUP_POS 22 #define PHY_RFIP_RXFASTONPS_RX_LO_HB_BUF_PUP_LEN 1 #define PHY_RFIP_RXFASTONPS_RX_LO_HB_BUF_PUP_MSK 0x400000 #define PHY_RFIP_RXFASTONPS_RX_LO_HB_BUF_PUP_EN 0x400000 #define PHY_RFIP_RXOFFPS_RX_LO_LB_BUF_PUP_POS 23 #define PHY_RFIP_RXOFFPS_RX_LO_LB_BUF_PUP_LEN 1 #define PHY_RFIP_RXOFFPS_RX_LO_LB_BUF_PUP_MSK 0x800000 #define PHY_RFIP_RXOFFPS_RX_LO_LB_BUF_PUP_EN 0x800000 #define PHY_RFIP_RXBIASPS_RX_LO_LB_BUF_PUP_POS 23 #define PHY_RFIP_RXBIASPS_RX_LO_LB_BUF_PUP_LEN 1 #define PHY_RFIP_RXBIASPS_RX_LO_LB_BUF_PUP_MSK 0x800000 #define PHY_RFIP_RXBIASPS_RX_LO_LB_BUF_PUP_EN 0x800000 #define PHY_RFIP_RXANAPS_RX_LO_LB_BUF_PUP_POS 23 #define PHY_RFIP_RXANAPS_RX_LO_LB_BUF_PUP_LEN 1 #define PHY_RFIP_RXANAPS_RX_LO_LB_BUF_PUP_MSK 0x800000 #define PHY_RFIP_RXANAPS_RX_LO_LB_BUF_PUP_EN 0x800000 #define PHY_RFIP_RXLQPS_RX_LO_LB_BUF_PUP_POS 23 #define PHY_RFIP_RXLQPS_RX_LO_LB_BUF_PUP_LEN 1 #define PHY_RFIP_RXLQPS_RX_LO_LB_BUF_PUP_MSK 0x800000 #define PHY_RFIP_RXLQPS_RX_LO_LB_BUF_PUP_EN 0x800000 #define PHY_RFIP_RXIDLEPS_RX_LO_LB_BUF_PUP_POS 23 #define PHY_RFIP_RXIDLEPS_RX_LO_LB_BUF_PUP_LEN 1 #define PHY_RFIP_RXIDLEPS_RX_LO_LB_BUF_PUP_MSK 0x800000 #define PHY_RFIP_RXIDLEPS_RX_LO_LB_BUF_PUP_EN 0x800000 #define PHY_RFIP_RXACTIVEPS_RX_LO_LB_BUF_PUP_POS 23 #define PHY_RFIP_RXACTIVEPS_RX_LO_LB_BUF_PUP_LEN 1 #define PHY_RFIP_RXACTIVEPS_RX_LO_LB_BUF_PUP_MSK 0x800000 #define PHY_RFIP_RXACTIVEPS_RX_LO_LB_BUF_PUP_EN 0x800000 #define PHY_RFIP_RXFASTONPS_RX_LO_LB_BUF_PUP_POS 23 #define PHY_RFIP_RXFASTONPS_RX_LO_LB_BUF_PUP_LEN 1 #define PHY_RFIP_RXFASTONPS_RX_LO_LB_BUF_PUP_MSK 0x800000 #define PHY_RFIP_RXFASTONPS_RX_LO_LB_BUF_PUP_EN 0x800000 #define PHY_RFIP_RXOFFPS_RX_LO_LB_2_5_SEL_POS 24 #define PHY_RFIP_RXOFFPS_RX_LO_LB_2_5_SEL_LEN 1 #define PHY_RFIP_RXOFFPS_RX_LO_LB_2_5_SEL_MSK 0x1000000 #define PHY_RFIP_RXOFFPS_RX_LO_LB_2_5_SEL_EN 0x1000000 #define PHY_RFIP_RXBIASPS_RX_LO_LB_2_5_SEL_POS 24 #define PHY_RFIP_RXBIASPS_RX_LO_LB_2_5_SEL_LEN 1 #define PHY_RFIP_RXBIASPS_RX_LO_LB_2_5_SEL_MSK 0x1000000 #define PHY_RFIP_RXBIASPS_RX_LO_LB_2_5_SEL_EN 0x1000000 #define PHY_RFIP_RXANAPS_RX_LO_LB_2_5_SEL_POS 24 #define PHY_RFIP_RXANAPS_RX_LO_LB_2_5_SEL_LEN 1 #define PHY_RFIP_RXANAPS_RX_LO_LB_2_5_SEL_MSK 0x1000000 #define PHY_RFIP_RXANAPS_RX_LO_LB_2_5_SEL_EN 0x1000000 #define PHY_RFIP_RXLQPS_RX_LO_LB_2_5_SEL_POS 24 #define PHY_RFIP_RXLQPS_RX_LO_LB_2_5_SEL_LEN 1 #define PHY_RFIP_RXLQPS_RX_LO_LB_2_5_SEL_MSK 0x1000000 #define PHY_RFIP_RXLQPS_RX_LO_LB_2_5_SEL_EN 0x1000000 #define PHY_RFIP_RXIDLEPS_RX_LO_LB_2_5_SEL_POS 24 #define PHY_RFIP_RXIDLEPS_RX_LO_LB_2_5_SEL_LEN 1 #define PHY_RFIP_RXIDLEPS_RX_LO_LB_2_5_SEL_MSK 0x1000000 #define PHY_RFIP_RXIDLEPS_RX_LO_LB_2_5_SEL_EN 0x1000000 #define PHY_RFIP_RXACTIVEPS_RX_LO_LB_2_5_SEL_POS 24 #define PHY_RFIP_RXACTIVEPS_RX_LO_LB_2_5_SEL_LEN 1 #define PHY_RFIP_RXACTIVEPS_RX_LO_LB_2_5_SEL_MSK 0x1000000 #define PHY_RFIP_RXACTIVEPS_RX_LO_LB_2_5_SEL_EN 0x1000000 #define PHY_RFIP_RXFASTONPS_RX_LO_LB_2_5_SEL_POS 24 #define PHY_RFIP_RXFASTONPS_RX_LO_LB_2_5_SEL_LEN 1 #define PHY_RFIP_RXFASTONPS_RX_LO_LB_2_5_SEL_MSK 0x1000000 #define PHY_RFIP_RXFASTONPS_RX_LO_LB_2_5_SEL_EN 0x1000000 #define PHY_RFIP_RXOFFPS_RX_LO_LB_2_5_INIT_POS 25 #define PHY_RFIP_RXOFFPS_RX_LO_LB_2_5_INIT_LEN 1 #define PHY_RFIP_RXOFFPS_RX_LO_LB_2_5_INIT_MSK 0x2000000 #define PHY_RFIP_RXOFFPS_RX_LO_LB_2_5_INIT_EN 0x2000000 #define PHY_RFIP_RXBIASPS_RX_LO_LB_2_5_INIT_POS 25 #define PHY_RFIP_RXBIASPS_RX_LO_LB_2_5_INIT_LEN 1 #define PHY_RFIP_RXBIASPS_RX_LO_LB_2_5_INIT_MSK 0x2000000 #define PHY_RFIP_RXBIASPS_RX_LO_LB_2_5_INIT_EN 0x2000000 #define PHY_RFIP_RXANAPS_RX_LO_LB_2_5_INIT_POS 25 #define PHY_RFIP_RXANAPS_RX_LO_LB_2_5_INIT_LEN 1 #define PHY_RFIP_RXANAPS_RX_LO_LB_2_5_INIT_MSK 0x2000000 #define PHY_RFIP_RXANAPS_RX_LO_LB_2_5_INIT_EN 0x2000000 #define PHY_RFIP_RXLQPS_RX_LO_LB_2_5_INIT_POS 25 #define PHY_RFIP_RXLQPS_RX_LO_LB_2_5_INIT_LEN 1 #define PHY_RFIP_RXLQPS_RX_LO_LB_2_5_INIT_MSK 0x2000000 #define PHY_RFIP_RXLQPS_RX_LO_LB_2_5_INIT_EN 0x2000000 #define PHY_RFIP_RXIDLEPS_RX_LO_LB_2_5_INIT_POS 25 #define PHY_RFIP_RXIDLEPS_RX_LO_LB_2_5_INIT_LEN 1 #define PHY_RFIP_RXIDLEPS_RX_LO_LB_2_5_INIT_MSK 0x2000000 #define PHY_RFIP_RXIDLEPS_RX_LO_LB_2_5_INIT_EN 0x2000000 #define PHY_RFIP_RXACTIVEPS_RX_LO_LB_2_5_INIT_POS 25 #define PHY_RFIP_RXACTIVEPS_RX_LO_LB_2_5_INIT_LEN 1 #define PHY_RFIP_RXACTIVEPS_RX_LO_LB_2_5_INIT_MSK 0x2000000 #define PHY_RFIP_RXACTIVEPS_RX_LO_LB_2_5_INIT_EN 0x2000000 #define PHY_RFIP_RXFASTONPS_RX_LO_LB_2_5_INIT_POS 25 #define PHY_RFIP_RXFASTONPS_RX_LO_LB_2_5_INIT_LEN 1 #define PHY_RFIP_RXFASTONPS_RX_LO_LB_2_5_INIT_MSK 0x2000000 #define PHY_RFIP_RXFASTONPS_RX_LO_LB_2_5_INIT_EN 0x2000000 #define PHY_RFIP_RXOFFPS_RX_RSVD_PS_POS 26 #define PHY_RFIP_RXOFFPS_RX_RSVD_PS_LEN 6 #define PHY_RFIP_RXOFFPS_RX_RSVD_PS_MSK 0xfc000000 #define PHY_RFIP_RXBIASPS_RX_RSVD_PS_POS 26 #define PHY_RFIP_RXBIASPS_RX_RSVD_PS_LEN 6 #define PHY_RFIP_RXBIASPS_RX_RSVD_PS_MSK 0xfc000000 #define PHY_RFIP_RXANAPS_RX_RSVD_PS_POS 26 #define PHY_RFIP_RXANAPS_RX_RSVD_PS_LEN 6 #define PHY_RFIP_RXANAPS_RX_RSVD_PS_MSK 0xfc000000 #define PHY_RFIP_RXLQPS_RX_RSVD_PS_POS 26 #define PHY_RFIP_RXLQPS_RX_RSVD_PS_LEN 6 #define PHY_RFIP_RXLQPS_RX_RSVD_PS_MSK 0xfc000000 #define PHY_RFIP_RXIDLEPS_RX_RSVD_PS_POS 26 #define PHY_RFIP_RXIDLEPS_RX_RSVD_PS_LEN 6 #define PHY_RFIP_RXIDLEPS_RX_RSVD_PS_MSK 0xfc000000 #define PHY_RFIP_RXACTIVEPS_RX_RSVD_PS_POS 26 #define PHY_RFIP_RXACTIVEPS_RX_RSVD_PS_LEN 6 #define PHY_RFIP_RXACTIVEPS_RX_RSVD_PS_MSK 0xfc000000 #define PHY_RFIP_RXFASTONPS_RX_RSVD_PS_POS 26 #define PHY_RFIP_RXFASTONPS_RX_RSVD_PS_LEN 6 #define PHY_RFIP_RXFASTONPS_RX_RSVD_PS_MSK 0xfc000000 #define PHY_RFIP_RXIDLEPS_CONFIG_PS_LOW_BAND_RF 0x00B47FF1 #define PHY_RFIP_RXACTIVEPS_CONFIG_PS_LOW_BAND_RF 0x00B47FF1 #define PHY_RFIP_RXFASTONPS_CONFIG_PS_LOW_BAND_RF 0x00B47FF1 #define PHY_RFIP_RXOFFPS_CONFIG_PS_HIGH_BAND_RF 0x00550000 #define PHY_RFIP_PS_CONFIG_FULL_RX_LB_FORCE_STATE_ADC_RESET 0x04A57FF1 #define PHY_RFIP_RXBIASPS_CONFIG_PS_HIGH_BAND_RF 0x00753830 #define PHY_RFIP_PS_CONFIG_FULL_RX_LB_FORCE_STATE_ADC_ENABLED 0x04A47FF1 #define PHY_RFIP_PS_CONFIG_HB_ABB_OUT_FORCE_STATE_ADC_RESET2 0x08447FF1 #define PHY_RFIP_PS_CONFIG_FULL_RX_HB_FORCE_STATE_ADC_RESET3 0x08657FF1 #define PHY_RFIP_PS_CONFIG_ADC_TEST_ADC_ENABLED4 0x08207801 #define PHY_RFIP_PS_CONFIG_FULL_RX_HB_FORCE_STATE_ADC_ENABLED5 0x08647FF1 #define PHY_RFIP_PS_CONFIG_ADC_TEST_LDO_TEST 0x08487FF3 #define PHY_RFIP_PS_CONFIG_ADC_TEST_DC_OFFSET 0x08687C60 #define PHY_RFIP_RXOFFPS_CONFIG_PS_LOW_BAND_RF 0x00950000 #define PHY_RFIP_RXBIASPS_CONFIG_PS_LOW_BAND_RF 0x00B53830 #define PHY_RFIP_RXANAPS_CONFIG_PS_LOW_BAND_RF 0x00B57FF1 #define PHY_RFIP_RXLQPS_CONFIG_PS_LOW_BAND_RF 0x00B47FF1 #define PHY_RFIP_RXANAPS_CONFIG_PS_HIGH_BAND_RF 0x00757FF1 #define PHY_RFIP_RXLQPS_CONFIG_PS_HIGH_BAND_RF 0x00747FF1 #define PHY_RFIP_RXIDLEPS_CONFIG_PS_HIGH_BAND_RF 0x00747FF1 #define PHY_RFIP_RXACTIVEPS_CONFIG_PS_HIGH_BAND_RF 0x00747FF1 #define PHY_RFIP_PS_CONFIG_IQ_CALIBRATION_ADC_RESET8 0x00217C63 #define PHY_RFIP_RXFASTONPS_CONFIG_PS_HIGH_BAND_RF 0x00747FF1 #define PHY_RFIP_PS_CONFIG_IQ_CALIBRATION_ADC_ENABLED9 0x00207C63 #define PHY_RFIP_PS_CONFIG_ADC_AUTOCAL_ADC_RESET10 0x08235801 #define PHY_RFIP_PS_CONFIG_ADC_AUTOCAL_ADC_ENABLED11 0x08225801 #define PHY_RFIP_PS_CONFIG_ADC_TEST_ADC_RESET12 0x08217801 /* This is automatically generated description for register: RX_LDO_POWER_STATE */ #define PHY_RFIP_RXLDOIDLEPS_RX_ABB_LDO_PUP_POS 0 #define PHY_RFIP_RXLDOIDLEPS_RX_ABB_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOIDLEPS_RX_ABB_LDO_PUP_MSK 0x1 #define PHY_RFIP_RXLDOIDLEPS_RX_ABB_LDO_PUP_EN 0x1 #define PHY_RFIP_RXLDOACTIVEPS_RX_ABB_LDO_PUP_POS 0 #define PHY_RFIP_RXLDOACTIVEPS_RX_ABB_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOACTIVEPS_RX_ABB_LDO_PUP_MSK 0x1 #define PHY_RFIP_RXLDOACTIVEPS_RX_ABB_LDO_PUP_EN 0x1 #define PHY_RFIP_RXLDOOFFPS_RX_ABB_LDO_PUP_POS 0 #define PHY_RFIP_RXLDOOFFPS_RX_ABB_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOOFFPS_RX_ABB_LDO_PUP_MSK 0x1 #define PHY_RFIP_RXLDOOFFPS_RX_ABB_LDO_PUP_EN 0x400 #define PHY_RFIP_RXLDOBIASPS_RX_ABB_LDO_PUP_POS 0 #define PHY_RFIP_RXLDOBIASPS_RX_ABB_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOBIASPS_RX_ABB_LDO_PUP_MSK 0x1 #define PHY_RFIP_RXLDOBIASPS_RX_ABB_LDO_PUP_EN 0x1 #define PHY_RFIP_RXLDOANAPS_RX_ABB_LDO_PUP_POS 0 #define PHY_RFIP_RXLDOANAPS_RX_ABB_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOANAPS_RX_ABB_LDO_PUP_MSK 0x1 #define PHY_RFIP_RXLDOANAPS_RX_ABB_LDO_PUP_EN 0x1 #define PHY_RFIP_RXLDOLQPS_RX_ABB_LDO_PUP_POS 0 #define PHY_RFIP_RXLDOLQPS_RX_ABB_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOLQPS_RX_ABB_LDO_PUP_MSK 0x1 #define PHY_RFIP_RXLDOLQPS_RX_ABB_LDO_PUP_EN 0x1 #define PHY_RFIP_RXLDOFASTONPS_RX_ABB_LDO_PUP_POS 0 #define PHY_RFIP_RXLDOFASTONPS_RX_ABB_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOFASTONPS_RX_ABB_LDO_PUP_MSK 0x1 #define PHY_RFIP_RXLDOFASTONPS_RX_ABB_LDO_PUP_EN 0x1 #define PHY_RFIP_RXLDOIDLEPS_RX_ABB_LDO_LQB_POS 1 #define PHY_RFIP_RXLDOIDLEPS_RX_ABB_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOIDLEPS_RX_ABB_LDO_LQB_MSK 0x2 #define PHY_RFIP_RXLDOIDLEPS_RX_ABB_LDO_LQB_EN 0x2 #define PHY_RFIP_RXLDOACTIVEPS_RX_ABB_LDO_LQB_POS 1 #define PHY_RFIP_RXLDOACTIVEPS_RX_ABB_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOACTIVEPS_RX_ABB_LDO_LQB_MSK 0x2 #define PHY_RFIP_RXLDOACTIVEPS_RX_ABB_LDO_LQB_EN 0x2 #define PHY_RFIP_RXLDOOFFPS_RX_ABB_LDO_LQB_POS 1 #define PHY_RFIP_RXLDOOFFPS_RX_ABB_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOOFFPS_RX_ABB_LDO_LQB_MSK 0x2 #define PHY_RFIP_RXLDOOFFPS_RX_ABB_LDO_LQB_EN 0x2 #define PHY_RFIP_RXLDOBIASPS_RX_ABB_LDO_LQB_POS 1 #define PHY_RFIP_RXLDOBIASPS_RX_ABB_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOBIASPS_RX_ABB_LDO_LQB_MSK 0x2 #define PHY_RFIP_RXLDOBIASPS_RX_ABB_LDO_LQB_EN 0x2 #define PHY_RFIP_RXLDOANAPS_RX_ABB_LDO_LQB_POS 1 #define PHY_RFIP_RXLDOANAPS_RX_ABB_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOANAPS_RX_ABB_LDO_LQB_MSK 0x2 #define PHY_RFIP_RXLDOANAPS_RX_ABB_LDO_LQB_EN 0x2 #define PHY_RFIP_RXLDOLQPS_RX_ABB_LDO_LQB_POS 1 #define PHY_RFIP_RXLDOLQPS_RX_ABB_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOLQPS_RX_ABB_LDO_LQB_MSK 0x2 #define PHY_RFIP_RXLDOLQPS_RX_ABB_LDO_LQB_EN 0x2 #define PHY_RFIP_RXLDOFASTONPS_RX_ABB_LDO_LQB_POS 1 #define PHY_RFIP_RXLDOFASTONPS_RX_ABB_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOFASTONPS_RX_ABB_LDO_LQB_MSK 0x2 #define PHY_RFIP_RXLDOFASTONPS_RX_ABB_LDO_LQB_EN 0x2 #define PHY_RFIP_RXLDOIDLEPS_RX_LO_LDO_PUP_POS 2 #define PHY_RFIP_RXLDOIDLEPS_RX_LO_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOIDLEPS_RX_LO_LDO_PUP_MSK 0x4 #define PHY_RFIP_RXLDOIDLEPS_RX_LO_LDO_PUP_EN 0x4 #define PHY_RFIP_RXLDOACTIVEPS_RX_LO_LDO_PUP_POS 2 #define PHY_RFIP_RXLDOACTIVEPS_RX_LO_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOACTIVEPS_RX_LO_LDO_PUP_MSK 0x4 #define PHY_RFIP_RXLDOACTIVEPS_RX_LO_LDO_PUP_EN 0x4 #define PHY_RFIP_RXLDOOFFPS_RX_LO_LDO_PUP_POS 2 #define PHY_RFIP_RXLDOOFFPS_RX_LO_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOOFFPS_RX_LO_LDO_PUP_MSK 0x4 #define PHY_RFIP_RXLDOOFFPS_RX_LO_LDO_PUP_EN 0x4 #define PHY_RFIP_RXLDOBIASPS_RX_LO_LDO_PUP_POS 2 #define PHY_RFIP_RXLDOBIASPS_RX_LO_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOBIASPS_RX_LO_LDO_PUP_MSK 0x4 #define PHY_RFIP_RXLDOBIASPS_RX_LO_LDO_PUP_EN 0x4 #define PHY_RFIP_RXLDOANAPS_RX_LO_LDO_PUP_POS 2 #define PHY_RFIP_RXLDOANAPS_RX_LO_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOANAPS_RX_LO_LDO_PUP_MSK 0x4 #define PHY_RFIP_RXLDOANAPS_RX_LO_LDO_PUP_EN 0x4 #define PHY_RFIP_RXLDOLQPS_RX_LO_LDO_PUP_POS 2 #define PHY_RFIP_RXLDOLQPS_RX_LO_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOLQPS_RX_LO_LDO_PUP_MSK 0x4 #define PHY_RFIP_RXLDOLQPS_RX_LO_LDO_PUP_EN 0x4 #define PHY_RFIP_RXLDOFASTONPS_RX_LO_LDO_PUP_POS 2 #define PHY_RFIP_RXLDOFASTONPS_RX_LO_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOFASTONPS_RX_LO_LDO_PUP_MSK 0x4 #define PHY_RFIP_RXLDOFASTONPS_RX_LO_LDO_PUP_EN 0x4 #define PHY_RFIP_RXLDOIDLEPS_RX_LO_LDO_LQB_POS 3 #define PHY_RFIP_RXLDOIDLEPS_RX_LO_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOIDLEPS_RX_LO_LDO_LQB_MSK 0x8 #define PHY_RFIP_RXLDOIDLEPS_RX_LO_LDO_LQB_EN 0x8 #define PHY_RFIP_RXLDOACTIVEPS_RX_LO_LDO_LQB_POS 3 #define PHY_RFIP_RXLDOACTIVEPS_RX_LO_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOACTIVEPS_RX_LO_LDO_LQB_MSK 0x8 #define PHY_RFIP_RXLDOACTIVEPS_RX_LO_LDO_LQB_EN 0x8 #define PHY_RFIP_RXLDOOFFPS_RX_LO_LDO_LQB_POS 3 #define PHY_RFIP_RXLDOOFFPS_RX_LO_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOOFFPS_RX_LO_LDO_LQB_MSK 0x8 #define PHY_RFIP_RXLDOOFFPS_RX_LO_LDO_LQB_EN 0x8 #define PHY_RFIP_RXLDOBIASPS_RX_LO_LDO_LQB_POS 3 #define PHY_RFIP_RXLDOBIASPS_RX_LO_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOBIASPS_RX_LO_LDO_LQB_MSK 0x8 #define PHY_RFIP_RXLDOBIASPS_RX_LO_LDO_LQB_EN 0x8 #define PHY_RFIP_RXLDOANAPS_RX_LO_LDO_LQB_POS 3 #define PHY_RFIP_RXLDOANAPS_RX_LO_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOANAPS_RX_LO_LDO_LQB_MSK 0x8 #define PHY_RFIP_RXLDOANAPS_RX_LO_LDO_LQB_EN 0x8 #define PHY_RFIP_RXLDOLQPS_RX_LO_LDO_LQB_POS 3 #define PHY_RFIP_RXLDOLQPS_RX_LO_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOLQPS_RX_LO_LDO_LQB_MSK 0x8 #define PHY_RFIP_RXLDOLQPS_RX_LO_LDO_LQB_EN 0x8 #define PHY_RFIP_RXLDOFASTONPS_RX_LO_LDO_LQB_POS 3 #define PHY_RFIP_RXLDOFASTONPS_RX_LO_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOFASTONPS_RX_LO_LDO_LQB_MSK 0x8 #define PHY_RFIP_RXLDOFASTONPS_RX_LO_LDO_LQB_EN 0x8 #define PHY_RFIP_RXLDOIDLEPS_RX_RF_LDO_PUP_POS 4 #define PHY_RFIP_RXLDOIDLEPS_RX_RF_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOIDLEPS_RX_RF_LDO_PUP_MSK 0x10 #define PHY_RFIP_RXLDOIDLEPS_RX_RF_LDO_PUP_EN 0x10 #define PHY_RFIP_RXLDOACTIVEPS_RX_RF_LDO_PUP_POS 4 #define PHY_RFIP_RXLDOACTIVEPS_RX_RF_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOACTIVEPS_RX_RF_LDO_PUP_MSK 0x10 #define PHY_RFIP_RXLDOACTIVEPS_RX_RF_LDO_PUP_EN 0x10 #define PHY_RFIP_RXLDOOFFPS_RX_RF_LDO_PUP_POS 4 #define PHY_RFIP_RXLDOOFFPS_RX_RF_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOOFFPS_RX_RF_LDO_PUP_MSK 0x10 #define PHY_RFIP_RXLDOOFFPS_RX_RF_LDO_PUP_EN 0x10 #define PHY_RFIP_RXLDOBIASPS_RX_RF_LDO_PUP_POS 4 #define PHY_RFIP_RXLDOBIASPS_RX_RF_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOBIASPS_RX_RF_LDO_PUP_MSK 0x10 #define PHY_RFIP_RXLDOBIASPS_RX_RF_LDO_PUP_EN 0x10 #define PHY_RFIP_RXLDOANAPS_RX_RF_LDO_PUP_POS 4 #define PHY_RFIP_RXLDOANAPS_RX_RF_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOANAPS_RX_RF_LDO_PUP_MSK 0x10 #define PHY_RFIP_RXLDOANAPS_RX_RF_LDO_PUP_EN 0x10 #define PHY_RFIP_RXLDOLQPS_RX_RF_LDO_PUP_POS 4 #define PHY_RFIP_RXLDOLQPS_RX_RF_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOLQPS_RX_RF_LDO_PUP_MSK 0x10 #define PHY_RFIP_RXLDOLQPS_RX_RF_LDO_PUP_EN 0x10 #define PHY_RFIP_RXLDOFASTONPS_RX_RF_LDO_PUP_POS 4 #define PHY_RFIP_RXLDOFASTONPS_RX_RF_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOFASTONPS_RX_RF_LDO_PUP_MSK 0x10 #define PHY_RFIP_RXLDOFASTONPS_RX_RF_LDO_PUP_EN 0x10 #define PHY_RFIP_RXLDOIDLEPS_RX_RF_LDO_LQB_POS 5 #define PHY_RFIP_RXLDOIDLEPS_RX_RF_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOIDLEPS_RX_RF_LDO_LQB_MSK 0x20 #define PHY_RFIP_RXLDOIDLEPS_RX_RF_LDO_LQB_EN 0x20 #define PHY_RFIP_RXLDOACTIVEPS_RX_RF_LDO_LQB_POS 5 #define PHY_RFIP_RXLDOACTIVEPS_RX_RF_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOACTIVEPS_RX_RF_LDO_LQB_MSK 0x20 #define PHY_RFIP_RXLDOACTIVEPS_RX_RF_LDO_LQB_EN 0x20 #define PHY_RFIP_RXLDOOFFPS_RX_RF_LDO_LQB_POS 5 #define PHY_RFIP_RXLDOOFFPS_RX_RF_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOOFFPS_RX_RF_LDO_LQB_MSK 0x20 #define PHY_RFIP_RXLDOOFFPS_RX_RF_LDO_LQB_EN 0x20 #define PHY_RFIP_RXLDOBIASPS_RX_RF_LDO_LQB_POS 5 #define PHY_RFIP_RXLDOBIASPS_RX_RF_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOBIASPS_RX_RF_LDO_LQB_MSK 0x20 #define PHY_RFIP_RXLDOBIASPS_RX_RF_LDO_LQB_EN 0x20 #define PHY_RFIP_RXLDOANAPS_RX_RF_LDO_LQB_POS 5 #define PHY_RFIP_RXLDOANAPS_RX_RF_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOANAPS_RX_RF_LDO_LQB_MSK 0x20 #define PHY_RFIP_RXLDOANAPS_RX_RF_LDO_LQB_EN 0x20 #define PHY_RFIP_RXLDOLQPS_RX_RF_LDO_LQB_POS 5 #define PHY_RFIP_RXLDOLQPS_RX_RF_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOLQPS_RX_RF_LDO_LQB_MSK 0x20 #define PHY_RFIP_RXLDOLQPS_RX_RF_LDO_LQB_EN 0x20 #define PHY_RFIP_RXLDOFASTONPS_RX_RF_LDO_LQB_POS 5 #define PHY_RFIP_RXLDOFASTONPS_RX_RF_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOFASTONPS_RX_RF_LDO_LQB_MSK 0x20 #define PHY_RFIP_RXLDOFASTONPS_RX_RF_LDO_LQB_EN 0x20 #define PHY_RFIP_RXLDOIDLEPS_RX_ADC_LDO_PUP_POS 6 #define PHY_RFIP_RXLDOIDLEPS_RX_ADC_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOIDLEPS_RX_ADC_LDO_PUP_MSK 0x40 #define PHY_RFIP_RXLDOIDLEPS_RX_ADC_LDO_PUP_EN 0x40 #define PHY_RFIP_RXLDOACTIVEPS_RX_ADC_LDO_PUP_POS 6 #define PHY_RFIP_RXLDOACTIVEPS_RX_ADC_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOACTIVEPS_RX_ADC_LDO_PUP_MSK 0x40 #define PHY_RFIP_RXLDOACTIVEPS_RX_ADC_LDO_PUP_EN 0x40 #define PHY_RFIP_RXLDOOFFPS_RX_ADC_LDO_PUP_POS 6 #define PHY_RFIP_RXLDOOFFPS_RX_ADC_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOOFFPS_RX_ADC_LDO_PUP_MSK 0x40 #define PHY_RFIP_RXLDOOFFPS_RX_ADC_LDO_PUP_EN 0x40 #define PHY_RFIP_RXLDOBIASPS_RX_ADC_LDO_PUP_POS 6 #define PHY_RFIP_RXLDOBIASPS_RX_ADC_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOBIASPS_RX_ADC_LDO_PUP_MSK 0x40 #define PHY_RFIP_RXLDOBIASPS_RX_ADC_LDO_PUP_EN 0x40 #define PHY_RFIP_RXLDOANAPS_RX_ADC_LDO_PUP_POS 6 #define PHY_RFIP_RXLDOANAPS_RX_ADC_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOANAPS_RX_ADC_LDO_PUP_MSK 0x40 #define PHY_RFIP_RXLDOANAPS_RX_ADC_LDO_PUP_EN 0x40 #define PHY_RFIP_RXLDOLQPS_RX_ADC_LDO_PUP_POS 6 #define PHY_RFIP_RXLDOLQPS_RX_ADC_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOLQPS_RX_ADC_LDO_PUP_MSK 0x40 #define PHY_RFIP_RXLDOLQPS_RX_ADC_LDO_PUP_EN 0x40 #define PHY_RFIP_RXLDOFASTONPS_RX_ADC_LDO_PUP_POS 6 #define PHY_RFIP_RXLDOFASTONPS_RX_ADC_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOFASTONPS_RX_ADC_LDO_PUP_MSK 0x40 #define PHY_RFIP_RXLDOFASTONPS_RX_ADC_LDO_PUP_EN 0x40 #define PHY_RFIP_RXLDOIDLEPS_RX_ADC_LDO_LQB_POS 7 #define PHY_RFIP_RXLDOIDLEPS_RX_ADC_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOIDLEPS_RX_ADC_LDO_LQB_MSK 0x80 #define PHY_RFIP_RXLDOIDLEPS_RX_ADC_LDO_LQB_EN 0x80 #define PHY_RFIP_RXLDOACTIVEPS_RX_ADC_LDO_LQB_POS 7 #define PHY_RFIP_RXLDOACTIVEPS_RX_ADC_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOACTIVEPS_RX_ADC_LDO_LQB_MSK 0x80 #define PHY_RFIP_RXLDOACTIVEPS_RX_ADC_LDO_LQB_EN 0x80 #define PHY_RFIP_RXLDOOFFPS_RX_ADC_LDO_LQB_POS 7 #define PHY_RFIP_RXLDOOFFPS_RX_ADC_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOOFFPS_RX_ADC_LDO_LQB_MSK 0x80 #define PHY_RFIP_RXLDOOFFPS_RX_ADC_LDO_LQB_EN 0x80 #define PHY_RFIP_RXLDOBIASPS_RX_ADC_LDO_LQB_POS 7 #define PHY_RFIP_RXLDOBIASPS_RX_ADC_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOBIASPS_RX_ADC_LDO_LQB_MSK 0x80 #define PHY_RFIP_RXLDOBIASPS_RX_ADC_LDO_LQB_EN 0x80 #define PHY_RFIP_RXLDOANAPS_RX_ADC_LDO_LQB_POS 7 #define PHY_RFIP_RXLDOANAPS_RX_ADC_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOANAPS_RX_ADC_LDO_LQB_MSK 0x80 #define PHY_RFIP_RXLDOANAPS_RX_ADC_LDO_LQB_EN 0x80 #define PHY_RFIP_RXLDOLQPS_RX_ADC_LDO_LQB_POS 7 #define PHY_RFIP_RXLDOLQPS_RX_ADC_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOLQPS_RX_ADC_LDO_LQB_MSK 0x80 #define PHY_RFIP_RXLDOLQPS_RX_ADC_LDO_LQB_EN 0x80 #define PHY_RFIP_RXLDOFASTONPS_RX_ADC_LDO_LQB_POS 7 #define PHY_RFIP_RXLDOFASTONPS_RX_ADC_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOFASTONPS_RX_ADC_LDO_LQB_MSK 0x80 #define PHY_RFIP_RXLDOFASTONPS_RX_ADC_LDO_LQB_EN 0x80 #define PHY_RFIP_RXLDOIDLEPS_CTRL_BIAS_LDO_LQB_POS 8 #define PHY_RFIP_RXLDOIDLEPS_CTRL_BIAS_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOIDLEPS_CTRL_BIAS_LDO_LQB_MSK 0x100 #define PHY_RFIP_RXLDOIDLEPS_CTRL_BIAS_LDO_LQB_EN 0x100 #define PHY_RFIP_RXLDOACTIVEPS_CTRL_BIAS_LDO_LQB_POS 8 #define PHY_RFIP_RXLDOACTIVEPS_CTRL_BIAS_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOACTIVEPS_CTRL_BIAS_LDO_LQB_MSK 0x100 #define PHY_RFIP_RXLDOACTIVEPS_CTRL_BIAS_LDO_LQB_EN 0x100 #define PHY_RFIP_RXLDOOFFPS_CTRL_BIAS_LDO_LQB_POS 8 #define PHY_RFIP_RXLDOOFFPS_CTRL_BIAS_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOOFFPS_CTRL_BIAS_LDO_LQB_MSK 0x100 #define PHY_RFIP_RXLDOOFFPS_CTRL_BIAS_LDO_LQB_EN 0x100 #define PHY_RFIP_RXLDOBIASPS_CTRL_BIAS_LDO_LQB_POS 8 #define PHY_RFIP_RXLDOBIASPS_CTRL_BIAS_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOBIASPS_CTRL_BIAS_LDO_LQB_MSK 0x100 #define PHY_RFIP_RXLDOBIASPS_CTRL_BIAS_LDO_LQB_EN 0x100 #define PHY_RFIP_RXLDOANAPS_CTRL_BIAS_LDO_LQB_POS 8 #define PHY_RFIP_RXLDOANAPS_CTRL_BIAS_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOANAPS_CTRL_BIAS_LDO_LQB_MSK 0x100 #define PHY_RFIP_RXLDOANAPS_CTRL_BIAS_LDO_LQB_EN 0x100 #define PHY_RFIP_RXLDOLQPS_CTRL_BIAS_LDO_LQB_POS 8 #define PHY_RFIP_RXLDOLQPS_CTRL_BIAS_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOLQPS_CTRL_BIAS_LDO_LQB_MSK 0x100 #define PHY_RFIP_RXLDOLQPS_CTRL_BIAS_LDO_LQB_EN 0x100 #define PHY_RFIP_RXLDOFASTONPS_CTRL_BIAS_LDO_LQB_POS 8 #define PHY_RFIP_RXLDOFASTONPS_CTRL_BIAS_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOFASTONPS_CTRL_BIAS_LDO_LQB_MSK 0x100 #define PHY_RFIP_RXLDOFASTONPS_CTRL_BIAS_LDO_LQB_EN 0x100 #define PHY_RFIP_RXLDOIDLEPS_RX_LDOABB_REF_PUP_POS 9 #define PHY_RFIP_RXLDOIDLEPS_RX_LDOABB_REF_PUP_LEN 1 #define PHY_RFIP_RXLDOIDLEPS_RX_LDOABB_REF_PUP_MSK 0x200 #define PHY_RFIP_RXLDOIDLEPS_RX_LDOABB_REF_PUP_EN 0x200 #define PHY_RFIP_RXLDOACTIVEPS_RX_LDOABB_REF_PUP_POS 9 #define PHY_RFIP_RXLDOACTIVEPS_RX_LDOABB_REF_PUP_LEN 1 #define PHY_RFIP_RXLDOACTIVEPS_RX_LDOABB_REF_PUP_MSK 0x200 #define PHY_RFIP_RXLDOACTIVEPS_RX_LDOABB_REF_PUP_EN 0x200 #define PHY_RFIP_RXLDOOFFPS_RX_LDOABB_REF_PUP_POS 9 #define PHY_RFIP_RXLDOOFFPS_RX_LDOABB_REF_PUP_LEN 1 #define PHY_RFIP_RXLDOOFFPS_RX_LDOABB_REF_PUP_MSK 0x200 #define PHY_RFIP_RXLDOOFFPS_RX_LDOABB_REF_PUP_EN 0x200 #define PHY_RFIP_RXLDOBIASPS_RX_LDOABB_REF_PUP_POS 9 #define PHY_RFIP_RXLDOBIASPS_RX_LDOABB_REF_PUP_LEN 1 #define PHY_RFIP_RXLDOBIASPS_RX_LDOABB_REF_PUP_MSK 0x200 #define PHY_RFIP_RXLDOBIASPS_RX_LDOABB_REF_PUP_EN 0x200 #define PHY_RFIP_RXLDOANAPS_RX_LDOABB_REF_PUP_POS 9 #define PHY_RFIP_RXLDOANAPS_RX_LDOABB_REF_PUP_LEN 1 #define PHY_RFIP_RXLDOANAPS_RX_LDOABB_REF_PUP_MSK 0x200 #define PHY_RFIP_RXLDOANAPS_RX_LDOABB_REF_PUP_EN 0x200 #define PHY_RFIP_RXLDOLQPS_RX_LDOABB_REF_PUP_POS 9 #define PHY_RFIP_RXLDOLQPS_RX_LDOABB_REF_PUP_LEN 1 #define PHY_RFIP_RXLDOLQPS_RX_LDOABB_REF_PUP_MSK 0x200 #define PHY_RFIP_RXLDOLQPS_RX_LDOABB_REF_PUP_EN 0x200 #define PHY_RFIP_RXLDOFASTONPS_RX_LDOABB_REF_PUP_POS 9 #define PHY_RFIP_RXLDOFASTONPS_RX_LDOABB_REF_PUP_LEN 1 #define PHY_RFIP_RXLDOFASTONPS_RX_LDOABB_REF_PUP_MSK 0x200 #define PHY_RFIP_RXLDOFASTONPS_RX_LDOABB_REF_PUP_EN 0x200 #define PHY_RFIP_RXLDOIDLEPS_RX_LDOADC_REF_PUP_POS 10 #define PHY_RFIP_RXLDOIDLEPS_RX_LDOADC_REF_PUP_LEN 1 #define PHY_RFIP_RXLDOIDLEPS_RX_LDOADC_REF_PUP_MSK 0x400 #define PHY_RFIP_RXLDOIDLEPS_RX_LDOADC_REF_PUP_EN 0x400 #define PHY_RFIP_RXLDOACTIVEPS_RX_LDOADC_REF_PUP_POS 10 #define PHY_RFIP_RXLDOACTIVEPS_RX_LDOADC_REF_PUP_LEN 1 #define PHY_RFIP_RXLDOACTIVEPS_RX_LDOADC_REF_PUP_MSK 0x400 #define PHY_RFIP_RXLDOACTIVEPS_RX_LDOADC_REF_PUP_EN 0x400 #define PHY_RFIP_RXLDOOFFPS_RX_LDOADC_REF_PUP_POS 10 #define PHY_RFIP_RXLDOOFFPS_RX_LDOADC_REF_PUP_LEN 1 #define PHY_RFIP_RXLDOOFFPS_RX_LDOADC_REF_PUP_MSK 0x400 #define PHY_RFIP_RXLDOOFFPS_RX_LDOADC_REF_PUP_EN 0x400 #define PHY_RFIP_RXLDOBIASPS_RX_LDOADC_REF_PUP_POS 10 #define PHY_RFIP_RXLDOBIASPS_RX_LDOADC_REF_PUP_LEN 1 #define PHY_RFIP_RXLDOBIASPS_RX_LDOADC_REF_PUP_MSK 0x400 #define PHY_RFIP_RXLDOBIASPS_RX_LDOADC_REF_PUP_EN 0x400 #define PHY_RFIP_RXLDOANAPS_RX_LDOADC_REF_PUP_POS 10 #define PHY_RFIP_RXLDOANAPS_RX_LDOADC_REF_PUP_LEN 1 #define PHY_RFIP_RXLDOANAPS_RX_LDOADC_REF_PUP_MSK 0x400 #define PHY_RFIP_RXLDOANAPS_RX_LDOADC_REF_PUP_EN 0x400 #define PHY_RFIP_RXLDOLQPS_RX_LDOADC_REF_PUP_POS 10 #define PHY_RFIP_RXLDOLQPS_RX_LDOADC_REF_PUP_LEN 1 #define PHY_RFIP_RXLDOLQPS_RX_LDOADC_REF_PUP_MSK 0x400 #define PHY_RFIP_RXLDOLQPS_RX_LDOADC_REF_PUP_EN 0x400 #define PHY_RFIP_RXLDOFASTONPS_RX_LDOADC_REF_PUP_POS 10 #define PHY_RFIP_RXLDOFASTONPS_RX_LDOADC_REF_PUP_LEN 1 #define PHY_RFIP_RXLDOFASTONPS_RX_LDOADC_REF_PUP_MSK 0x400 #define PHY_RFIP_RXLDOFASTONPS_RX_LDOADC_REF_PUP_EN 0x400 #define PHY_RFIP_RXLDOIDLEPS_RX_LDOLO_REF_PUP_POS 11 #define PHY_RFIP_RXLDOIDLEPS_RX_LDOLO_REF_PUP_LEN 1 #define PHY_RFIP_RXLDOIDLEPS_RX_LDOLO_REF_PUP_MSK 0x800 #define PHY_RFIP_RXLDOIDLEPS_RX_LDOLO_REF_PUP_EN 0x800 #define PHY_RFIP_RXLDOACTIVEPS_RX_LDOLO_REF_PUP_POS 11 #define PHY_RFIP_RXLDOACTIVEPS_RX_LDOLO_REF_PUP_LEN 1 #define PHY_RFIP_RXLDOACTIVEPS_RX_LDOLO_REF_PUP_MSK 0x800 #define PHY_RFIP_RXLDOACTIVEPS_RX_LDOLO_REF_PUP_EN 0x800 #define PHY_RFIP_RXLDOOFFPS_RX_LDOLO_REF_PUP_POS 11 #define PHY_RFIP_RXLDOOFFPS_RX_LDOLO_REF_PUP_LEN 1 #define PHY_RFIP_RXLDOOFFPS_RX_LDOLO_REF_PUP_MSK 0x800 #define PHY_RFIP_RXLDOOFFPS_RX_LDOLO_REF_PUP_EN 0x800 #define PHY_RFIP_RXLDOBIASPS_RX_LDOLO_REF_PUP_POS 11 #define PHY_RFIP_RXLDOBIASPS_RX_LDOLO_REF_PUP_LEN 1 #define PHY_RFIP_RXLDOBIASPS_RX_LDOLO_REF_PUP_MSK 0x800 #define PHY_RFIP_RXLDOBIASPS_RX_LDOLO_REF_PUP_EN 0x800 #define PHY_RFIP_RXLDOANAPS_RX_LDOLO_REF_PUP_POS 11 #define PHY_RFIP_RXLDOANAPS_RX_LDOLO_REF_PUP_LEN 1 #define PHY_RFIP_RXLDOANAPS_RX_LDOLO_REF_PUP_MSK 0x800 #define PHY_RFIP_RXLDOANAPS_RX_LDOLO_REF_PUP_EN 0x800 #define PHY_RFIP_RXLDOLQPS_RX_LDOLO_REF_PUP_POS 11 #define PHY_RFIP_RXLDOLQPS_RX_LDOLO_REF_PUP_LEN 1 #define PHY_RFIP_RXLDOLQPS_RX_LDOLO_REF_PUP_MSK 0x800 #define PHY_RFIP_RXLDOLQPS_RX_LDOLO_REF_PUP_EN 0x800 #define PHY_RFIP_RXLDOFASTONPS_RX_LDOLO_REF_PUP_POS 11 #define PHY_RFIP_RXLDOFASTONPS_RX_LDOLO_REF_PUP_LEN 1 #define PHY_RFIP_RXLDOFASTONPS_RX_LDOLO_REF_PUP_MSK 0x800 #define PHY_RFIP_RXLDOFASTONPS_RX_LDOLO_REF_PUP_EN 0x800 #define PHY_RFIP_RXLDOIDLEPS_RX_LDORF_REF_PUP_POS 12 #define PHY_RFIP_RXLDOIDLEPS_RX_LDORF_REF_PUP_LEN 20 #define PHY_RFIP_RXLDOIDLEPS_RX_LDORF_REF_PUP_MSK 0xfffff000 #define PHY_RFIP_RXLDOACTIVEPS_RX_LDORF_REF_PUP_POS 12 #define PHY_RFIP_RXLDOACTIVEPS_RX_LDORF_REF_PUP_LEN 20 #define PHY_RFIP_RXLDOACTIVEPS_RX_LDORF_REF_PUP_MSK 0xfffff000 #define PHY_RFIP_RXLDOOFFPS_RX_LDORF_REF_PUP_POS 12 #define PHY_RFIP_RXLDOOFFPS_RX_LDORF_REF_PUP_LEN 20 #define PHY_RFIP_RXLDOOFFPS_RX_LDORF_REF_PUP_MSK 0xfffff000 #define PHY_RFIP_RXLDOBIASPS_RX_LDORF_REF_PUP_POS 12 #define PHY_RFIP_RXLDOBIASPS_RX_LDORF_REF_PUP_LEN 20 #define PHY_RFIP_RXLDOBIASPS_RX_LDORF_REF_PUP_MSK 0xfffff000 #define PHY_RFIP_RXLDOANAPS_RX_LDORF_REF_PUP_POS 12 #define PHY_RFIP_RXLDOANAPS_RX_LDORF_REF_PUP_LEN 20 #define PHY_RFIP_RXLDOANAPS_RX_LDORF_REF_PUP_MSK 0xfffff000 #define PHY_RFIP_RXLDOLQPS_RX_LDORF_REF_PUP_POS 12 #define PHY_RFIP_RXLDOLQPS_RX_LDORF_REF_PUP_LEN 20 #define PHY_RFIP_RXLDOLQPS_RX_LDORF_REF_PUP_MSK 0xfffff000 #define PHY_RFIP_RXLDOFASTONPS_RX_LDORF_REF_PUP_POS 12 #define PHY_RFIP_RXLDOFASTONPS_RX_LDORF_REF_PUP_LEN 20 #define PHY_RFIP_RXLDOFASTONPS_RX_LDORF_REF_PUP_MSK 0xfffff000 #define PHY_RFIP_PS_CONFIG_RX_ACTIVE_GP_ADC 0x00000303 #define PHY_RFIP_PS_CONFIG_RX_ACTIVE_ADC_TEST 0x000006C1 #define PHY_RFIP_RXLDOBIASPS_CONFIG_RX_ACTIVE_RF 0x00001E55 #define PHY_RFIP_PS_CONFIG_RX_ACTIVE_LDO_TEST_ENABLED 0x00001E55 #define PHY_RFIP_PS_CONFIG_RX_ACTIVE_LDO_TEST 0x00001FFF #define PHY_RFIP_RXLDOANAPS_CONFIG_RX_ACTIVE_RF 0x00001E55 #define PHY_RFIP_RXLDOLQPS_CONFIG_RX_ACTIVE_RF 0x00001FFF #define PHY_RFIP_RXLDOIDLEPS_CONFIG_RX_ACTIVE_RF 0x00001FFF #define PHY_RFIP_PS_CONFIG_RX_ACTIVE_IQCAL_MODE 0x000006C3 #define PHY_RFIP_PS_CONFIG_RX_ACTIVE_ATE_FULL_LDO_ON 0x00001E55 #define PHY_RFIP_RXLDOACTIVEPS_CONFIG_RX_ACTIVE_RF 0x00001FFF #define PHY_RFIP_PS_CONFIG_RX_ACTIVE_FORCESTATE 0x00001FFF #define PHY_RFIP_PS_CONFIG_RX_ACTIVE_DC_OFFSET 0x00001E41 #define PHY_RFIP_PS_CONFIG_RX_ACTIVE_RC_CAL_ENABLED 0x00000201 #define PHY_RFIP_PS_CONFIG_RX_ACTIVE_ADC_AUTOCAL 0x000004C0 #define PHY_RFIP_RXLDOOFFPS_CONFIG_RX_ACTIVE_RF 0x00001E05 /* This is automatically generated description for register: RFIP_RXLDOCFG */ #define PHY_RFIP_RXLDOCFG_RX_ABB_LDO_BYP_POS 0 #define PHY_RFIP_RXLDOCFG_RX_ABB_LDO_BYP_LEN 1 #define PHY_RFIP_RXLDOCFG_RX_ABB_LDO_BYP_MSK 0x1 #define PHY_RFIP_RXLDOCFG_RX_ABB_LDO_BYP_EN 0x1 #define PHY_RFIP_RXLDOCFG_RX_LO_LDO_BYP_POS 1 #define PHY_RFIP_RXLDOCFG_RX_LO_LDO_BYP_LEN 1 #define PHY_RFIP_RXLDOCFG_RX_LO_LDO_BYP_MSK 0x2 #define PHY_RFIP_RXLDOCFG_RX_LO_LDO_BYP_EN 0x2 #define PHY_RFIP_RXLDOCFG_RX_RF_LDO_BYP_POS 2 #define PHY_RFIP_RXLDOCFG_RX_RF_LDO_BYP_LEN 1 #define PHY_RFIP_RXLDOCFG_RX_RF_LDO_BYP_MSK 0x4 #define PHY_RFIP_RXLDOCFG_RX_RF_LDO_BYP_EN 0x4 #define PHY_RFIP_RXLDOCFG_RX_ADC_LDO_BYP_POS 3 #define PHY_RFIP_RXLDOCFG_RX_ADC_LDO_BYP_LEN 1 #define PHY_RFIP_RXLDOCFG_RX_ADC_LDO_BYP_MSK 0x8 #define PHY_RFIP_RXLDOCFG_RX_ADC_LDO_BYP_EN 0x8 #define PHY_RFIP_RXLDOCFG_RX_ABB_LDO_TST_POS 4 #define PHY_RFIP_RXLDOCFG_RX_ABB_LDO_TST_LEN 1 #define PHY_RFIP_RXLDOCFG_RX_ABB_LDO_TST_MSK 0x10 #define PHY_RFIP_RXLDOCFG_RX_ABB_LDO_TST_EN 0x10 #define PHY_RFIP_RXLDOCFG_RX_LO_LDO_TST_POS 5 #define PHY_RFIP_RXLDOCFG_RX_LO_LDO_TST_LEN 1 #define PHY_RFIP_RXLDOCFG_RX_LO_LDO_TST_MSK 0x20 #define PHY_RFIP_RXLDOCFG_RX_LO_LDO_TST_EN 0x20 #define PHY_RFIP_RXLDOCFG_RX_RF_LDO_TST_POS 6 #define PHY_RFIP_RXLDOCFG_RX_RF_LDO_TST_LEN 1 #define PHY_RFIP_RXLDOCFG_RX_RF_LDO_TST_MSK 0x40 #define PHY_RFIP_RXLDOCFG_RX_RF_LDO_TST_EN 0x40 #define PHY_RFIP_RXLDOCFG_RX_ADC_LDO_TST_POS 7 #define PHY_RFIP_RXLDOCFG_RX_ADC_LDO_TST_LEN 1 #define PHY_RFIP_RXLDOCFG_RX_ADC_LDO_TST_MSK 0x80 #define PHY_RFIP_RXLDOCFG_RX_ADC_LDO_TST_EN 0x80 #define PHY_RFIP_RXLDOCFG_RX_DIG_LDO_TST_POS 8 #define PHY_RFIP_RXLDOCFG_RX_DIG_LDO_TST_LEN 1 #define PHY_RFIP_RXLDOCFG_RX_DIG_LDO_TST_MSK 0x100 #define PHY_RFIP_RXLDOCFG_RX_DIG_LDO_TST_EN 0x100 #define PHY_RFIP_RXLDOCFG_CTRL_BIAS_LDO_BYP_POS 9 #define PHY_RFIP_RXLDOCFG_CTRL_BIAS_LDO_BYP_LEN 1 #define PHY_RFIP_RXLDOCFG_CTRL_BIAS_LDO_BYP_MSK 0x200 #define PHY_RFIP_RXLDOCFG_CTRL_BIAS_LDO_BYP_EN 0x200 #define PHY_RFIP_RXLDOCFG_CTRL_BIAS_LDO_TST_POS 10 #define PHY_RFIP_RXLDOCFG_CTRL_BIAS_LDO_TST_LEN 1 #define PHY_RFIP_RXLDOCFG_CTRL_BIAS_LDO_TST_MSK 0x400 #define PHY_RFIP_RXLDOCFG_CTRL_BIAS_LDO_TST_EN 0x400 #define PHY_RFIP_RXLDOCFG_TESTBLOCK_LDO_PUP_POS 11 #define PHY_RFIP_RXLDOCFG_TESTBLOCK_LDO_PUP_LEN 1 #define PHY_RFIP_RXLDOCFG_TESTBLOCK_LDO_PUP_MSK 0x800 #define PHY_RFIP_RXLDOCFG_TESTBLOCK_LDO_PUP_EN 0x800 #define PHY_RFIP_RXLDOCFG_TESTBLOCK_LDO_LQB_POS 12 #define PHY_RFIP_RXLDOCFG_TESTBLOCK_LDO_LQB_LEN 1 #define PHY_RFIP_RXLDOCFG_TESTBLOCK_LDO_LQB_MSK 0x1000 #define PHY_RFIP_RXLDOCFG_TESTBLOCK_LDO_LQB_EN 0x1000 #define PHY_RFIP_RXLDOCFG_TESTBLOCK_LDO_BYP_POS 13 #define PHY_RFIP_RXLDOCFG_TESTBLOCK_LDO_BYP_LEN 1 #define PHY_RFIP_RXLDOCFG_TESTBLOCK_LDO_BYP_MSK 0x2000 #define PHY_RFIP_RXLDOCFG_TESTBLOCK_LDO_BYP_EN 0x2000 #define PHY_RFIP_RXLDOCFG_TESTBLOCK_LDO_TST_POS 14 #define PHY_RFIP_RXLDOCFG_TESTBLOCK_LDO_TST_LEN 18 #define PHY_RFIP_RXLDOCFG_TESTBLOCK_LDO_TST_MSK 0xffffc000 #define PHY_RFIP_RXLDOCFG_CONFIG_MODE_ABB_LDO_TEST 0x00000810 #define PHY_RFIP_RXLDOCFG_CONFIG_MODE_RX_TEST_MODE 0x00000800 #define PHY_RFIP_RXLDOCFG_CONFIG_MODE_ADC_LDO_TEST 0x00000880 #define PHY_RFIP_RXLDOCFG_CONFIG_MODE_RX_ABB_LDO_TESTMODE 0x00000010 #define PHY_RFIP_RXLDOCFG_CONFIG_MODE_RX_ADC_LDO_TESTMODE 0x00000080 #define PHY_RFIP_RXLDOCFG_CONFIG_MODE_RX_RF_LDO_TESTMODE 0x00000040 #define PHY_RFIP_RXLDOCFG_CONFIG_MODE_RF_LDO_TEST 0x00000840 #define PHY_RFIP_RXLDOCFG_CONFIG_MODE_RX_LO_LDO_TESTMODE 0x00000020 #define PHY_RFIP_RXLDOCFG_CONFIG_MODE_LO_LDO_TEST 0x00000820 #define PHY_RFIP_RXLDOCFG_CONFIG_MODE_RX_LO_LDO_TESTMODE9 0x00000100 #define PHY_RFIP_RXLDOCFG_CONFIG_MODE_DIG_LDO_TEST 0x00000900 #define PHY_RFIP_RXLDOCFG_CONFIG_MODE_RX_ACTIVE 0x00000000 /* This is automatically generated description for register: RFIP_RXPSDELAY */ #define PHY_RFIP_RXPSDELAY_RXBIASONDELAY_POS 0 #define PHY_RFIP_RXPSDELAY_RXBIASONDELAY_LEN 16 #define PHY_RFIP_RXPSDELAY_RXBIASONDELAY_MSK 0xffff #define PHY_RFIP_RXPSDELAY_RXLDOLQDELAY_POS 16 #define PHY_RFIP_RXPSDELAY_RXLDOLQDELAY_LEN 16 #define PHY_RFIP_RXPSDELAY_RXLDOLQDELAY_MSK 0xffff0000 #define PHY_RFIP_RXPSDELAY_CONFIG_MODE_DEFAULT 0x00500100 /* This is automatically generated description for register: TX_POWER_STATE */ #define PHY_RFIP_TXOFFPS_TX_DPLL_EN320_POS 0 #define PHY_RFIP_TXOFFPS_TX_DPLL_EN320_LEN 1 #define PHY_RFIP_TXOFFPS_TX_DPLL_EN320_MSK 0x1 #define PHY_RFIP_TXOFFPS_TX_DPLL_EN320_EN 0x1 #define PHY_RFIP_TXSUPPLIEDPS_TX_DPLL_EN320_POS 0 #define PHY_RFIP_TXSUPPLIEDPS_TX_DPLL_EN320_LEN 1 #define PHY_RFIP_TXSUPPLIEDPS_TX_DPLL_EN320_MSK 0x1 #define PHY_RFIP_TXSUPPLIEDPS_TX_DPLL_EN320_EN 0x1 #define PHY_RFIP_TXBIASPS_TX_DPLL_EN320_POS 0 #define PHY_RFIP_TXBIASPS_TX_DPLL_EN320_LEN 1 #define PHY_RFIP_TXBIASPS_TX_DPLL_EN320_MSK 0x1 #define PHY_RFIP_TXBIASPS_TX_DPLL_EN320_EN 0x1 #define PHY_RFIP_TXANAPS_TX_DPLL_EN320_POS 0 #define PHY_RFIP_TXANAPS_TX_DPLL_EN320_LEN 1 #define PHY_RFIP_TXANAPS_TX_DPLL_EN320_MSK 0x1 #define PHY_RFIP_TXANAPS_TX_DPLL_EN320_EN 0x1 #define PHY_RFIP_TXLQPS_TX_DPLL_EN320_POS 0 #define PHY_RFIP_TXLQPS_TX_DPLL_EN320_LEN 1 #define PHY_RFIP_TXLQPS_TX_DPLL_EN320_MSK 0x1 #define PHY_RFIP_TXLQPS_TX_DPLL_EN320_EN 0x1 #define PHY_RFIP_TXONPS_TX_DPLL_EN320_POS 0 #define PHY_RFIP_TXONPS_TX_DPLL_EN320_LEN 1 #define PHY_RFIP_TXONPS_TX_DPLL_EN320_MSK 0x1 #define PHY_RFIP_TXONPS_TX_DPLL_EN320_EN 0x1 #define PHY_RFIP_TXRFOFFPS_TX_DPLL_EN320_POS 0 #define PHY_RFIP_TXRFOFFPS_TX_DPLL_EN320_LEN 1 #define PHY_RFIP_TXRFOFFPS_TX_DPLL_EN320_MSK 0x1 #define PHY_RFIP_TXRFOFFPS_TX_DPLL_EN320_EN 0x1 #define PHY_RFIP_TXOFFPS_TX_DPLL_EN960_POS 1 #define PHY_RFIP_TXOFFPS_TX_DPLL_EN960_LEN 2 #define PHY_RFIP_TXOFFPS_TX_DPLL_EN960_MSK 0x6 #define PHY_RFIP_TXSUPPLIEDPS_TX_DPLL_EN960_POS 1 #define PHY_RFIP_TXSUPPLIEDPS_TX_DPLL_EN960_LEN 2 #define PHY_RFIP_TXSUPPLIEDPS_TX_DPLL_EN960_MSK 0x6 #define PHY_RFIP_TXBIASPS_TX_DPLL_EN960_POS 1 #define PHY_RFIP_TXBIASPS_TX_DPLL_EN960_LEN 2 #define PHY_RFIP_TXBIASPS_TX_DPLL_EN960_MSK 0x6 #define PHY_RFIP_TXANAPS_TX_DPLL_EN960_POS 1 #define PHY_RFIP_TXANAPS_TX_DPLL_EN960_LEN 2 #define PHY_RFIP_TXANAPS_TX_DPLL_EN960_MSK 0x6 #define PHY_RFIP_TXLQPS_TX_DPLL_EN960_POS 1 #define PHY_RFIP_TXLQPS_TX_DPLL_EN960_LEN 2 #define PHY_RFIP_TXLQPS_TX_DPLL_EN960_MSK 0x6 #define PHY_RFIP_TXONPS_TX_DPLL_EN960_POS 1 #define PHY_RFIP_TXONPS_TX_DPLL_EN960_LEN 2 #define PHY_RFIP_TXONPS_TX_DPLL_EN960_MSK 0x6 #define PHY_RFIP_TXRFOFFPS_TX_DPLL_EN960_POS 1 #define PHY_RFIP_TXRFOFFPS_TX_DPLL_EN960_LEN 2 #define PHY_RFIP_TXRFOFFPS_TX_DPLL_EN960_MSK 0x6 #define PHY_RFIP_TXOFFPS_TX_DPLL_EN480_POS 3 #define PHY_RFIP_TXOFFPS_TX_DPLL_EN480_LEN 1 #define PHY_RFIP_TXOFFPS_TX_DPLL_EN480_MSK 0x8 #define PHY_RFIP_TXOFFPS_TX_DPLL_EN480_EN 0x8 #define PHY_RFIP_TXSUPPLIEDPS_TX_DPLL_EN480_POS 3 #define PHY_RFIP_TXSUPPLIEDPS_TX_DPLL_EN480_LEN 1 #define PHY_RFIP_TXSUPPLIEDPS_TX_DPLL_EN480_MSK 0x8 #define PHY_RFIP_TXSUPPLIEDPS_TX_DPLL_EN480_EN 0x8 #define PHY_RFIP_TXBIASPS_TX_DPLL_EN480_POS 3 #define PHY_RFIP_TXBIASPS_TX_DPLL_EN480_LEN 1 #define PHY_RFIP_TXBIASPS_TX_DPLL_EN480_MSK 0x8 #define PHY_RFIP_TXBIASPS_TX_DPLL_EN480_EN 0x8 #define PHY_RFIP_TXANAPS_TX_DPLL_EN480_POS 3 #define PHY_RFIP_TXANAPS_TX_DPLL_EN480_LEN 1 #define PHY_RFIP_TXANAPS_TX_DPLL_EN480_MSK 0x8 #define PHY_RFIP_TXANAPS_TX_DPLL_EN480_EN 0x8 #define PHY_RFIP_TXLQPS_TX_DPLL_EN480_POS 3 #define PHY_RFIP_TXLQPS_TX_DPLL_EN480_LEN 1 #define PHY_RFIP_TXLQPS_TX_DPLL_EN480_MSK 0x8 #define PHY_RFIP_TXLQPS_TX_DPLL_EN480_EN 0x8 #define PHY_RFIP_TXONPS_TX_DPLL_EN480_POS 3 #define PHY_RFIP_TXONPS_TX_DPLL_EN480_LEN 1 #define PHY_RFIP_TXONPS_TX_DPLL_EN480_MSK 0x8 #define PHY_RFIP_TXONPS_TX_DPLL_EN480_EN 0x8 #define PHY_RFIP_TXRFOFFPS_TX_DPLL_EN480_POS 3 #define PHY_RFIP_TXRFOFFPS_TX_DPLL_EN480_LEN 1 #define PHY_RFIP_TXRFOFFPS_TX_DPLL_EN480_MSK 0x8 #define PHY_RFIP_TXRFOFFPS_TX_DPLL_EN480_EN 0x8 #define PHY_RFIP_TXOFFPS_TX_DACANA_PUP_POS 4 #define PHY_RFIP_TXOFFPS_TX_DACANA_PUP_LEN 1 #define PHY_RFIP_TXOFFPS_TX_DACANA_PUP_MSK 0x10 #define PHY_RFIP_TXOFFPS_TX_DACANA_PUP_EN 0x10 #define PHY_RFIP_TXSUPPLIEDPS_TX_DACANA_PUP_POS 4 #define PHY_RFIP_TXSUPPLIEDPS_TX_DACANA_PUP_LEN 1 #define PHY_RFIP_TXSUPPLIEDPS_TX_DACANA_PUP_MSK 0x10 #define PHY_RFIP_TXSUPPLIEDPS_TX_DACANA_PUP_EN 0x10 #define PHY_RFIP_TXBIASPS_TX_DACANA_PUP_POS 4 #define PHY_RFIP_TXBIASPS_TX_DACANA_PUP_LEN 1 #define PHY_RFIP_TXBIASPS_TX_DACANA_PUP_MSK 0x10 #define PHY_RFIP_TXBIASPS_TX_DACANA_PUP_EN 0x10 #define PHY_RFIP_TXANAPS_TX_DACANA_PUP_POS 4 #define PHY_RFIP_TXANAPS_TX_DACANA_PUP_LEN 1 #define PHY_RFIP_TXANAPS_TX_DACANA_PUP_MSK 0x10 #define PHY_RFIP_TXANAPS_TX_DACANA_PUP_EN 0x10 #define PHY_RFIP_TXLQPS_TX_DACANA_PUP_POS 4 #define PHY_RFIP_TXLQPS_TX_DACANA_PUP_LEN 1 #define PHY_RFIP_TXLQPS_TX_DACANA_PUP_MSK 0x10 #define PHY_RFIP_TXLQPS_TX_DACANA_PUP_EN 0x10 #define PHY_RFIP_TXONPS_TX_DACANA_PUP_POS 4 #define PHY_RFIP_TXONPS_TX_DACANA_PUP_LEN 1 #define PHY_RFIP_TXONPS_TX_DACANA_PUP_MSK 0x10 #define PHY_RFIP_TXONPS_TX_DACANA_PUP_EN 0x10 #define PHY_RFIP_TXRFOFFPS_TX_DACANA_PUP_POS 4 #define PHY_RFIP_TXRFOFFPS_TX_DACANA_PUP_LEN 1 #define PHY_RFIP_TXRFOFFPS_TX_DACANA_PUP_MSK 0x10 #define PHY_RFIP_TXRFOFFPS_TX_DACANA_PUP_EN 0x10 #define PHY_RFIP_TXOFFPS_TX_ABB_PUP_POS 5 #define PHY_RFIP_TXOFFPS_TX_ABB_PUP_LEN 1 #define PHY_RFIP_TXOFFPS_TX_ABB_PUP_MSK 0x20 #define PHY_RFIP_TXOFFPS_TX_ABB_PUP_EN 0x20 #define PHY_RFIP_TXSUPPLIEDPS_TX_ABB_PUP_POS 5 #define PHY_RFIP_TXSUPPLIEDPS_TX_ABB_PUP_LEN 1 #define PHY_RFIP_TXSUPPLIEDPS_TX_ABB_PUP_MSK 0x20 #define PHY_RFIP_TXSUPPLIEDPS_TX_ABB_PUP_EN 0x20 #define PHY_RFIP_TXBIASPS_TX_ABB_PUP_POS 5 #define PHY_RFIP_TXBIASPS_TX_ABB_PUP_LEN 1 #define PHY_RFIP_TXBIASPS_TX_ABB_PUP_MSK 0x20 #define PHY_RFIP_TXBIASPS_TX_ABB_PUP_EN 0x20 #define PHY_RFIP_TXANAPS_TX_ABB_PUP_POS 5 #define PHY_RFIP_TXANAPS_TX_ABB_PUP_LEN 1 #define PHY_RFIP_TXANAPS_TX_ABB_PUP_MSK 0x20 #define PHY_RFIP_TXANAPS_TX_ABB_PUP_EN 0x20 #define PHY_RFIP_TXLQPS_TX_ABB_PUP_POS 5 #define PHY_RFIP_TXLQPS_TX_ABB_PUP_LEN 1 #define PHY_RFIP_TXLQPS_TX_ABB_PUP_MSK 0x20 #define PHY_RFIP_TXLQPS_TX_ABB_PUP_EN 0x20 #define PHY_RFIP_TXONPS_TX_ABB_PUP_POS 5 #define PHY_RFIP_TXONPS_TX_ABB_PUP_LEN 1 #define PHY_RFIP_TXONPS_TX_ABB_PUP_MSK 0x20 #define PHY_RFIP_TXONPS_TX_ABB_PUP_EN 0x20 #define PHY_RFIP_TXRFOFFPS_TX_ABB_PUP_POS 5 #define PHY_RFIP_TXRFOFFPS_TX_ABB_PUP_LEN 1 #define PHY_RFIP_TXRFOFFPS_TX_ABB_PUP_MSK 0x20 #define PHY_RFIP_TXRFOFFPS_TX_ABB_PUP_EN 0x20 #define PHY_RFIP_TXOFFPS_TX_LO_PUP_POS 6 #define PHY_RFIP_TXOFFPS_TX_LO_PUP_LEN 1 #define PHY_RFIP_TXOFFPS_TX_LO_PUP_MSK 0x40 #define PHY_RFIP_TXOFFPS_TX_LO_PUP_EN 0x40 #define PHY_RFIP_TXSUPPLIEDPS_TX_LO_PUP_POS 6 #define PHY_RFIP_TXSUPPLIEDPS_TX_LO_PUP_LEN 1 #define PHY_RFIP_TXSUPPLIEDPS_TX_LO_PUP_MSK 0x40 #define PHY_RFIP_TXSUPPLIEDPS_TX_LO_PUP_EN 0x40 #define PHY_RFIP_TXBIASPS_TX_LO_PUP_POS 6 #define PHY_RFIP_TXBIASPS_TX_LO_PUP_LEN 1 #define PHY_RFIP_TXBIASPS_TX_LO_PUP_MSK 0x40 #define PHY_RFIP_TXBIASPS_TX_LO_PUP_EN 0x40 #define PHY_RFIP_TXANAPS_TX_LO_PUP_POS 6 #define PHY_RFIP_TXANAPS_TX_LO_PUP_LEN 1 #define PHY_RFIP_TXANAPS_TX_LO_PUP_MSK 0x40 #define PHY_RFIP_TXANAPS_TX_LO_PUP_EN 0x40 #define PHY_RFIP_TXLQPS_TX_LO_PUP_POS 6 #define PHY_RFIP_TXLQPS_TX_LO_PUP_LEN 1 #define PHY_RFIP_TXLQPS_TX_LO_PUP_MSK 0x40 #define PHY_RFIP_TXLQPS_TX_LO_PUP_EN 0x40 #define PHY_RFIP_TXONPS_TX_LO_PUP_POS 6 #define PHY_RFIP_TXONPS_TX_LO_PUP_LEN 1 #define PHY_RFIP_TXONPS_TX_LO_PUP_MSK 0x40 #define PHY_RFIP_TXONPS_TX_LO_PUP_EN 0x40 #define PHY_RFIP_TXRFOFFPS_TX_LO_PUP_POS 6 #define PHY_RFIP_TXRFOFFPS_TX_LO_PUP_LEN 1 #define PHY_RFIP_TXRFOFFPS_TX_LO_PUP_MSK 0x40 #define PHY_RFIP_TXRFOFFPS_TX_LO_PUP_EN 0x40 #define PHY_RFIP_TXOFFPS_TX_RF_PUP_POS 7 #define PHY_RFIP_TXOFFPS_TX_RF_PUP_LEN 2 #define PHY_RFIP_TXOFFPS_TX_RF_PUP_MSK 0x180 #define PHY_RFIP_TXSUPPLIEDPS_TX_RF_PUP_POS 7 #define PHY_RFIP_TXSUPPLIEDPS_TX_RF_PUP_LEN 2 #define PHY_RFIP_TXSUPPLIEDPS_TX_RF_PUP_MSK 0x180 #define PHY_RFIP_TXBIASPS_TX_RF_PUP_POS 7 #define PHY_RFIP_TXBIASPS_TX_RF_PUP_LEN 2 #define PHY_RFIP_TXBIASPS_TX_RF_PUP_MSK 0x180 #define PHY_RFIP_TXANAPS_TX_RF_PUP_POS 7 #define PHY_RFIP_TXANAPS_TX_RF_PUP_LEN 2 #define PHY_RFIP_TXANAPS_TX_RF_PUP_MSK 0x180 #define PHY_RFIP_TXLQPS_TX_RF_PUP_POS 7 #define PHY_RFIP_TXLQPS_TX_RF_PUP_LEN 2 #define PHY_RFIP_TXLQPS_TX_RF_PUP_MSK 0x180 #define PHY_RFIP_TXONPS_TX_RF_PUP_POS 7 #define PHY_RFIP_TXONPS_TX_RF_PUP_LEN 2 #define PHY_RFIP_TXONPS_TX_RF_PUP_MSK 0x180 #define PHY_RFIP_TXRFOFFPS_TX_RF_PUP_POS 7 #define PHY_RFIP_TXRFOFFPS_TX_RF_PUP_LEN 2 #define PHY_RFIP_TXRFOFFPS_TX_RF_PUP_MSK 0x180 #define PHY_RFIP_TXOFFPS_TX_ADC_PUP_POS 9 #define PHY_RFIP_TXOFFPS_TX_ADC_PUP_LEN 1 #define PHY_RFIP_TXOFFPS_TX_ADC_PUP_MSK 0x200 #define PHY_RFIP_TXOFFPS_TX_ADC_PUP_EN 0x200 #define PHY_RFIP_TXSUPPLIEDPS_TX_ADC_PUP_POS 9 #define PHY_RFIP_TXSUPPLIEDPS_TX_ADC_PUP_LEN 1 #define PHY_RFIP_TXSUPPLIEDPS_TX_ADC_PUP_MSK 0x200 #define PHY_RFIP_TXSUPPLIEDPS_TX_ADC_PUP_EN 0x200 #define PHY_RFIP_TXBIASPS_TX_ADC_PUP_POS 9 #define PHY_RFIP_TXBIASPS_TX_ADC_PUP_LEN 1 #define PHY_RFIP_TXBIASPS_TX_ADC_PUP_MSK 0x200 #define PHY_RFIP_TXBIASPS_TX_ADC_PUP_EN 0x200 #define PHY_RFIP_TXANAPS_TX_ADC_PUP_POS 9 #define PHY_RFIP_TXANAPS_TX_ADC_PUP_LEN 1 #define PHY_RFIP_TXANAPS_TX_ADC_PUP_MSK 0x200 #define PHY_RFIP_TXANAPS_TX_ADC_PUP_EN 0x200 #define PHY_RFIP_TXLQPS_TX_ADC_PUP_POS 9 #define PHY_RFIP_TXLQPS_TX_ADC_PUP_LEN 1 #define PHY_RFIP_TXLQPS_TX_ADC_PUP_MSK 0x200 #define PHY_RFIP_TXLQPS_TX_ADC_PUP_EN 0x200 #define PHY_RFIP_TXONPS_TX_ADC_PUP_POS 9 #define PHY_RFIP_TXONPS_TX_ADC_PUP_LEN 1 #define PHY_RFIP_TXONPS_TX_ADC_PUP_MSK 0x200 #define PHY_RFIP_TXONPS_TX_ADC_PUP_EN 0x200 #define PHY_RFIP_TXRFOFFPS_TX_ADC_PUP_POS 9 #define PHY_RFIP_TXRFOFFPS_TX_ADC_PUP_LEN 1 #define PHY_RFIP_TXRFOFFPS_TX_ADC_PUP_MSK 0x200 #define PHY_RFIP_TXRFOFFPS_TX_ADC_PUP_EN 0x200 #define PHY_RFIP_TXOFFPS_TX_ADC_PCLEN_CFG_POS 10 #define PHY_RFIP_TXOFFPS_TX_ADC_PCLEN_CFG_LEN 1 #define PHY_RFIP_TXOFFPS_TX_ADC_PCLEN_CFG_MSK 0x400 #define PHY_RFIP_TXOFFPS_TX_ADC_PCLEN_CFG_EN 0x400 #define PHY_RFIP_TXSUPPLIEDPS_TX_ADC_PCLEN_CFG_POS 10 #define PHY_RFIP_TXSUPPLIEDPS_TX_ADC_PCLEN_CFG_LEN 1 #define PHY_RFIP_TXSUPPLIEDPS_TX_ADC_PCLEN_CFG_MSK 0x400 #define PHY_RFIP_TXSUPPLIEDPS_TX_ADC_PCLEN_CFG_EN 0x400 #define PHY_RFIP_TXBIASPS_TX_ADC_PCLEN_CFG_POS 10 #define PHY_RFIP_TXBIASPS_TX_ADC_PCLEN_CFG_LEN 1 #define PHY_RFIP_TXBIASPS_TX_ADC_PCLEN_CFG_MSK 0x400 #define PHY_RFIP_TXBIASPS_TX_ADC_PCLEN_CFG_EN 0x400 #define PHY_RFIP_TXANAPS_TX_ADC_PCLEN_CFG_POS 10 #define PHY_RFIP_TXANAPS_TX_ADC_PCLEN_CFG_LEN 1 #define PHY_RFIP_TXANAPS_TX_ADC_PCLEN_CFG_MSK 0x400 #define PHY_RFIP_TXANAPS_TX_ADC_PCLEN_CFG_EN 0x400 #define PHY_RFIP_TXLQPS_TX_ADC_PCLEN_CFG_POS 10 #define PHY_RFIP_TXLQPS_TX_ADC_PCLEN_CFG_LEN 1 #define PHY_RFIP_TXLQPS_TX_ADC_PCLEN_CFG_MSK 0x400 #define PHY_RFIP_TXLQPS_TX_ADC_PCLEN_CFG_EN 0x400 #define PHY_RFIP_TXONPS_TX_ADC_PCLEN_CFG_POS 10 #define PHY_RFIP_TXONPS_TX_ADC_PCLEN_CFG_LEN 1 #define PHY_RFIP_TXONPS_TX_ADC_PCLEN_CFG_MSK 0x400 #define PHY_RFIP_TXONPS_TX_ADC_PCLEN_CFG_EN 0x400 #define PHY_RFIP_TXRFOFFPS_TX_ADC_PCLEN_CFG_POS 10 #define PHY_RFIP_TXRFOFFPS_TX_ADC_PCLEN_CFG_LEN 1 #define PHY_RFIP_TXRFOFFPS_TX_ADC_PCLEN_CFG_MSK 0x400 #define PHY_RFIP_TXRFOFFPS_TX_ADC_PCLEN_CFG_EN 0x400 #define PHY_RFIP_TXOFFPS_TX_BLEEDCURRENT_PUP_POS 11 #define PHY_RFIP_TXOFFPS_TX_BLEEDCURRENT_PUP_LEN 1 #define PHY_RFIP_TXOFFPS_TX_BLEEDCURRENT_PUP_MSK 0x800 #define PHY_RFIP_TXOFFPS_TX_BLEEDCURRENT_PUP_EN 0x800 #define PHY_RFIP_TXSUPPLIEDPS_TX_BLEEDCURRENT_PUP_POS 11 #define PHY_RFIP_TXSUPPLIEDPS_TX_BLEEDCURRENT_PUP_LEN 1 #define PHY_RFIP_TXSUPPLIEDPS_TX_BLEEDCURRENT_PUP_MSK 0x800 #define PHY_RFIP_TXSUPPLIEDPS_TX_BLEEDCURRENT_PUP_EN 0x800 #define PHY_RFIP_TXBIASPS_TX_BLEEDCURRENT_PUP_POS 11 #define PHY_RFIP_TXBIASPS_TX_BLEEDCURRENT_PUP_LEN 1 #define PHY_RFIP_TXBIASPS_TX_BLEEDCURRENT_PUP_MSK 0x800 #define PHY_RFIP_TXBIASPS_TX_BLEEDCURRENT_PUP_EN 0x800 #define PHY_RFIP_TXANAPS_TX_BLEEDCURRENT_PUP_POS 11 #define PHY_RFIP_TXANAPS_TX_BLEEDCURRENT_PUP_LEN 1 #define PHY_RFIP_TXANAPS_TX_BLEEDCURRENT_PUP_MSK 0x800 #define PHY_RFIP_TXANAPS_TX_BLEEDCURRENT_PUP_EN 0x800 #define PHY_RFIP_TXLQPS_TX_BLEEDCURRENT_PUP_POS 11 #define PHY_RFIP_TXLQPS_TX_BLEEDCURRENT_PUP_LEN 1 #define PHY_RFIP_TXLQPS_TX_BLEEDCURRENT_PUP_MSK 0x800 #define PHY_RFIP_TXLQPS_TX_BLEEDCURRENT_PUP_EN 0x800 #define PHY_RFIP_TXONPS_TX_BLEEDCURRENT_PUP_POS 11 #define PHY_RFIP_TXONPS_TX_BLEEDCURRENT_PUP_LEN 1 #define PHY_RFIP_TXONPS_TX_BLEEDCURRENT_PUP_MSK 0x800 #define PHY_RFIP_TXONPS_TX_BLEEDCURRENT_PUP_EN 0x800 #define PHY_RFIP_TXRFOFFPS_TX_BLEEDCURRENT_PUP_POS 11 #define PHY_RFIP_TXRFOFFPS_TX_BLEEDCURRENT_PUP_LEN 1 #define PHY_RFIP_TXRFOFFPS_TX_BLEEDCURRENT_PUP_MSK 0x800 #define PHY_RFIP_TXRFOFFPS_TX_BLEEDCURRENT_PUP_EN 0x800 #define PHY_RFIP_TXOFFPS_TX_DIG_RST_CFG_POS 12 #define PHY_RFIP_TXOFFPS_TX_DIG_RST_CFG_LEN 1 #define PHY_RFIP_TXOFFPS_TX_DIG_RST_CFG_MSK 0x1000 #define PHY_RFIP_TXOFFPS_TX_DIG_RST_CFG_EN 0x1000 #define PHY_RFIP_TXSUPPLIEDPS_TX_DIG_RST_CFG_POS 12 #define PHY_RFIP_TXSUPPLIEDPS_TX_DIG_RST_CFG_LEN 1 #define PHY_RFIP_TXSUPPLIEDPS_TX_DIG_RST_CFG_MSK 0x1000 #define PHY_RFIP_TXSUPPLIEDPS_TX_DIG_RST_CFG_EN 0x1000 #define PHY_RFIP_TXBIASPS_TX_DIG_RST_CFG_POS 12 #define PHY_RFIP_TXBIASPS_TX_DIG_RST_CFG_LEN 1 #define PHY_RFIP_TXBIASPS_TX_DIG_RST_CFG_MSK 0x1000 #define PHY_RFIP_TXBIASPS_TX_DIG_RST_CFG_EN 0x1000 #define PHY_RFIP_TXANAPS_TX_DIG_RST_CFG_POS 12 #define PHY_RFIP_TXANAPS_TX_DIG_RST_CFG_LEN 1 #define PHY_RFIP_TXANAPS_TX_DIG_RST_CFG_MSK 0x1000 #define PHY_RFIP_TXANAPS_TX_DIG_RST_CFG_EN 0x1000 #define PHY_RFIP_TXLQPS_TX_DIG_RST_CFG_POS 12 #define PHY_RFIP_TXLQPS_TX_DIG_RST_CFG_LEN 1 #define PHY_RFIP_TXLQPS_TX_DIG_RST_CFG_MSK 0x1000 #define PHY_RFIP_TXLQPS_TX_DIG_RST_CFG_EN 0x1000 #define PHY_RFIP_TXONPS_TX_DIG_RST_CFG_POS 12 #define PHY_RFIP_TXONPS_TX_DIG_RST_CFG_LEN 1 #define PHY_RFIP_TXONPS_TX_DIG_RST_CFG_MSK 0x1000 #define PHY_RFIP_TXONPS_TX_DIG_RST_CFG_EN 0x1000 #define PHY_RFIP_TXRFOFFPS_TX_DIG_RST_CFG_POS 12 #define PHY_RFIP_TXRFOFFPS_TX_DIG_RST_CFG_LEN 1 #define PHY_RFIP_TXRFOFFPS_TX_DIG_RST_CFG_MSK 0x1000 #define PHY_RFIP_TXRFOFFPS_TX_DIG_RST_CFG_EN 0x1000 #define PHY_RFIP_TXOFFPS_TX_TXDD_CLOCK_EN_POS 13 #define PHY_RFIP_TXOFFPS_TX_TXDD_CLOCK_EN_LEN 1 #define PHY_RFIP_TXOFFPS_TX_TXDD_CLOCK_EN_MSK 0x2000 #define PHY_RFIP_TXOFFPS_TX_TXDD_CLOCK_EN_EN 0x2000 #define PHY_RFIP_TXSUPPLIEDPS_TX_TXDD_CLOCK_EN_POS 13 #define PHY_RFIP_TXSUPPLIEDPS_TX_TXDD_CLOCK_EN_LEN 1 #define PHY_RFIP_TXSUPPLIEDPS_TX_TXDD_CLOCK_EN_MSK 0x2000 #define PHY_RFIP_TXSUPPLIEDPS_TX_TXDD_CLOCK_EN_EN 0x2000 #define PHY_RFIP_TXBIASPS_TX_TXDD_CLOCK_EN_POS 13 #define PHY_RFIP_TXBIASPS_TX_TXDD_CLOCK_EN_LEN 1 #define PHY_RFIP_TXBIASPS_TX_TXDD_CLOCK_EN_MSK 0x2000 #define PHY_RFIP_TXBIASPS_TX_TXDD_CLOCK_EN_EN 0x2000 #define PHY_RFIP_TXANAPS_TX_TXDD_CLOCK_EN_POS 13 #define PHY_RFIP_TXANAPS_TX_TXDD_CLOCK_EN_LEN 1 #define PHY_RFIP_TXANAPS_TX_TXDD_CLOCK_EN_MSK 0x2000 #define PHY_RFIP_TXANAPS_TX_TXDD_CLOCK_EN_EN 0x2000 #define PHY_RFIP_TXLQPS_TX_TXDD_CLOCK_EN_POS 13 #define PHY_RFIP_TXLQPS_TX_TXDD_CLOCK_EN_LEN 1 #define PHY_RFIP_TXLQPS_TX_TXDD_CLOCK_EN_MSK 0x2000 #define PHY_RFIP_TXLQPS_TX_TXDD_CLOCK_EN_EN 0x2000 #define PHY_RFIP_TXONPS_TX_TXDD_CLOCK_EN_POS 13 #define PHY_RFIP_TXONPS_TX_TXDD_CLOCK_EN_LEN 1 #define PHY_RFIP_TXONPS_TX_TXDD_CLOCK_EN_MSK 0x2000 #define PHY_RFIP_TXONPS_TX_TXDD_CLOCK_EN_EN 0x2000 #define PHY_RFIP_TXRFOFFPS_TX_TXDD_CLOCK_EN_POS 13 #define PHY_RFIP_TXRFOFFPS_TX_TXDD_CLOCK_EN_LEN 1 #define PHY_RFIP_TXRFOFFPS_TX_TXDD_CLOCK_EN_MSK 0x2000 #define PHY_RFIP_TXRFOFFPS_TX_TXDD_CLOCK_EN_EN 0x2000 #define PHY_RFIP_TXOFFPS_TX_LO_HB_DIV_PUP_POS 14 #define PHY_RFIP_TXOFFPS_TX_LO_HB_DIV_PUP_LEN 1 #define PHY_RFIP_TXOFFPS_TX_LO_HB_DIV_PUP_MSK 0x4000 #define PHY_RFIP_TXOFFPS_TX_LO_HB_DIV_PUP_EN 0x4000 #define PHY_RFIP_TXSUPPLIEDPS_TX_LO_HB_DIV_PUP_POS 14 #define PHY_RFIP_TXSUPPLIEDPS_TX_LO_HB_DIV_PUP_LEN 1 #define PHY_RFIP_TXSUPPLIEDPS_TX_LO_HB_DIV_PUP_MSK 0x4000 #define PHY_RFIP_TXSUPPLIEDPS_TX_LO_HB_DIV_PUP_EN 0x4000 #define PHY_RFIP_TXBIASPS_TX_LO_HB_DIV_PUP_POS 14 #define PHY_RFIP_TXBIASPS_TX_LO_HB_DIV_PUP_LEN 1 #define PHY_RFIP_TXBIASPS_TX_LO_HB_DIV_PUP_MSK 0x4000 #define PHY_RFIP_TXBIASPS_TX_LO_HB_DIV_PUP_EN 0x4000 #define PHY_RFIP_TXANAPS_TX_LO_HB_DIV_PUP_POS 14 #define PHY_RFIP_TXANAPS_TX_LO_HB_DIV_PUP_LEN 1 #define PHY_RFIP_TXANAPS_TX_LO_HB_DIV_PUP_MSK 0x4000 #define PHY_RFIP_TXANAPS_TX_LO_HB_DIV_PUP_EN 0x4000 #define PHY_RFIP_TXLQPS_TX_LO_HB_DIV_PUP_POS 14 #define PHY_RFIP_TXLQPS_TX_LO_HB_DIV_PUP_LEN 1 #define PHY_RFIP_TXLQPS_TX_LO_HB_DIV_PUP_MSK 0x4000 #define PHY_RFIP_TXLQPS_TX_LO_HB_DIV_PUP_EN 0x4000 #define PHY_RFIP_TXONPS_TX_LO_HB_DIV_PUP_POS 14 #define PHY_RFIP_TXONPS_TX_LO_HB_DIV_PUP_LEN 1 #define PHY_RFIP_TXONPS_TX_LO_HB_DIV_PUP_MSK 0x4000 #define PHY_RFIP_TXONPS_TX_LO_HB_DIV_PUP_EN 0x4000 #define PHY_RFIP_TXRFOFFPS_TX_LO_HB_DIV_PUP_POS 14 #define PHY_RFIP_TXRFOFFPS_TX_LO_HB_DIV_PUP_LEN 1 #define PHY_RFIP_TXRFOFFPS_TX_LO_HB_DIV_PUP_MSK 0x4000 #define PHY_RFIP_TXRFOFFPS_TX_LO_HB_DIV_PUP_EN 0x4000 #define PHY_RFIP_TXOFFPS_TX_LO_LB_BUF_PUP_POS 15 #define PHY_RFIP_TXOFFPS_TX_LO_LB_BUF_PUP_LEN 1 #define PHY_RFIP_TXOFFPS_TX_LO_LB_BUF_PUP_MSK 0x8000 #define PHY_RFIP_TXOFFPS_TX_LO_LB_BUF_PUP_EN 0x8000 #define PHY_RFIP_TXSUPPLIEDPS_TX_LO_LB_BUF_PUP_POS 15 #define PHY_RFIP_TXSUPPLIEDPS_TX_LO_LB_BUF_PUP_LEN 1 #define PHY_RFIP_TXSUPPLIEDPS_TX_LO_LB_BUF_PUP_MSK 0x8000 #define PHY_RFIP_TXSUPPLIEDPS_TX_LO_LB_BUF_PUP_EN 0x8000 #define PHY_RFIP_TXBIASPS_TX_LO_LB_BUF_PUP_POS 15 #define PHY_RFIP_TXBIASPS_TX_LO_LB_BUF_PUP_LEN 1 #define PHY_RFIP_TXBIASPS_TX_LO_LB_BUF_PUP_MSK 0x8000 #define PHY_RFIP_TXBIASPS_TX_LO_LB_BUF_PUP_EN 0x8000 #define PHY_RFIP_TXANAPS_TX_LO_LB_BUF_PUP_POS 15 #define PHY_RFIP_TXANAPS_TX_LO_LB_BUF_PUP_LEN 1 #define PHY_RFIP_TXANAPS_TX_LO_LB_BUF_PUP_MSK 0x8000 #define PHY_RFIP_TXANAPS_TX_LO_LB_BUF_PUP_EN 0x8000 #define PHY_RFIP_TXLQPS_TX_LO_LB_BUF_PUP_POS 15 #define PHY_RFIP_TXLQPS_TX_LO_LB_BUF_PUP_LEN 1 #define PHY_RFIP_TXLQPS_TX_LO_LB_BUF_PUP_MSK 0x8000 #define PHY_RFIP_TXLQPS_TX_LO_LB_BUF_PUP_EN 0x8000 #define PHY_RFIP_TXONPS_TX_LO_LB_BUF_PUP_POS 15 #define PHY_RFIP_TXONPS_TX_LO_LB_BUF_PUP_LEN 1 #define PHY_RFIP_TXONPS_TX_LO_LB_BUF_PUP_MSK 0x8000 #define PHY_RFIP_TXONPS_TX_LO_LB_BUF_PUP_EN 0x8000 #define PHY_RFIP_TXRFOFFPS_TX_LO_LB_BUF_PUP_POS 15 #define PHY_RFIP_TXRFOFFPS_TX_LO_LB_BUF_PUP_LEN 1 #define PHY_RFIP_TXRFOFFPS_TX_LO_LB_BUF_PUP_MSK 0x8000 #define PHY_RFIP_TXRFOFFPS_TX_LO_LB_BUF_PUP_EN 0x8000 #define PHY_RFIP_TXOFFPS_TX_LO_LB_2_5_SEL_POS 16 #define PHY_RFIP_TXOFFPS_TX_LO_LB_2_5_SEL_LEN 1 #define PHY_RFIP_TXOFFPS_TX_LO_LB_2_5_SEL_MSK 0x10000 #define PHY_RFIP_TXOFFPS_TX_LO_LB_2_5_SEL_EN 0x10000 #define PHY_RFIP_TXSUPPLIEDPS_TX_LO_LB_2_5_SEL_POS 16 #define PHY_RFIP_TXSUPPLIEDPS_TX_LO_LB_2_5_SEL_LEN 1 #define PHY_RFIP_TXSUPPLIEDPS_TX_LO_LB_2_5_SEL_MSK 0x10000 #define PHY_RFIP_TXSUPPLIEDPS_TX_LO_LB_2_5_SEL_EN 0x10000 #define PHY_RFIP_TXBIASPS_TX_LO_LB_2_5_SEL_POS 16 #define PHY_RFIP_TXBIASPS_TX_LO_LB_2_5_SEL_LEN 1 #define PHY_RFIP_TXBIASPS_TX_LO_LB_2_5_SEL_MSK 0x10000 #define PHY_RFIP_TXBIASPS_TX_LO_LB_2_5_SEL_EN 0x10000 #define PHY_RFIP_TXANAPS_TX_LO_LB_2_5_SEL_POS 16 #define PHY_RFIP_TXANAPS_TX_LO_LB_2_5_SEL_LEN 1 #define PHY_RFIP_TXANAPS_TX_LO_LB_2_5_SEL_MSK 0x10000 #define PHY_RFIP_TXANAPS_TX_LO_LB_2_5_SEL_EN 0x10000 #define PHY_RFIP_TXLQPS_TX_LO_LB_2_5_SEL_POS 16 #define PHY_RFIP_TXLQPS_TX_LO_LB_2_5_SEL_LEN 1 #define PHY_RFIP_TXLQPS_TX_LO_LB_2_5_SEL_MSK 0x10000 #define PHY_RFIP_TXLQPS_TX_LO_LB_2_5_SEL_EN 0x10000 #define PHY_RFIP_TXONPS_TX_LO_LB_2_5_SEL_POS 16 #define PHY_RFIP_TXONPS_TX_LO_LB_2_5_SEL_LEN 1 #define PHY_RFIP_TXONPS_TX_LO_LB_2_5_SEL_MSK 0x10000 #define PHY_RFIP_TXONPS_TX_LO_LB_2_5_SEL_EN 0x10000 #define PHY_RFIP_TXRFOFFPS_TX_LO_LB_2_5_SEL_POS 16 #define PHY_RFIP_TXRFOFFPS_TX_LO_LB_2_5_SEL_LEN 1 #define PHY_RFIP_TXRFOFFPS_TX_LO_LB_2_5_SEL_MSK 0x10000 #define PHY_RFIP_TXRFOFFPS_TX_LO_LB_2_5_SEL_EN 0x10000 #define PHY_RFIP_TXOFFPS_TX_LO_LB_2_5_INIT_POS 17 #define PHY_RFIP_TXOFFPS_TX_LO_LB_2_5_INIT_LEN 1 #define PHY_RFIP_TXOFFPS_TX_LO_LB_2_5_INIT_MSK 0x20000 #define PHY_RFIP_TXOFFPS_TX_LO_LB_2_5_INIT_EN 0x20000 #define PHY_RFIP_TXSUPPLIEDPS_TX_LO_LB_2_5_INIT_POS 17 #define PHY_RFIP_TXSUPPLIEDPS_TX_LO_LB_2_5_INIT_LEN 1 #define PHY_RFIP_TXSUPPLIEDPS_TX_LO_LB_2_5_INIT_MSK 0x20000 #define PHY_RFIP_TXSUPPLIEDPS_TX_LO_LB_2_5_INIT_EN 0x20000 #define PHY_RFIP_TXBIASPS_TX_LO_LB_2_5_INIT_POS 17 #define PHY_RFIP_TXBIASPS_TX_LO_LB_2_5_INIT_LEN 1 #define PHY_RFIP_TXBIASPS_TX_LO_LB_2_5_INIT_MSK 0x20000 #define PHY_RFIP_TXBIASPS_TX_LO_LB_2_5_INIT_EN 0x20000 #define PHY_RFIP_TXANAPS_TX_LO_LB_2_5_INIT_POS 17 #define PHY_RFIP_TXANAPS_TX_LO_LB_2_5_INIT_LEN 1 #define PHY_RFIP_TXANAPS_TX_LO_LB_2_5_INIT_MSK 0x20000 #define PHY_RFIP_TXANAPS_TX_LO_LB_2_5_INIT_EN 0x20000 #define PHY_RFIP_TXLQPS_TX_LO_LB_2_5_INIT_POS 17 #define PHY_RFIP_TXLQPS_TX_LO_LB_2_5_INIT_LEN 1 #define PHY_RFIP_TXLQPS_TX_LO_LB_2_5_INIT_MSK 0x20000 #define PHY_RFIP_TXLQPS_TX_LO_LB_2_5_INIT_EN 0x20000 #define PHY_RFIP_TXONPS_TX_LO_LB_2_5_INIT_POS 17 #define PHY_RFIP_TXONPS_TX_LO_LB_2_5_INIT_LEN 1 #define PHY_RFIP_TXONPS_TX_LO_LB_2_5_INIT_MSK 0x20000 #define PHY_RFIP_TXONPS_TX_LO_LB_2_5_INIT_EN 0x20000 #define PHY_RFIP_TXRFOFFPS_TX_LO_LB_2_5_INIT_POS 17 #define PHY_RFIP_TXRFOFFPS_TX_LO_LB_2_5_INIT_LEN 1 #define PHY_RFIP_TXRFOFFPS_TX_LO_LB_2_5_INIT_MSK 0x20000 #define PHY_RFIP_TXRFOFFPS_TX_LO_LB_2_5_INIT_EN 0x20000 #define PHY_RFIP_TXOFFPS_TX_PA_DRIVER_PUP_POS 18 #define PHY_RFIP_TXOFFPS_TX_PA_DRIVER_PUP_LEN 1 #define PHY_RFIP_TXOFFPS_TX_PA_DRIVER_PUP_MSK 0x40000 #define PHY_RFIP_TXOFFPS_TX_PA_DRIVER_PUP_EN 0x40000 #define PHY_RFIP_TXSUPPLIEDPS_TX_PA_DRIVER_PUP_POS 18 #define PHY_RFIP_TXSUPPLIEDPS_TX_PA_DRIVER_PUP_LEN 1 #define PHY_RFIP_TXSUPPLIEDPS_TX_PA_DRIVER_PUP_MSK 0x40000 #define PHY_RFIP_TXSUPPLIEDPS_TX_PA_DRIVER_PUP_EN 0x40000 #define PHY_RFIP_TXBIASPS_TX_PA_DRIVER_PUP_POS 18 #define PHY_RFIP_TXBIASPS_TX_PA_DRIVER_PUP_LEN 1 #define PHY_RFIP_TXBIASPS_TX_PA_DRIVER_PUP_MSK 0x40000 #define PHY_RFIP_TXBIASPS_TX_PA_DRIVER_PUP_EN 0x40000 #define PHY_RFIP_TXANAPS_TX_PA_DRIVER_PUP_POS 18 #define PHY_RFIP_TXANAPS_TX_PA_DRIVER_PUP_LEN 1 #define PHY_RFIP_TXANAPS_TX_PA_DRIVER_PUP_MSK 0x40000 #define PHY_RFIP_TXANAPS_TX_PA_DRIVER_PUP_EN 0x40000 #define PHY_RFIP_TXLQPS_TX_PA_DRIVER_PUP_POS 18 #define PHY_RFIP_TXLQPS_TX_PA_DRIVER_PUP_LEN 1 #define PHY_RFIP_TXLQPS_TX_PA_DRIVER_PUP_MSK 0x40000 #define PHY_RFIP_TXLQPS_TX_PA_DRIVER_PUP_EN 0x40000 #define PHY_RFIP_TXONPS_TX_PA_DRIVER_PUP_POS 18 #define PHY_RFIP_TXONPS_TX_PA_DRIVER_PUP_LEN 1 #define PHY_RFIP_TXONPS_TX_PA_DRIVER_PUP_MSK 0x40000 #define PHY_RFIP_TXONPS_TX_PA_DRIVER_PUP_EN 0x40000 #define PHY_RFIP_TXRFOFFPS_TX_PA_DRIVER_PUP_POS 18 #define PHY_RFIP_TXRFOFFPS_TX_PA_DRIVER_PUP_LEN 1 #define PHY_RFIP_TXRFOFFPS_TX_PA_DRIVER_PUP_MSK 0x40000 #define PHY_RFIP_TXRFOFFPS_TX_PA_DRIVER_PUP_EN 0x40000 #define PHY_RFIP_TXOFFPS_TX_PA_POWER_PUP_POS 19 #define PHY_RFIP_TXOFFPS_TX_PA_POWER_PUP_LEN 1 #define PHY_RFIP_TXOFFPS_TX_PA_POWER_PUP_MSK 0x80000 #define PHY_RFIP_TXOFFPS_TX_PA_POWER_PUP_EN 0x80000 #define PHY_RFIP_TXSUPPLIEDPS_TX_PA_POWER_PUP_POS 19 #define PHY_RFIP_TXSUPPLIEDPS_TX_PA_POWER_PUP_LEN 1 #define PHY_RFIP_TXSUPPLIEDPS_TX_PA_POWER_PUP_MSK 0x80000 #define PHY_RFIP_TXSUPPLIEDPS_TX_PA_POWER_PUP_EN 0x80000 #define PHY_RFIP_TXBIASPS_TX_PA_POWER_PUP_POS 19 #define PHY_RFIP_TXBIASPS_TX_PA_POWER_PUP_LEN 1 #define PHY_RFIP_TXBIASPS_TX_PA_POWER_PUP_MSK 0x80000 #define PHY_RFIP_TXBIASPS_TX_PA_POWER_PUP_EN 0x80000 #define PHY_RFIP_TXANAPS_TX_PA_POWER_PUP_POS 19 #define PHY_RFIP_TXANAPS_TX_PA_POWER_PUP_LEN 1 #define PHY_RFIP_TXANAPS_TX_PA_POWER_PUP_MSK 0x80000 #define PHY_RFIP_TXANAPS_TX_PA_POWER_PUP_EN 0x80000 #define PHY_RFIP_TXLQPS_TX_PA_POWER_PUP_POS 19 #define PHY_RFIP_TXLQPS_TX_PA_POWER_PUP_LEN 1 #define PHY_RFIP_TXLQPS_TX_PA_POWER_PUP_MSK 0x80000 #define PHY_RFIP_TXLQPS_TX_PA_POWER_PUP_EN 0x80000 #define PHY_RFIP_TXONPS_TX_PA_POWER_PUP_POS 19 #define PHY_RFIP_TXONPS_TX_PA_POWER_PUP_LEN 1 #define PHY_RFIP_TXONPS_TX_PA_POWER_PUP_MSK 0x80000 #define PHY_RFIP_TXONPS_TX_PA_POWER_PUP_EN 0x80000 #define PHY_RFIP_TXRFOFFPS_TX_PA_POWER_PUP_POS 19 #define PHY_RFIP_TXRFOFFPS_TX_PA_POWER_PUP_LEN 1 #define PHY_RFIP_TXRFOFFPS_TX_PA_POWER_PUP_MSK 0x80000 #define PHY_RFIP_TXRFOFFPS_TX_PA_POWER_PUP_EN 0x80000 #define PHY_RFIP_TXOFFPS_TX_PA_VBATSENS_PUP_POS 20 #define PHY_RFIP_TXOFFPS_TX_PA_VBATSENS_PUP_LEN 1 #define PHY_RFIP_TXOFFPS_TX_PA_VBATSENS_PUP_MSK 0x100000 #define PHY_RFIP_TXOFFPS_TX_PA_VBATSENS_PUP_EN 0x100000 #define PHY_RFIP_TXSUPPLIEDPS_TX_PA_VBATSENS_PUP_POS 20 #define PHY_RFIP_TXSUPPLIEDPS_TX_PA_VBATSENS_PUP_LEN 1 #define PHY_RFIP_TXSUPPLIEDPS_TX_PA_VBATSENS_PUP_MSK 0x100000 #define PHY_RFIP_TXSUPPLIEDPS_TX_PA_VBATSENS_PUP_EN 0x100000 #define PHY_RFIP_TXBIASPS_TX_PA_VBATSENS_PUP_POS 20 #define PHY_RFIP_TXBIASPS_TX_PA_VBATSENS_PUP_LEN 1 #define PHY_RFIP_TXBIASPS_TX_PA_VBATSENS_PUP_MSK 0x100000 #define PHY_RFIP_TXBIASPS_TX_PA_VBATSENS_PUP_EN 0x100000 #define PHY_RFIP_TXANAPS_TX_PA_VBATSENS_PUP_POS 20 #define PHY_RFIP_TXANAPS_TX_PA_VBATSENS_PUP_LEN 1 #define PHY_RFIP_TXANAPS_TX_PA_VBATSENS_PUP_MSK 0x100000 #define PHY_RFIP_TXANAPS_TX_PA_VBATSENS_PUP_EN 0x100000 #define PHY_RFIP_TXLQPS_TX_PA_VBATSENS_PUP_POS 20 #define PHY_RFIP_TXLQPS_TX_PA_VBATSENS_PUP_LEN 1 #define PHY_RFIP_TXLQPS_TX_PA_VBATSENS_PUP_MSK 0x100000 #define PHY_RFIP_TXLQPS_TX_PA_VBATSENS_PUP_EN 0x100000 #define PHY_RFIP_TXONPS_TX_PA_VBATSENS_PUP_POS 20 #define PHY_RFIP_TXONPS_TX_PA_VBATSENS_PUP_LEN 1 #define PHY_RFIP_TXONPS_TX_PA_VBATSENS_PUP_MSK 0x100000 #define PHY_RFIP_TXONPS_TX_PA_VBATSENS_PUP_EN 0x100000 #define PHY_RFIP_TXRFOFFPS_TX_PA_VBATSENS_PUP_POS 20 #define PHY_RFIP_TXRFOFFPS_TX_PA_VBATSENS_PUP_LEN 1 #define PHY_RFIP_TXRFOFFPS_TX_PA_VBATSENS_PUP_MSK 0x100000 #define PHY_RFIP_TXRFOFFPS_TX_PA_VBATSENS_PUP_EN 0x100000 #define PHY_RFIP_TXOFFPS_TX_PA_POWER_BIAS_PUP_POS 21 #define PHY_RFIP_TXOFFPS_TX_PA_POWER_BIAS_PUP_LEN 1 #define PHY_RFIP_TXOFFPS_TX_PA_POWER_BIAS_PUP_MSK 0x200000 #define PHY_RFIP_TXOFFPS_TX_PA_POWER_BIAS_PUP_EN 0x200000 #define PHY_RFIP_TXSUPPLIEDPS_TX_PA_POWER_BIAS_PUP_POS 21 #define PHY_RFIP_TXSUPPLIEDPS_TX_PA_POWER_BIAS_PUP_LEN 1 #define PHY_RFIP_TXSUPPLIEDPS_TX_PA_POWER_BIAS_PUP_MSK 0x200000 #define PHY_RFIP_TXSUPPLIEDPS_TX_PA_POWER_BIAS_PUP_EN 0x200000 #define PHY_RFIP_TXBIASPS_TX_PA_POWER_BIAS_PUP_POS 21 #define PHY_RFIP_TXBIASPS_TX_PA_POWER_BIAS_PUP_LEN 1 #define PHY_RFIP_TXBIASPS_TX_PA_POWER_BIAS_PUP_MSK 0x200000 #define PHY_RFIP_TXBIASPS_TX_PA_POWER_BIAS_PUP_EN 0x200000 #define PHY_RFIP_TXANAPS_TX_PA_POWER_BIAS_PUP_POS 21 #define PHY_RFIP_TXANAPS_TX_PA_POWER_BIAS_PUP_LEN 1 #define PHY_RFIP_TXANAPS_TX_PA_POWER_BIAS_PUP_MSK 0x200000 #define PHY_RFIP_TXANAPS_TX_PA_POWER_BIAS_PUP_EN 0x200000 #define PHY_RFIP_TXLQPS_TX_PA_POWER_BIAS_PUP_POS 21 #define PHY_RFIP_TXLQPS_TX_PA_POWER_BIAS_PUP_LEN 1 #define PHY_RFIP_TXLQPS_TX_PA_POWER_BIAS_PUP_MSK 0x200000 #define PHY_RFIP_TXLQPS_TX_PA_POWER_BIAS_PUP_EN 0x200000 #define PHY_RFIP_TXONPS_TX_PA_POWER_BIAS_PUP_POS 21 #define PHY_RFIP_TXONPS_TX_PA_POWER_BIAS_PUP_LEN 1 #define PHY_RFIP_TXONPS_TX_PA_POWER_BIAS_PUP_MSK 0x200000 #define PHY_RFIP_TXONPS_TX_PA_POWER_BIAS_PUP_EN 0x200000 #define PHY_RFIP_TXRFOFFPS_TX_PA_POWER_BIAS_PUP_POS 21 #define PHY_RFIP_TXRFOFFPS_TX_PA_POWER_BIAS_PUP_LEN 1 #define PHY_RFIP_TXRFOFFPS_TX_PA_POWER_BIAS_PUP_MSK 0x200000 #define PHY_RFIP_TXRFOFFPS_TX_PA_POWER_BIAS_PUP_EN 0x200000 #define PHY_RFIP_TXOFFPS_TX_TXDD_FIFO_EN_POS 22 #define PHY_RFIP_TXOFFPS_TX_TXDD_FIFO_EN_LEN 1 #define PHY_RFIP_TXOFFPS_TX_TXDD_FIFO_EN_MSK 0x400000 #define PHY_RFIP_TXOFFPS_TX_TXDD_FIFO_EN_EN 0x400000 #define PHY_RFIP_TXSUPPLIEDPS_TX_TXDD_FIFO_EN_POS 22 #define PHY_RFIP_TXSUPPLIEDPS_TX_TXDD_FIFO_EN_LEN 1 #define PHY_RFIP_TXSUPPLIEDPS_TX_TXDD_FIFO_EN_MSK 0x400000 #define PHY_RFIP_TXSUPPLIEDPS_TX_TXDD_FIFO_EN_EN 0x400000 #define PHY_RFIP_TXBIASPS_TX_TXDD_FIFO_EN_POS 22 #define PHY_RFIP_TXBIASPS_TX_TXDD_FIFO_EN_LEN 1 #define PHY_RFIP_TXBIASPS_TX_TXDD_FIFO_EN_MSK 0x400000 #define PHY_RFIP_TXBIASPS_TX_TXDD_FIFO_EN_EN 0x400000 #define PHY_RFIP_TXANAPS_TX_TXDD_FIFO_EN_POS 22 #define PHY_RFIP_TXANAPS_TX_TXDD_FIFO_EN_LEN 1 #define PHY_RFIP_TXANAPS_TX_TXDD_FIFO_EN_MSK 0x400000 #define PHY_RFIP_TXANAPS_TX_TXDD_FIFO_EN_EN 0x400000 #define PHY_RFIP_TXLQPS_TX_TXDD_FIFO_EN_POS 22 #define PHY_RFIP_TXLQPS_TX_TXDD_FIFO_EN_LEN 1 #define PHY_RFIP_TXLQPS_TX_TXDD_FIFO_EN_MSK 0x400000 #define PHY_RFIP_TXLQPS_TX_TXDD_FIFO_EN_EN 0x400000 #define PHY_RFIP_TXONPS_TX_TXDD_FIFO_EN_POS 22 #define PHY_RFIP_TXONPS_TX_TXDD_FIFO_EN_LEN 1 #define PHY_RFIP_TXONPS_TX_TXDD_FIFO_EN_MSK 0x400000 #define PHY_RFIP_TXONPS_TX_TXDD_FIFO_EN_EN 0x400000 #define PHY_RFIP_TXRFOFFPS_TX_TXDD_FIFO_EN_POS 22 #define PHY_RFIP_TXRFOFFPS_TX_TXDD_FIFO_EN_LEN 1 #define PHY_RFIP_TXRFOFFPS_TX_TXDD_FIFO_EN_MSK 0x400000 #define PHY_RFIP_TXRFOFFPS_TX_TXDD_FIFO_EN_EN 0x400000 #define PHY_RFIP_TXOFFPS_TX_PA_POWER_EN_POS 23 #define PHY_RFIP_TXOFFPS_TX_PA_POWER_EN_LEN 1 #define PHY_RFIP_TXOFFPS_TX_PA_POWER_EN_MSK 0x800000 #define PHY_RFIP_TXOFFPS_TX_PA_POWER_EN_EN 0x800000 #define PHY_RFIP_TXSUPPLIEDPS_TX_PA_POWER_EN_POS 23 #define PHY_RFIP_TXSUPPLIEDPS_TX_PA_POWER_EN_LEN 1 #define PHY_RFIP_TXSUPPLIEDPS_TX_PA_POWER_EN_MSK 0x800000 #define PHY_RFIP_TXSUPPLIEDPS_TX_PA_POWER_EN_EN 0x800000 #define PHY_RFIP_TXBIASPS_TX_PA_POWER_EN_POS 23 #define PHY_RFIP_TXBIASPS_TX_PA_POWER_EN_LEN 1 #define PHY_RFIP_TXBIASPS_TX_PA_POWER_EN_MSK 0x800000 #define PHY_RFIP_TXBIASPS_TX_PA_POWER_EN_EN 0x800000 #define PHY_RFIP_TXANAPS_TX_PA_POWER_EN_POS 23 #define PHY_RFIP_TXANAPS_TX_PA_POWER_EN_LEN 1 #define PHY_RFIP_TXANAPS_TX_PA_POWER_EN_MSK 0x800000 #define PHY_RFIP_TXANAPS_TX_PA_POWER_EN_EN 0x800000 #define PHY_RFIP_TXLQPS_TX_PA_POWER_EN_POS 23 #define PHY_RFIP_TXLQPS_TX_PA_POWER_EN_LEN 1 #define PHY_RFIP_TXLQPS_TX_PA_POWER_EN_MSK 0x800000 #define PHY_RFIP_TXLQPS_TX_PA_POWER_EN_EN 0x800000 #define PHY_RFIP_TXONPS_TX_PA_POWER_EN_POS 23 #define PHY_RFIP_TXONPS_TX_PA_POWER_EN_LEN 1 #define PHY_RFIP_TXONPS_TX_PA_POWER_EN_MSK 0x800000 #define PHY_RFIP_TXONPS_TX_PA_POWER_EN_EN 0x800000 #define PHY_RFIP_TXRFOFFPS_TX_PA_POWER_EN_POS 23 #define PHY_RFIP_TXRFOFFPS_TX_PA_POWER_EN_LEN 1 #define PHY_RFIP_TXRFOFFPS_TX_PA_POWER_EN_MSK 0x800000 #define PHY_RFIP_TXRFOFFPS_TX_PA_POWER_EN_EN 0x800000 #define PHY_RFIP_TXOFFPS_TX_LDO_REF_PUP_POS 24 #define PHY_RFIP_TXOFFPS_TX_LDO_REF_PUP_LEN 1 #define PHY_RFIP_TXOFFPS_TX_LDO_REF_PUP_MSK 0x1000000 #define PHY_RFIP_TXOFFPS_TX_LDO_REF_PUP_EN 0x1000000 #define PHY_RFIP_TXSUPPLIEDPS_LDO_LQB_POS 24 #define PHY_RFIP_TXSUPPLIEDPS_LDO_LQB_LEN 1 #define PHY_RFIP_TXSUPPLIEDPS_LDO_LQB_MSK 0x1000000 #define PHY_RFIP_TXSUPPLIEDPS_LDO_LQB_EN 0x1000000 #define PHY_RFIP_TXBIASPS_TX_LDO_REF_PUP_POS 24 #define PHY_RFIP_TXBIASPS_TX_LDO_REF_PUP_LEN 1 #define PHY_RFIP_TXBIASPS_TX_LDO_REF_PUP_MSK 0x1000000 #define PHY_RFIP_TXBIASPS_TX_LDO_REF_PUP_EN 0x1000000 #define PHY_RFIP_TXANAPS_TX_LDO_REF_PUP_POS 24 #define PHY_RFIP_TXANAPS_TX_LDO_REF_PUP_LEN 1 #define PHY_RFIP_TXANAPS_TX_LDO_REF_PUP_MSK 0x1000000 #define PHY_RFIP_TXANAPS_TX_LDO_REF_PUP_EN 0x1000000 #define PHY_RFIP_TXLQPS_TX_LDO_REF_PUP_POS 24 #define PHY_RFIP_TXLQPS_TX_LDO_REF_PUP_LEN 1 #define PHY_RFIP_TXLQPS_TX_LDO_REF_PUP_MSK 0x1000000 #define PHY_RFIP_TXLQPS_TX_LDO_REF_PUP_EN 0x1000000 #define PHY_RFIP_TXONPS_TX_LDO_REF_PUP_POS 24 #define PHY_RFIP_TXONPS_TX_LDO_REF_PUP_LEN 1 #define PHY_RFIP_TXONPS_TX_LDO_REF_PUP_MSK 0x1000000 #define PHY_RFIP_TXONPS_TX_LDO_REF_PUP_EN 0x1000000 #define PHY_RFIP_TXRFOFFPS_TX_LDO_REF_PUP_POS 24 #define PHY_RFIP_TXRFOFFPS_TX_LDO_REF_PUP_LE 1 #define PHY_RFIP_TXRFOFFPS_TX_LDO_REF_PUP_MSK 0x1000000 #define PHY_RFIP_TXRFOFFPS_TX_LDO_REF_PUP_EN 0x1000000 #define PHY_RFIP_TXOFFPS_TX_LDO_PUP_POS 25 #define PHY_RFIP_TXOFFPS_TX_LDO_PUP_LEN 1 #define PHY_RFIP_TXOFFPS_TX_LDO_PUP_MSK 0x2000000 #define PHY_RFIP_TXOFFPS_TX_LDO_PUP_EN 0x2000000 #define PHY_RFIP_TXSUPPLIEDPS_LDO_PUP_POS 25 #define PHY_RFIP_TXSUPPLIEDPS_LDO_PUP_LEN 1 #define PHY_RFIP_TXSUPPLIEDPS_LDO_PUP_MSK 0x2000000 #define PHY_RFIP_TXSUPPLIEDPS_LDO_PUP_EN 0x2000000 #define PHY_RFIP_TXBIASPS_TX_LDO_PUP_POS 25 #define PHY_RFIP_TXBIASPS_TX_LDO_PUP_LEN 1 #define PHY_RFIP_TXBIASPS_TX_LDO_PUP_MSK 0x2000000 #define PHY_RFIP_TXBIASPS_TX_LDO_PUP_EN 0x2000000 #define PHY_RFIP_TXANAPS_TX_LDO_PUP_POS 25 #define PHY_RFIP_TXANAPS_TX_LDO_PUP_LEN 1 #define PHY_RFIP_TXANAPS_TX_LDO_PUP_MSK 0x2000000 #define PHY_RFIP_TXANAPS_TX_LDO_PUP_EN 0x2000000 #define PHY_RFIP_TXLQPS_TX_LDO_PUP_POS 25 #define PHY_RFIP_TXLQPS_TX_LDO_PUP_LEN 1 #define PHY_RFIP_TXLQPS_TX_LDO_PUP_MSK 0x2000000 #define PHY_RFIP_TXLQPS_TX_LDO_PUP_EN 0x2000000 #define PHY_RFIP_TXONPS_TX_LDO_PUP_POS 25 #define PHY_RFIP_TXONPS_TX_LDO_PUP_LEN 1 #define PHY_RFIP_TXONPS_TX_LDO_PUP_MSK 0x2000000 #define PHY_RFIP_TXONPS_TX_LDO_PUP_EN 0x2000000 #define PHY_RFIP_TXRFOFFPS_TX_LDO_PUP_POS 25 #define PHY_RFIP_TXRFOFFPS_TX_LDO_PUP_LE 1 #define PHY_RFIP_TXRFOFFPS_TX_LDO_PUP_MSK 0x2000000 #define PHY_RFIP_TXRFOFFPS_TX_LDO_PUP_EN 0x2000000 #define PHY_RFIP_TXOFFPS_TX_LDO_LQB_POS 26 #define PHY_RFIP_TXOFFPS_TX_LDO_LQB_LEN 1 #define PHY_RFIP_TXOFFPS_TX_LDO_LQB_MSK 0x4000000 #define PHY_RFIP_TXOFFPS_TX_LDO_LQB_EN 0x4000000 #define PHY_RFIP_TXSUPPLIEDPS_LDO_REF_PUP_POS 26 #define PHY_RFIP_TXSUPPLIEDPS_LDO_REF_PUP_LEN 1 #define PHY_RFIP_TXSUPPLIEDPS_LDO_REF_PUP_MSK 0x4000000 #define PHY_RFIP_TXSUPPLIEDPS_LDO_REF_PUP_EN 0x4000000 #define PHY_RFIP_TXBIASPS_TX_LDO_LQB_POS 26 #define PHY_RFIP_TXBIASPS_TX_LDO_LQB_LEN 1 #define PHY_RFIP_TXBIASPS_TX_LDO_LQB_MSK 0x4000000 #define PHY_RFIP_TXBIASPS_TX_LDO_LQB_EN 0x4000000 #define PHY_RFIP_TXANAPS_TX_LDO_LQB_POS 26 #define PHY_RFIP_TXANAPS_TX_LDO_LQB_LEN 1 #define PHY_RFIP_TXANAPS_TX_LDO_LQB_MSK 0x4000000 #define PHY_RFIP_TXANAPS_TX_LDO_LQB_EN 0x4000000 #define PHY_RFIP_TXLQPS_TX_LDO_LQB_POS 26 #define PHY_RFIP_TXLQPS_TX_LDO_LQB_LEN 1 #define PHY_RFIP_TXLQPS_TX_LDO_LQB_MSK 0x4000000 #define PHY_RFIP_TXLQPS_TX_LDO_LQB_EN 0x4000000 #define PHY_RFIP_TXONPS_TX_LDO_LQB_POS 26 #define PHY_RFIP_TXONPS_TX_LDO_LQB_LEN 1 #define PHY_RFIP_TXONPS_TX_LDO_LQB_MSK 0x4000000 #define PHY_RFIP_TXONPS_TX_LDO_LQB_EN 0x4000000 #define PHY_RFIP_TXRFOFFPS_TX_LDO_LQB_POS 26 #define PHY_RFIP_TXRFOFFPS_TX_LDO_LQB_LE 1 #define PHY_RFIP_TXRFOFFPS_TX_LDO_LQB_MSK 0x4000000 #define PHY_RFIP_TXRFOFFPS_TX_LDO_LQB_EN 0x4000000 #define PHY_RFIP_TXOFFPS_TX_IPTAT_PUP_POS 27 #define PHY_RFIP_TXOFFPS_TX_IPTAT_PUP_LEN 1 #define PHY_RFIP_TXOFFPS_TX_IPTAT_PUP_MSK 0x8000000 #define PHY_RFIP_TXOFFPS_TX_IPTAT_PUP_EN 0x8000000 #define PHY_RFIP_TXSUPPLIEDPS_IPTAT_PUP_POS 27 #define PHY_RFIP_TXSUPPLIEDPS_IPTAT_PUP_LEN 1 #define PHY_RFIP_TXSUPPLIEDPS_IPTAT_PUP_MSK 0x8000000 #define PHY_RFIP_TXSUPPLIEDPS_IPTAT_PUP_EN 0x8000000 #define PHY_RFIP_TXBIASPS_TX_IPTAT_PUP_POS 27 #define PHY_RFIP_TXBIASPS_TX_IPTAT_PUP_LEN 1 #define PHY_RFIP_TXBIASPS_TX_IPTAT_PUP_MSK 0x8000000 #define PHY_RFIP_TXBIASPS_TX_IPTAT_PUP_EN 0x8000000 #define PHY_RFIP_TXANAPS_TX_IPTAT_PUP_POS 27 #define PHY_RFIP_TXANAPS_TX_IPTAT_PUP_LEN 1 #define PHY_RFIP_TXANAPS_TX_IPTAT_PUP_MSK 0x8000000 #define PHY_RFIP_TXANAPS_TX_IPTAT_PUP_EN 0x8000000 #define PHY_RFIP_TXLQPS_TX_IPTAT_PUP_POS 27 #define PHY_RFIP_TXLQPS_TX_IPTAT_PUP_LEN 1 #define PHY_RFIP_TXLQPS_TX_IPTAT_PUP_MSK 0x8000000 #define PHY_RFIP_TXLQPS_TX_IPTAT_PUP_EN 0x8000000 #define PHY_RFIP_TXONPS_TX_IPTAT_PUP_POS 27 #define PHY_RFIP_TXONPS_TX_IPTAT_PUP_LEN 1 #define PHY_RFIP_TXONPS_TX_IPTAT_PUP_MSK 0x8000000 #define PHY_RFIP_TXONPS_TX_IPTAT_PUP_EN 0x8000000 #define PHY_RFIP_TXRFOFFPS_TX_IPTAT_PUP_POS 27 #define PHY_RFIP_TXRFOFFPS_TX_IPTAT_PUP_LE 1 #define PHY_RFIP_TXRFOFFPS_TX_IPTAT_PUP_MSK 0x8000000 #define PHY_RFIP_TXRFOFFPS_TX_IPTAT_PUP_EN 0x8000000 // RSVD #define PHY_RFIP_TXOFFPS_TX_RSVD_PS_POS 28 #define PHY_RFIP_TXOFFPS_TX_RSVD_PS_LEN 4 #define PHY_RFIP_TXOFFPS_TX_RSVD_PS_MSK 0xf0000000 #define PHY_RFIP_TXSUPPLIEDPS_TX_RSVD_PS_POS 28 #define PHY_RFIP_TXSUPPLIEDPS_TX_RSVD_PS_LEN 4 #define PHY_RFIP_TXSUPPLIEDPS_TX_RSVD_PS_MSK 0xf0000000 #define PHY_RFIP_TXBIASPS_TX_RSVD_PS_POS 28 #define PHY_RFIP_TXBIASPS_TX_RSVD_PS_LEN 4 #define PHY_RFIP_TXBIASPS_TX_RSVD_PS_MSK 0xf0000000 #define PHY_RFIP_TXANAPS_TX_RSVD_PS_POS 28 #define PHY_RFIP_TXANAPS_TX_RSVD_PS_LEN 4 #define PHY_RFIP_TXANAPS_TX_RSVD_PS_MSK 0xf0000000 #define PHY_RFIP_TXLQPS_TX_RSVD_PS_POS 28 #define PHY_RFIP_TXLQPS_TX_RSVD_PS_LEN 4 #define PHY_RFIP_TXLQPS_TX_RSVD_PS_MSK 0xf0000000 #define PHY_RFIP_TXONPS_TX_RSVD_PS_POS 28 #define PHY_RFIP_TXONPS_TX_RSVD_PS_LEN 4 #define PHY_RFIP_TXONPS_TX_RSVD_PS_MSK 0xf0000000 #define PHY_RFIP_TXRFOFFPS_TX_RSVD_PS_POS 28 #define PHY_RFIP_TXRFOFFPS_TX_RSVD_PS_LEN 4 #define PHY_RFIP_TXRFOFFPS_TX_RSVD_PS_MSK 0xf0000000 #define PHY_RFIP_TXLQPS_CONFIG_LOW_BAND_RF 0x007CAEF2 #define PHY_RFIP_TXONPS_CONFIG_LOW_BAND_RF 0x00FCAEF2 #define PHY_RFIP_TXRFOFFPS_CONFIG_LOW_BAND_RF 0x006CA8F2 #define PHY_RFIP_TXOFFPS_CONFIG_HIGH_BAND_RF 0x00005000 #define PHY_RFIP_PS_CONFIG_LOW_BAND_IQCAL_LB_RESET 0x0040B872 #define PHY_RFIP_TXSUPPLIEDPS_CONFIG_HIGH_BAND_RF 0x00005220 #define PHY_RFIP_PS_CONFIG_LOW_BAND_IQCAL_LB_ACTIVE 0x0040A872 #define PHY_RFIP_PS_CONFIG_HIGH_BAND_IQCAL_HB_RESET 0x00407872 #define PHY_RFIP_PS_CONFIG_HIGH_BAND_IQCAL_HB_ACTIVE 0x00406872 #define PHY_RFIP_PS_CONFIG_HIGH_BAND_GPADC_BAT_SENSOR 0x00000200 #define PHY_RFIP_PS_CONFIG_HIGH_BAND_DAC_TEST__DIG_RESET 0x00403012 #define PHY_RFIP_PS_CONFIG_HIGH_BAND_TX_LB_FORCE_STATE_RST1 0x00FCBEF2 #define PHY_RFIP_PS_CONFIG_HIGH_BAND_TX_LB_FORCE_STATE_RST0 0x00FCAEF2 #define PHY_RFIP_PS_CONFIG_HIGH_BAND_TX_HB_FORCE_STATE_RST1 0x00407AF2 #define PHY_RFIP_TXOFFPS_CONFIG_LOW_BAND_RF 0x00009000 #define PHY_RFIP_PS_CONFIG_HIGH_BAND_TX_HB_FORCE_STATE_RST0 0x00406AF2 #define PHY_RFIP_TXSUPPLIEDPS_CONFIG_LOW_BAND_RF 0x00001220 #define PHY_RFIP_TXBIASPS_CONFIG_LOW_BAND_RF 0x002CAA72 #define PHY_RFIP_TXANAPS_CONFIG_LOW_BAND_RF 0x007CAEF2 #define PHY_RFIP_TXBIASPS_CONFIG_HIGH_BAND_RF 0x00006A70 #define PHY_RFIP_TXANAPS_CONFIG_HIGH_BAND_RF 0x00406A72 #define PHY_RFIP_TXLQPS_CONFIG_HIGH_BAND_RF 0x00406AF2 #define PHY_RFIP_TXONPS_CONFIG_HIGH_BAND_RF 0x00406AF2 #define PHY_RFIP_PS_CONFIG_HIGH_BAND_DAC_TEST_ACTIVE_MODE 0x00402012 #define PHY_RFIP_TXRFOFFPS_CONFIG_HIGH_BAND_RF 0x00406872 #define PHY_RFIP_PS_CONFIG_HIGH_BAND_ABB_TEST_LB_MODE 0x00ECB8F2 #define PHY_RFIP_PS_CONFIG_HIGH_BAND_ABB_TEST_HB_MODE 0x004078F2 #define PHY_RFIP_PS_CONFIG_HIGH_BAND_LDO_TEST_ENABLED 0x00000000 #define PHY_RFIP_PS_CONFIG_HIGH_BAND_GPADC_BAT_SENSOR15 0x00300200 /* This is automatically generated description for register: TX_LDO_POWER_STATE */ #define PHY_RFIP_TXLDOOFFPS_UNUSED_POS 0 #define PHY_RFIP_TXLDOOFFPS_UNUSED_LEN 1 #define PHY_RFIP_TXLDOOFFPS_UNUSED_MSK 0x1 #define PHY_RFIP_TXLDOOFFPS_UNUSED_EN 0x1 #define PHY_RFIP_TXLDOSUPPLIEDPS_UNUSED_POS 0 #define PHY_RFIP_TXLDOSUPPLIEDPS_UNUSED_LEN 1 #define PHY_RFIP_TXLDOSUPPLIEDPS_UNUSED_MSK 0x1 #define PHY_RFIP_TXLDOSUPPLIEDPS_UNUSED_EN 0x1 #define PHY_RFIP_TXLDOBIASPS_UNUSED_POS 0 #define PHY_RFIP_TXLDOBIASPS_UNUSED_LEN 1 #define PHY_RFIP_TXLDOBIASPS_UNUSED_MSK 0x1 #define PHY_RFIP_TXLDOBIASPS_UNUSED_EN 0x1 #define PHY_RFIP_TXLDOANAPS_UNUSED_POS 0 #define PHY_RFIP_TXLDOANAPS_UNUSED_LEN 1 #define PHY_RFIP_TXLDOANAPS_UNUSED_MSK 0x1 #define PHY_RFIP_TXLDOANAPS_UNUSED_EN 0x1 #define PHY_RFIP_TXLDOLQPS_UNUSED_POS 0 #define PHY_RFIP_TXLDOLQPS_UNUSED_LEN 1 #define PHY_RFIP_TXLDOLQPS_UNUSED_MSK 0x1 #define PHY_RFIP_TXLDOLQPS_UNUSED_EN 0x1 #define PHY_RFIP_TXLDOONPS_UNUSED_POS 0 #define PHY_RFIP_TXLDOONPS_UNUSED_LEN 1 #define PHY_RFIP_TXLDOONPS_UNUSED_MSK 0x1 #define PHY_RFIP_TXLDOONPS_UNUSED_EN 0x1 #define PHY_RFIP_TXLDORFOFFPS_UNUSED_POS 0 #define PHY_RFIP_TXLDORFOFFPS_UNUSED_LEN 1 #define PHY_RFIP_TXLDORFOFFPS_UNUSED_MSK 0x1 #define PHY_RFIP_TXLDORFOFFPS_UNUSED_EN 0x1 #define PHY_RFIP_TXLDOOFFPS_TX_LDOABB_REF_PUP_POS 1 #define PHY_RFIP_TXLDOOFFPS_TX_LDOABB_REF_PUP_LEN 1 #define PHY_RFIP_TXLDOOFFPS_TX_LDOABB_REF_PUP_MSK 0x2 #define PHY_RFIP_TXLDOOFFPS_TX_LDOABB_REF_PUP_EN 0x2 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LDOABB_REF_PUP_POS 1 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LDOABB_REF_PUP_LEN 1 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LDOABB_REF_PUP_MSK 0x2 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LDOABB_REF_PUP_EN 0x2 #define PHY_RFIP_TXLDOBIASPS_TX_LDOABB_REF_PUP_POS 1 #define PHY_RFIP_TXLDOBIASPS_TX_LDOABB_REF_PUP_LEN 1 #define PHY_RFIP_TXLDOBIASPS_TX_LDOABB_REF_PUP_MSK 0x2 #define PHY_RFIP_TXLDOBIASPS_TX_LDOABB_REF_PUP_EN 0x2 #define PHY_RFIP_TXLDOANAPS_TX_LDOABB_REF_PUP_POS 1 #define PHY_RFIP_TXLDOANAPS_TX_LDOABB_REF_PUP_LEN 1 #define PHY_RFIP_TXLDOANAPS_TX_LDOABB_REF_PUP_MSK 0x2 #define PHY_RFIP_TXLDOANAPS_TX_LDOABB_REF_PUP_EN 0x2 #define PHY_RFIP_TXLDOLQPS_TX_LDOABB_REF_PUP_POS 1 #define PHY_RFIP_TXLDOLQPS_TX_LDOABB_REF_PUP_LEN 1 #define PHY_RFIP_TXLDOLQPS_TX_LDOABB_REF_PUP_MSK 0x2 #define PHY_RFIP_TXLDOLQPS_TX_LDOABB_REF_PUP_EN 0x2 #define PHY_RFIP_TXLDOONPS_TX_LDOABB_REF_PUP_POS 1 #define PHY_RFIP_TXLDOONPS_TX_LDOABB_REF_PUP_LEN 1 #define PHY_RFIP_TXLDOONPS_TX_LDOABB_REF_PUP_MSK 0x2 #define PHY_RFIP_TXLDOONPS_TX_LDOABB_REF_PUP_EN 0x2 #define PHY_RFIP_TXLDORFOFFPS_TX_LDOABB_REF_PUP_POS 1 #define PHY_RFIP_TXLDORFOFFPS_TX_LDOABB_REF_PUP_LEN 1 #define PHY_RFIP_TXLDORFOFFPS_TX_LDOABB_REF_PUP_MSK 0x2 #define PHY_RFIP_TXLDORFOFFPS_TX_LDOABB_REF_PUP_EN 0x2 #define PHY_RFIP_TXLDOOFFPS_TX_RF_LDO_LB_REF_PUP_POS 2 #define PHY_RFIP_TXLDOOFFPS_TX_RF_LDO_LB_REF_PUP_LEN 1 #define PHY_RFIP_TXLDOOFFPS_TX_RF_LDO_LB_REF_PUP_MSK 0x4 #define PHY_RFIP_TXLDOOFFPS_TX_RF_LDO_LB_REF_PUP_EN 0x4 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_RF_LDO_LB_REF_PUP_POS 2 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_RF_LDO_LB_REF_PUP_LEN 1 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_RF_LDO_LB_REF_PUP_MSK 0x4 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_RF_LDO_LB_REF_PUP_EN 0x4 #define PHY_RFIP_TXLDOBIASPS_TX_RF_LDO_LB_REF_PUP_POS 2 #define PHY_RFIP_TXLDOBIASPS_TX_RF_LDO_LB_REF_PUP_LEN 1 #define PHY_RFIP_TXLDOBIASPS_TX_RF_LDO_LB_REF_PUP_MSK 0x4 #define PHY_RFIP_TXLDOBIASPS_TX_RF_LDO_LB_REF_PUP_EN 0x4 #define PHY_RFIP_TXLDOANAPS_TX_RF_LDO_LB_REF_PUP_POS 2 #define PHY_RFIP_TXLDOANAPS_TX_RF_LDO_LB_REF_PUP_LEN 1 #define PHY_RFIP_TXLDOANAPS_TX_RF_LDO_LB_REF_PUP_MSK 0x4 #define PHY_RFIP_TXLDOANAPS_TX_RF_LDO_LB_REF_PUP_EN 0x4 #define PHY_RFIP_TXLDOLQPS_TX_RF_LDO_LB_REF_PUP_POS 2 #define PHY_RFIP_TXLDOLQPS_TX_RF_LDO_LB_REF_PUP_LEN 1 #define PHY_RFIP_TXLDOLQPS_TX_RF_LDO_LB_REF_PUP_MSK 0x4 #define PHY_RFIP_TXLDOLQPS_TX_RF_LDO_LB_REF_PUP_EN 0x4 #define PHY_RFIP_TXLDOONPS_TX_RF_LDO_LB_REF_PUP_POS 2 #define PHY_RFIP_TXLDOONPS_TX_RF_LDO_LB_REF_PUP_LEN 1 #define PHY_RFIP_TXLDOONPS_TX_RF_LDO_LB_REF_PUP_MSK 0x4 #define PHY_RFIP_TXLDOONPS_TX_RF_LDO_LB_REF_PUP_EN 0x4 #define PHY_RFIP_TXLDORFOFFPS_TX_RF_LDO_LB_REF_PUP_POS 2 #define PHY_RFIP_TXLDORFOFFPS_TX_RF_LDO_LB_REF_PUP_LEN 1 #define PHY_RFIP_TXLDORFOFFPS_TX_RF_LDO_LB_REF_PUP_MSK 0x4 #define PHY_RFIP_TXLDORFOFFPS_TX_RF_LDO_LB_REF_PUP_EN 0x4 #define PHY_RFIP_TXLDOOFFPS_TX_RF_LDO_HB_REF_PUP_POS 3 #define PHY_RFIP_TXLDOOFFPS_TX_RF_LDO_HB_REF_PUP_LEN 1 #define PHY_RFIP_TXLDOOFFPS_TX_RF_LDO_HB_REF_PUP_MSK 0x8 #define PHY_RFIP_TXLDOOFFPS_TX_RF_LDO_HB_REF_PUP_EN 0x8 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_RF_LDO_HB_REF_PUP_POS 3 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_RF_LDO_HB_REF_PUP_LEN 1 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_RF_LDO_HB_REF_PUP_MSK 0x8 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_RF_LDO_HB_REF_PUP_EN 0x8 #define PHY_RFIP_TXLDOBIASPS_TX_RF_LDO_HB_REF_PUP_POS 3 #define PHY_RFIP_TXLDOBIASPS_TX_RF_LDO_HB_REF_PUP_LEN 1 #define PHY_RFIP_TXLDOBIASPS_TX_RF_LDO_HB_REF_PUP_MSK 0x8 #define PHY_RFIP_TXLDOBIASPS_TX_RF_LDO_HB_REF_PUP_EN 0x8 #define PHY_RFIP_TXLDOANAPS_TX_RF_LDO_HB_REF_PUP_POS 3 #define PHY_RFIP_TXLDOANAPS_TX_RF_LDO_HB_REF_PUP_LEN 1 #define PHY_RFIP_TXLDOANAPS_TX_RF_LDO_HB_REF_PUP_MSK 0x8 #define PHY_RFIP_TXLDOANAPS_TX_RF_LDO_HB_REF_PUP_EN 0x8 #define PHY_RFIP_TXLDOLQPS_TX_RF_LDO_HB_REF_PUP_POS 3 #define PHY_RFIP_TXLDOLQPS_TX_RF_LDO_HB_REF_PUP_LEN 1 #define PHY_RFIP_TXLDOLQPS_TX_RF_LDO_HB_REF_PUP_MSK 0x8 #define PHY_RFIP_TXLDOLQPS_TX_RF_LDO_HB_REF_PUP_EN 0x8 #define PHY_RFIP_TXLDOONPS_TX_RF_LDO_HB_REF_PUP_POS 3 #define PHY_RFIP_TXLDOONPS_TX_RF_LDO_HB_REF_PUP_LEN 1 #define PHY_RFIP_TXLDOONPS_TX_RF_LDO_HB_REF_PUP_MSK 0x8 #define PHY_RFIP_TXLDOONPS_TX_RF_LDO_HB_REF_PUP_EN 0x8 #define PHY_RFIP_TXLDORFOFFPS_TX_RF_LDO_HB_REF_PUP_POS 3 #define PHY_RFIP_TXLDORFOFFPS_TX_RF_LDO_HB_REF_PUP_LEN 1 #define PHY_RFIP_TXLDORFOFFPS_TX_RF_LDO_HB_REF_PUP_MSK 0x8 #define PHY_RFIP_TXLDORFOFFPS_TX_RF_LDO_HB_REF_PUP_EN 0x8 #define PHY_RFIP_TXLDOOFFPS_TX_ABB_LDO_PUP_POS 4 #define PHY_RFIP_TXLDOOFFPS_TX_ABB_LDO_PUP_LEN 1 #define PHY_RFIP_TXLDOOFFPS_TX_ABB_LDO_PUP_MSK 0x10 #define PHY_RFIP_TXLDOOFFPS_TX_ABB_LDO_PUP_EN 0x10 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_ABB_LDO_PUP_POS 4 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_ABB_LDO_PUP_LEN 1 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_ABB_LDO_PUP_MSK 0x10 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_ABB_LDO_PUP_EN 0x10 #define PHY_RFIP_TXLDOBIASPS_TX_ABB_LDO_PUP_POS 4 #define PHY_RFIP_TXLDOBIASPS_TX_ABB_LDO_PUP_LEN 1 #define PHY_RFIP_TXLDOBIASPS_TX_ABB_LDO_PUP_MSK 0x10 #define PHY_RFIP_TXLDOBIASPS_TX_ABB_LDO_PUP_EN 0x10 #define PHY_RFIP_TXLDOANAPS_TX_ABB_LDO_PUP_POS 4 #define PHY_RFIP_TXLDOANAPS_TX_ABB_LDO_PUP_LEN 1 #define PHY_RFIP_TXLDOANAPS_TX_ABB_LDO_PUP_MSK 0x10 #define PHY_RFIP_TXLDOANAPS_TX_ABB_LDO_PUP_EN 0x10 #define PHY_RFIP_TXLDOLQPS_TX_ABB_LDO_PUP_POS 4 #define PHY_RFIP_TXLDOLQPS_TX_ABB_LDO_PUP_LEN 1 #define PHY_RFIP_TXLDOLQPS_TX_ABB_LDO_PUP_MSK 0x10 #define PHY_RFIP_TXLDOLQPS_TX_ABB_LDO_PUP_EN 0x10 #define PHY_RFIP_TXLDOONPS_TX_ABB_LDO_PUP_POS 4 #define PHY_RFIP_TXLDOONPS_TX_ABB_LDO_PUP_LEN 1 #define PHY_RFIP_TXLDOONPS_TX_ABB_LDO_PUP_MSK 0x10 #define PHY_RFIP_TXLDOONPS_TX_ABB_LDO_PUP_EN 0x10 #define PHY_RFIP_TXLDORFOFFPS_TX_ABB_LDO_PUP_POS 4 #define PHY_RFIP_TXLDORFOFFPS_TX_ABB_LDO_PUP_LEN 1 #define PHY_RFIP_TXLDORFOFFPS_TX_ABB_LDO_PUP_MSK 0x10 #define PHY_RFIP_TXLDORFOFFPS_TX_ABB_LDO_PUP_EN 0x10 #define PHY_RFIP_TXLDOOFFPS_TX_ABB_LDO_LQB_POS 5 #define PHY_RFIP_TXLDOOFFPS_TX_ABB_LDO_LQB_LEN 1 #define PHY_RFIP_TXLDOOFFPS_TX_ABB_LDO_LQB_MSK 0x20 #define PHY_RFIP_TXLDOOFFPS_TX_ABB_LDO_LQB_EN 0x20 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_ABB_LDO_LQB_POS 5 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_ABB_LDO_LQB_LEN 1 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_ABB_LDO_LQB_MSK 0x20 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_ABB_LDO_LQB_EN 0x20 #define PHY_RFIP_TXLDOBIASPS_TX_ABB_LDO_LQB_POS 5 #define PHY_RFIP_TXLDOBIASPS_TX_ABB_LDO_LQB_LEN 1 #define PHY_RFIP_TXLDOBIASPS_TX_ABB_LDO_LQB_MSK 0x20 #define PHY_RFIP_TXLDOBIASPS_TX_ABB_LDO_LQB_EN 0x20 #define PHY_RFIP_TXLDOANAPS_TX_ABB_LDO_LQB_POS 5 #define PHY_RFIP_TXLDOANAPS_TX_ABB_LDO_LQB_LEN 1 #define PHY_RFIP_TXLDOANAPS_TX_ABB_LDO_LQB_MSK 0x20 #define PHY_RFIP_TXLDOANAPS_TX_ABB_LDO_LQB_EN 0x20 #define PHY_RFIP_TXLDOLQPS_TX_ABB_LDO_LQB_POS 5 #define PHY_RFIP_TXLDOLQPS_TX_ABB_LDO_LQB_LEN 1 #define PHY_RFIP_TXLDOLQPS_TX_ABB_LDO_LQB_MSK 0x20 #define PHY_RFIP_TXLDOLQPS_TX_ABB_LDO_LQB_EN 0x20 #define PHY_RFIP_TXLDOONPS_TX_ABB_LDO_LQB_POS 5 #define PHY_RFIP_TXLDOONPS_TX_ABB_LDO_LQB_LEN 1 #define PHY_RFIP_TXLDOONPS_TX_ABB_LDO_LQB_MSK 0x20 #define PHY_RFIP_TXLDOONPS_TX_ABB_LDO_LQB_EN 0x20 #define PHY_RFIP_TXLDORFOFFPS_TX_ABB_LDO_LQB_POS 5 #define PHY_RFIP_TXLDORFOFFPS_TX_ABB_LDO_LQB_LEN 1 #define PHY_RFIP_TXLDORFOFFPS_TX_ABB_LDO_LQB_MSK 0x20 #define PHY_RFIP_TXLDORFOFFPS_TX_ABB_LDO_LQB_EN 0x20 #define PHY_RFIP_TXLDOOFFPS_TX_LO_HB_LDO_PUP_POS 6 #define PHY_RFIP_TXLDOOFFPS_TX_LO_HB_LDO_PUP_LEN 1 #define PHY_RFIP_TXLDOOFFPS_TX_LO_HB_LDO_PUP_MSK 0x40 #define PHY_RFIP_TXLDOOFFPS_TX_LO_HB_LDO_PUP_EN 0x40 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LO_HB_LDO_PUP_POS 6 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LO_HB_LDO_PUP_LEN 1 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LO_HB_LDO_PUP_MSK 0x40 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LO_HB_LDO_PUP_EN 0x40 #define PHY_RFIP_TXLDOBIASPS_TX_LO_HB_LDO_PUP_POS 6 #define PHY_RFIP_TXLDOBIASPS_TX_LO_HB_LDO_PUP_LEN 1 #define PHY_RFIP_TXLDOBIASPS_TX_LO_HB_LDO_PUP_MSK 0x40 #define PHY_RFIP_TXLDOBIASPS_TX_LO_HB_LDO_PUP_EN 0x40 #define PHY_RFIP_TXLDOANAPS_TX_LO_HB_LDO_PUP_POS 6 #define PHY_RFIP_TXLDOANAPS_TX_LO_HB_LDO_PUP_LEN 1 #define PHY_RFIP_TXLDOANAPS_TX_LO_HB_LDO_PUP_MSK 0x40 #define PHY_RFIP_TXLDOANAPS_TX_LO_HB_LDO_PUP_EN 0x40 #define PHY_RFIP_TXLDOLQPS_TX_LO_HB_LDO_PUP_POS 6 #define PHY_RFIP_TXLDOLQPS_TX_LO_HB_LDO_PUP_LEN 1 #define PHY_RFIP_TXLDOLQPS_TX_LO_HB_LDO_PUP_MSK 0x40 #define PHY_RFIP_TXLDOLQPS_TX_LO_HB_LDO_PUP_EN 0x40 #define PHY_RFIP_TXLDOONPS_TX_LO_HB_LDO_PUP_POS 6 #define PHY_RFIP_TXLDOONPS_TX_LO_HB_LDO_PUP_LEN 1 #define PHY_RFIP_TXLDOONPS_TX_LO_HB_LDO_PUP_MSK 0x40 #define PHY_RFIP_TXLDOONPS_TX_LO_HB_LDO_PUP_EN 0x40 #define PHY_RFIP_TXLDORFOFFPS_TX_LO_HB_LDO_PUP_POS 6 #define PHY_RFIP_TXLDORFOFFPS_TX_LO_HB_LDO_PUP_LEN 1 #define PHY_RFIP_TXLDORFOFFPS_TX_LO_HB_LDO_PUP_MSK 0x40 #define PHY_RFIP_TXLDORFOFFPS_TX_LO_HB_LDO_PUP_EN 0x40 #define PHY_RFIP_TXLDOOFFPS_TX_LO_HB_LDO_LQB_POS 7 #define PHY_RFIP_TXLDOOFFPS_TX_LO_HB_LDO_LQB_LEN 1 #define PHY_RFIP_TXLDOOFFPS_TX_LO_HB_LDO_LQB_MSK 0x80 #define PHY_RFIP_TXLDOOFFPS_TX_LO_HB_LDO_LQB_EN 0x80 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LO_HB_LDO_LQB_POS 7 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LO_HB_LDO_LQB_LEN 1 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LO_HB_LDO_LQB_MSK 0x80 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LO_HB_LDO_LQB_EN 0x80 #define PHY_RFIP_TXLDOBIASPS_TX_LO_HB_LDO_LQB_POS 7 #define PHY_RFIP_TXLDOBIASPS_TX_LO_HB_LDO_LQB_LEN 1 #define PHY_RFIP_TXLDOBIASPS_TX_LO_HB_LDO_LQB_MSK 0x80 #define PHY_RFIP_TXLDOBIASPS_TX_LO_HB_LDO_LQB_EN 0x80 #define PHY_RFIP_TXLDOANAPS_TX_LO_HB_LDO_LQB_POS 7 #define PHY_RFIP_TXLDOANAPS_TX_LO_HB_LDO_LQB_LEN 1 #define PHY_RFIP_TXLDOANAPS_TX_LO_HB_LDO_LQB_MSK 0x80 #define PHY_RFIP_TXLDOANAPS_TX_LO_HB_LDO_LQB_EN 0x80 #define PHY_RFIP_TXLDOLQPS_TX_LO_HB_LDO_LQB_POS 7 #define PHY_RFIP_TXLDOLQPS_TX_LO_HB_LDO_LQB_LEN 1 #define PHY_RFIP_TXLDOLQPS_TX_LO_HB_LDO_LQB_MSK 0x80 #define PHY_RFIP_TXLDOLQPS_TX_LO_HB_LDO_LQB_EN 0x80 #define PHY_RFIP_TXLDOONPS_TX_LO_HB_LDO_LQB_POS 7 #define PHY_RFIP_TXLDOONPS_TX_LO_HB_LDO_LQB_LEN 1 #define PHY_RFIP_TXLDOONPS_TX_LO_HB_LDO_LQB_MSK 0x80 #define PHY_RFIP_TXLDOONPS_TX_LO_HB_LDO_LQB_EN 0x80 #define PHY_RFIP_TXLDORFOFFPS_TX_LO_HB_LDO_LQB_POS 7 #define PHY_RFIP_TXLDORFOFFPS_TX_LO_HB_LDO_LQB_LEN 1 #define PHY_RFIP_TXLDORFOFFPS_TX_LO_HB_LDO_LQB_MSK 0x80 #define PHY_RFIP_TXLDORFOFFPS_TX_LO_HB_LDO_LQB_EN 0x80 #define PHY_RFIP_TXLDOOFFPS_TX_LO_LB_LDO_PUP_POS 8 #define PHY_RFIP_TXLDOOFFPS_TX_LO_LB_LDO_PUP_LEN 1 #define PHY_RFIP_TXLDOOFFPS_TX_LO_LB_LDO_PUP_MSK 0x100 #define PHY_RFIP_TXLDOOFFPS_TX_LO_LB_LDO_PUP_EN 0x100 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LO_LB_LDO_PUP_POS 8 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LO_LB_LDO_PUP_LEN 1 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LO_LB_LDO_PUP_MSK 0x100 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LO_LB_LDO_PUP_EN 0x100 #define PHY_RFIP_TXLDOBIASPS_TX_LO_LB_LDO_PUP_POS 8 #define PHY_RFIP_TXLDOBIASPS_TX_LO_LB_LDO_PUP_LEN 1 #define PHY_RFIP_TXLDOBIASPS_TX_LO_LB_LDO_PUP_MSK 0x100 #define PHY_RFIP_TXLDOBIASPS_TX_LO_LB_LDO_PUP_EN 0x100 #define PHY_RFIP_TXLDOANAPS_TX_LO_LB_LDO_PUP_POS 8 #define PHY_RFIP_TXLDOANAPS_TX_LO_LB_LDO_PUP_LEN 1 #define PHY_RFIP_TXLDOANAPS_TX_LO_LB_LDO_PUP_MSK 0x100 #define PHY_RFIP_TXLDOANAPS_TX_LO_LB_LDO_PUP_EN 0x100 #define PHY_RFIP_TXLDOLQPS_TX_LO_LB_LDO_PUP_POS 8 #define PHY_RFIP_TXLDOLQPS_TX_LO_LB_LDO_PUP_LEN 1 #define PHY_RFIP_TXLDOLQPS_TX_LO_LB_LDO_PUP_MSK 0x100 #define PHY_RFIP_TXLDOLQPS_TX_LO_LB_LDO_PUP_EN 0x100 #define PHY_RFIP_TXLDOONPS_TX_LO_LB_LDO_PUP_POS 8 #define PHY_RFIP_TXLDOONPS_TX_LO_LB_LDO_PUP_LEN 1 #define PHY_RFIP_TXLDOONPS_TX_LO_LB_LDO_PUP_MSK 0x100 #define PHY_RFIP_TXLDOONPS_TX_LO_LB_LDO_PUP_EN 0x100 #define PHY_RFIP_TXLDORFOFFPS_TX_LO_LB_LDO_PUP_POS 8 #define PHY_RFIP_TXLDORFOFFPS_TX_LO_LB_LDO_PUP_LEN 1 #define PHY_RFIP_TXLDORFOFFPS_TX_LO_LB_LDO_PUP_MSK 0x100 #define PHY_RFIP_TXLDORFOFFPS_TX_LO_LB_LDO_PUP_EN 0x100 #define PHY_RFIP_TXLDOOFFPS_TX_LO_LB_LDO_LQB_POS 9 #define PHY_RFIP_TXLDOOFFPS_TX_LO_LB_LDO_LQB_LEN 1 #define PHY_RFIP_TXLDOOFFPS_TX_LO_LB_LDO_LQB_MSK 0x200 #define PHY_RFIP_TXLDOOFFPS_TX_LO_LB_LDO_LQB_EN 0x200 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LO_LB_LDO_LQB_POS 9 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LO_LB_LDO_LQB_LEN 1 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LO_LB_LDO_LQB_MSK 0x200 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LO_LB_LDO_LQB_EN 0x200 #define PHY_RFIP_TXLDOBIASPS_TX_LO_LB_LDO_LQB_POS 9 #define PHY_RFIP_TXLDOBIASPS_TX_LO_LB_LDO_LQB_LEN 1 #define PHY_RFIP_TXLDOBIASPS_TX_LO_LB_LDO_LQB_MSK 0x200 #define PHY_RFIP_TXLDOBIASPS_TX_LO_LB_LDO_LQB_EN 0x200 #define PHY_RFIP_TXLDOANAPS_TX_LO_LB_LDO_LQB_POS 9 #define PHY_RFIP_TXLDOANAPS_TX_LO_LB_LDO_LQB_LEN 1 #define PHY_RFIP_TXLDOANAPS_TX_LO_LB_LDO_LQB_MSK 0x200 #define PHY_RFIP_TXLDOANAPS_TX_LO_LB_LDO_LQB_EN 0x200 #define PHY_RFIP_TXLDOLQPS_TX_LO_LB_LDO_LQB_POS 9 #define PHY_RFIP_TXLDOLQPS_TX_LO_LB_LDO_LQB_LEN 1 #define PHY_RFIP_TXLDOLQPS_TX_LO_LB_LDO_LQB_MSK 0x200 #define PHY_RFIP_TXLDOLQPS_TX_LO_LB_LDO_LQB_EN 0x200 #define PHY_RFIP_TXLDOONPS_TX_LO_LB_LDO_LQB_POS 9 #define PHY_RFIP_TXLDOONPS_TX_LO_LB_LDO_LQB_LEN 1 #define PHY_RFIP_TXLDOONPS_TX_LO_LB_LDO_LQB_MSK 0x200 #define PHY_RFIP_TXLDOONPS_TX_LO_LB_LDO_LQB_EN 0x200 #define PHY_RFIP_TXLDORFOFFPS_TX_LO_LB_LDO_LQB_POS 9 #define PHY_RFIP_TXLDORFOFFPS_TX_LO_LB_LDO_LQB_LEN 1 #define PHY_RFIP_TXLDORFOFFPS_TX_LO_LB_LDO_LQB_MSK 0x200 #define PHY_RFIP_TXLDORFOFFPS_TX_LO_LB_LDO_LQB_EN 0x200 #define PHY_RFIP_TXLDOOFFPS_TX_RF_LDO_LB_PUP_POS 10 #define PHY_RFIP_TXLDOOFFPS_TX_RF_LDO_LB_PUP_LEN 1 #define PHY_RFIP_TXLDOOFFPS_TX_RF_LDO_LB_PUP_MSK 0x400 #define PHY_RFIP_TXLDOOFFPS_TX_RF_LDO_LB_PUP_EN 0x400 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_RF_LDO_LB_PUP_POS 10 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_RF_LDO_LB_PUP_LEN 1 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_RF_LDO_LB_PUP_MSK 0x400 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_RF_LDO_LB_PUP_EN 0x400 #define PHY_RFIP_TXLDOBIASPS_TX_RF_LDO_LB_PUP_POS 10 #define PHY_RFIP_TXLDOBIASPS_TX_RF_LDO_LB_PUP_LEN 1 #define PHY_RFIP_TXLDOBIASPS_TX_RF_LDO_LB_PUP_MSK 0x400 #define PHY_RFIP_TXLDOBIASPS_TX_RF_LDO_LB_PUP_EN 0x400 #define PHY_RFIP_TXLDOANAPS_TX_RF_LDO_LB_PUP_POS 10 #define PHY_RFIP_TXLDOANAPS_TX_RF_LDO_LB_PUP_LEN 1 #define PHY_RFIP_TXLDOANAPS_TX_RF_LDO_LB_PUP_MSK 0x400 #define PHY_RFIP_TXLDOANAPS_TX_RF_LDO_LB_PUP_EN 0x400 #define PHY_RFIP_TXLDOLQPS_TX_RF_LDO_LB_PUP_POS 10 #define PHY_RFIP_TXLDOLQPS_TX_RF_LDO_LB_PUP_LEN 1 #define PHY_RFIP_TXLDOLQPS_TX_RF_LDO_LB_PUP_MSK 0x400 #define PHY_RFIP_TXLDOLQPS_TX_RF_LDO_LB_PUP_EN 0x400 #define PHY_RFIP_TXLDOONPS_TX_RF_LDO_LB_PUP_POS 10 #define PHY_RFIP_TXLDOONPS_TX_RF_LDO_LB_PUP_LEN 1 #define PHY_RFIP_TXLDOONPS_TX_RF_LDO_LB_PUP_MSK 0x400 #define PHY_RFIP_TXLDOONPS_TX_RF_LDO_LB_PUP_EN 0x400 #define PHY_RFIP_TXLDORFOFFPS_TX_RF_LDO_LB_PUP_POS 10 #define PHY_RFIP_TXLDORFOFFPS_TX_RF_LDO_LB_PUP_LEN 1 #define PHY_RFIP_TXLDORFOFFPS_TX_RF_LDO_LB_PUP_MSK 0x400 #define PHY_RFIP_TXLDORFOFFPS_TX_RF_LDO_LB_PUP_EN 0x400 #define PHY_RFIP_TXLDOOFFPS_TX_RF_LDO_LB_LQB_POS 11 #define PHY_RFIP_TXLDOOFFPS_TX_RF_LDO_LB_LQB_LEN 1 #define PHY_RFIP_TXLDOOFFPS_TX_RF_LDO_LB_LQB_MSK 0x800 #define PHY_RFIP_TXLDOOFFPS_TX_RF_LDO_LB_LQB_EN 0x800 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_RF_LDO_LB_LQB_POS 11 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_RF_LDO_LB_LQB_LEN 1 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_RF_LDO_LB_LQB_MSK 0x800 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_RF_LDO_LB_LQB_EN 0x800 #define PHY_RFIP_TXLDOBIASPS_TX_RF_LDO_LB_LQB_POS 11 #define PHY_RFIP_TXLDOBIASPS_TX_RF_LDO_LB_LQB_LEN 1 #define PHY_RFIP_TXLDOBIASPS_TX_RF_LDO_LB_LQB_MSK 0x800 #define PHY_RFIP_TXLDOBIASPS_TX_RF_LDO_LB_LQB_EN 0x800 #define PHY_RFIP_TXLDOANAPS_TX_RF_LDO_LB_LQB_POS 11 #define PHY_RFIP_TXLDOANAPS_TX_RF_LDO_LB_LQB_LEN 1 #define PHY_RFIP_TXLDOANAPS_TX_RF_LDO_LB_LQB_MSK 0x800 #define PHY_RFIP_TXLDOANAPS_TX_RF_LDO_LB_LQB_EN 0x800 #define PHY_RFIP_TXLDOLQPS_TX_RF_LDO_LB_LQB_POS 11 #define PHY_RFIP_TXLDOLQPS_TX_RF_LDO_LB_LQB_LEN 1 #define PHY_RFIP_TXLDOLQPS_TX_RF_LDO_LB_LQB_MSK 0x800 #define PHY_RFIP_TXLDOLQPS_TX_RF_LDO_LB_LQB_EN 0x800 #define PHY_RFIP_TXLDOONPS_TX_RF_LDO_LB_LQB_POS 11 #define PHY_RFIP_TXLDOONPS_TX_RF_LDO_LB_LQB_LEN 1 #define PHY_RFIP_TXLDOONPS_TX_RF_LDO_LB_LQB_MSK 0x800 #define PHY_RFIP_TXLDOONPS_TX_RF_LDO_LB_LQB_EN 0x800 #define PHY_RFIP_TXLDORFOFFPS_TX_RF_LDO_LB_LQB_POS 11 #define PHY_RFIP_TXLDORFOFFPS_TX_RF_LDO_LB_LQB_LEN 1 #define PHY_RFIP_TXLDORFOFFPS_TX_RF_LDO_LB_LQB_MSK 0x800 #define PHY_RFIP_TXLDORFOFFPS_TX_RF_LDO_LB_LQB_EN 0x800 #define PHY_RFIP_TXLDOOFFPS_TX_RF_LDO_HB_PUP_POS 12 #define PHY_RFIP_TXLDOOFFPS_TX_RF_LDO_HB_PUP_LEN 1 #define PHY_RFIP_TXLDOOFFPS_TX_RF_LDO_HB_PUP_MSK 0x1000 #define PHY_RFIP_TXLDOOFFPS_TX_RF_LDO_HB_PUP_EN 0x1000 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_RF_LDO_HB_PUP_POS 12 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_RF_LDO_HB_PUP_LEN 1 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_RF_LDO_HB_PUP_MSK 0x1000 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_RF_LDO_HB_PUP_EN 0x1000 #define PHY_RFIP_TXLDOBIASPS_TX_RF_LDO_HB_PUP_POS 12 #define PHY_RFIP_TXLDOBIASPS_TX_RF_LDO_HB_PUP_LEN 1 #define PHY_RFIP_TXLDOBIASPS_TX_RF_LDO_HB_PUP_MSK 0x1000 #define PHY_RFIP_TXLDOBIASPS_TX_RF_LDO_HB_PUP_EN 0x1000 #define PHY_RFIP_TXLDOANAPS_TX_RF_LDO_HB_PUP_POS 12 #define PHY_RFIP_TXLDOANAPS_TX_RF_LDO_HB_PUP_LEN 1 #define PHY_RFIP_TXLDOANAPS_TX_RF_LDO_HB_PUP_MSK 0x1000 #define PHY_RFIP_TXLDOANAPS_TX_RF_LDO_HB_PUP_EN 0x1000 #define PHY_RFIP_TXLDOLQPS_TX_RF_LDO_HB_PUP_POS 12 #define PHY_RFIP_TXLDOLQPS_TX_RF_LDO_HB_PUP_LEN 1 #define PHY_RFIP_TXLDOLQPS_TX_RF_LDO_HB_PUP_MSK 0x1000 #define PHY_RFIP_TXLDOLQPS_TX_RF_LDO_HB_PUP_EN 0x1000 #define PHY_RFIP_TXLDOONPS_TX_RF_LDO_HB_PUP_POS 12 #define PHY_RFIP_TXLDOONPS_TX_RF_LDO_HB_PUP_LEN 1 #define PHY_RFIP_TXLDOONPS_TX_RF_LDO_HB_PUP_MSK 0x1000 #define PHY_RFIP_TXLDOONPS_TX_RF_LDO_HB_PUP_EN 0x1000 #define PHY_RFIP_TXLDORFOFFPS_TX_RF_LDO_HB_PUP_POS 12 #define PHY_RFIP_TXLDORFOFFPS_TX_RF_LDO_HB_PUP_LEN 1 #define PHY_RFIP_TXLDORFOFFPS_TX_RF_LDO_HB_PUP_MSK 0x1000 #define PHY_RFIP_TXLDORFOFFPS_TX_RF_LDO_HB_PUP_EN 0x1000 #define PHY_RFIP_TXLDOOFFPS_TX_RF_LDO_HB_LQB_POS 13 #define PHY_RFIP_TXLDOOFFPS_TX_RF_LDO_HB_LQB_LEN 1 #define PHY_RFIP_TXLDOOFFPS_TX_RF_LDO_HB_LQB_MSK 0x2000 #define PHY_RFIP_TXLDOOFFPS_TX_RF_LDO_HB_LQB_EN 0x2000 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_RF_LDO_HB_LQB_POS 13 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_RF_LDO_HB_LQB_LEN 1 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_RF_LDO_HB_LQB_MSK 0x2000 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_RF_LDO_HB_LQB_EN 0x2000 #define PHY_RFIP_TXLDOBIASPS_TX_RF_LDO_HB_LQB_POS 13 #define PHY_RFIP_TXLDOBIASPS_TX_RF_LDO_HB_LQB_LEN 1 #define PHY_RFIP_TXLDOBIASPS_TX_RF_LDO_HB_LQB_MSK 0x2000 #define PHY_RFIP_TXLDOBIASPS_TX_RF_LDO_HB_LQB_EN 0x2000 #define PHY_RFIP_TXLDOANAPS_TX_RF_LDO_HB_LQB_POS 13 #define PHY_RFIP_TXLDOANAPS_TX_RF_LDO_HB_LQB_LEN 1 #define PHY_RFIP_TXLDOANAPS_TX_RF_LDO_HB_LQB_MSK 0x2000 #define PHY_RFIP_TXLDOANAPS_TX_RF_LDO_HB_LQB_EN 0x2000 #define PHY_RFIP_TXLDOLQPS_TX_RF_LDO_HB_LQB_POS 13 #define PHY_RFIP_TXLDOLQPS_TX_RF_LDO_HB_LQB_LEN 1 #define PHY_RFIP_TXLDOLQPS_TX_RF_LDO_HB_LQB_MSK 0x2000 #define PHY_RFIP_TXLDOLQPS_TX_RF_LDO_HB_LQB_EN 0x2000 #define PHY_RFIP_TXLDOONPS_TX_RF_LDO_HB_LQB_POS 13 #define PHY_RFIP_TXLDOONPS_TX_RF_LDO_HB_LQB_LEN 1 #define PHY_RFIP_TXLDOONPS_TX_RF_LDO_HB_LQB_MSK 0x2000 #define PHY_RFIP_TXLDOONPS_TX_RF_LDO_HB_LQB_EN 0x2000 #define PHY_RFIP_TXLDORFOFFPS_TX_RF_LDO_HB_LQB_POS 13 #define PHY_RFIP_TXLDORFOFFPS_TX_RF_LDO_HB_LQB_LEN 1 #define PHY_RFIP_TXLDORFOFFPS_TX_RF_LDO_HB_LQB_MSK 0x2000 #define PHY_RFIP_TXLDORFOFFPS_TX_RF_LDO_HB_LQB_EN 0x2000 #define PHY_RFIP_TXLDOOFFPS_TX_CTRL_BIAS_LDO_LQB_POS 14 #define PHY_RFIP_TXLDOOFFPS_TX_CTRL_BIAS_LDO_LQB_LEN 2 #define PHY_RFIP_TXLDOOFFPS_TX_CTRL_BIAS_LDO_LQB_MSK 0xc000 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_CTRL_BIAS_LDO_LQB_POS 14 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_CTRL_BIAS_LDO_LQB_LEN 2 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_CTRL_BIAS_LDO_LQB_MSK 0xc000 #define PHY_RFIP_TXLDOBIASPS_TX_CTRL_BIAS_LDO_LQB_POS 14 #define PHY_RFIP_TXLDOBIASPS_TX_CTRL_BIAS_LDO_LQB_LEN 2 #define PHY_RFIP_TXLDOBIASPS_TX_CTRL_BIAS_LDO_LQB_MSK 0xc000 #define PHY_RFIP_TXLDOANAPS_TX_CTRL_BIAS_LDO_LQB_POS 14 #define PHY_RFIP_TXLDOANAPS_TX_CTRL_BIAS_LDO_LQB_LEN 2 #define PHY_RFIP_TXLDOANAPS_TX_CTRL_BIAS_LDO_LQB_MSK 0xc000 #define PHY_RFIP_TXLDOLQPS_TX_CTRL_BIAS_LDO_LQB_POS 14 #define PHY_RFIP_TXLDOLQPS_TX_CTRL_BIAS_LDO_LQB_LEN 2 #define PHY_RFIP_TXLDOLQPS_TX_CTRL_BIAS_LDO_LQB_MSK 0xc000 #define PHY_RFIP_TXLDOONPS_TX_CTRL_BIAS_LDO_LQB_POS 14 #define PHY_RFIP_TXLDOONPS_TX_CTRL_BIAS_LDO_LQB_LEN 2 #define PHY_RFIP_TXLDOONPS_TX_CTRL_BIAS_LDO_LQB_MSK 0xc000 #define PHY_RFIP_TXLDORFOFFPS_TX_CTRL_BIAS_LDO_LQB_POS 14 #define PHY_RFIP_TXLDORFOFFPS_TX_CTRL_BIAS_LDO_LQB_LEN 2 #define PHY_RFIP_TXLDORFOFFPS_TX_CTRL_BIAS_LDO_LQB_MSK 0xc000 #define PHY_RFIP_TXLDOOFFPS_TX_LDO_HBLO_REF_PUP_POS 16 #define PHY_RFIP_TXLDOOFFPS_TX_LDO_HBLO_REF_PUP_LEN 1 #define PHY_RFIP_TXLDOOFFPS_TX_LDO_HBLO_REF_PUP_MSK 0x10000 #define PHY_RFIP_TXLDOOFFPS_TX_LDO_HBLO_REF_PUP_EN 0x10000 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LDO_HBLO_REF_PUP_POS 16 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LDO_HBLO_REF_PUP_LEN 1 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LDO_HBLO_REF_PUP_MSK 0x10000 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LDO_HBLO_REF_PUP_EN 0x10000 #define PHY_RFIP_TXLDOBIASPS_TX_LDO_HBLO_REF_PUP_POS 16 #define PHY_RFIP_TXLDOBIASPS_TX_LDO_HBLO_REF_PUP_LEN 1 #define PHY_RFIP_TXLDOBIASPS_TX_LDO_HBLO_REF_PUP_MSK 0x10000 #define PHY_RFIP_TXLDOBIASPS_TX_LDO_HBLO_REF_PUP_EN 0x10000 #define PHY_RFIP_TXLDOANAPS_TX_LDO_HBLO_REF_PUP_POS 16 #define PHY_RFIP_TXLDOANAPS_TX_LDO_HBLO_REF_PUP_LEN 1 #define PHY_RFIP_TXLDOANAPS_TX_LDO_HBLO_REF_PUP_MSK 0x10000 #define PHY_RFIP_TXLDOANAPS_TX_LDO_HBLO_REF_PUP_EN 0x10000 #define PHY_RFIP_TXLDOLQPS_TX_LDO_HBLO_REF_PUP_POS 16 #define PHY_RFIP_TXLDOLQPS_TX_LDO_HBLO_REF_PUP_LEN 1 #define PHY_RFIP_TXLDOLQPS_TX_LDO_HBLO_REF_PUP_MSK 0x10000 #define PHY_RFIP_TXLDOLQPS_TX_LDO_HBLO_REF_PUP_EN 0x10000 #define PHY_RFIP_TXLDOONPS_TX_LDO_HBLO_REF_PUP_POS 16 #define PHY_RFIP_TXLDOONPS_TX_LDO_HBLO_REF_PUP_LEN 1 #define PHY_RFIP_TXLDOONPS_TX_LDO_HBLO_REF_PUP_MSK 0x10000 #define PHY_RFIP_TXLDOONPS_TX_LDO_HBLO_REF_PUP_EN 0x10000 #define PHY_RFIP_TXLDORFOFFPS_TX_LDO_HBLO_REF_PUP_POS 16 #define PHY_RFIP_TXLDORFOFFPS_TX_LDO_HBLO_REF_PUP_LEN 1 #define PHY_RFIP_TXLDORFOFFPS_TX_LDO_HBLO_REF_PUP_MSK 0x10000 #define PHY_RFIP_TXLDORFOFFPS_TX_LDO_HBLO_REF_PUP_EN 0x10000 #define PHY_RFIP_TXLDOOFFPS_TX_LDO_LBLO_REF_PUP_POS 17 #define PHY_RFIP_TXLDOOFFPS_TX_LDO_LBLO_REF_PUP_LEN 15 #define PHY_RFIP_TXLDOOFFPS_TX_LDO_LBLO_REF_PUP_MSK 0xfffe0000 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LDO_LBLO_REF_PUP_POS 17 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LDO_LBLO_REF_PUP_LEN 15 #define PHY_RFIP_TXLDOSUPPLIEDPS_TX_LDO_LBLO_REF_PUP_MSK 0xfffe0000 #define PHY_RFIP_TXLDOBIASPS_TX_LDO_LBLO_REF_PUP_POS 17 #define PHY_RFIP_TXLDOBIASPS_TX_LDO_LBLO_REF_PUP_LEN 15 #define PHY_RFIP_TXLDOBIASPS_TX_LDO_LBLO_REF_PUP_MSK 0xfffe0000 #define PHY_RFIP_TXLDOANAPS_TX_LDO_LBLO_REF_PUP_POS 17 #define PHY_RFIP_TXLDOANAPS_TX_LDO_LBLO_REF_PUP_LEN 15 #define PHY_RFIP_TXLDOANAPS_TX_LDO_LBLO_REF_PUP_MSK 0xfffe0000 #define PHY_RFIP_TXLDOLQPS_TX_LDO_LBLO_REF_PUP_POS 17 #define PHY_RFIP_TXLDOLQPS_TX_LDO_LBLO_REF_PUP_LEN 15 #define PHY_RFIP_TXLDOLQPS_TX_LDO_LBLO_REF_PUP_MSK 0xfffe0000 #define PHY_RFIP_TXLDOONPS_TX_LDO_LBLO_REF_PUP_POS 17 #define PHY_RFIP_TXLDOONPS_TX_LDO_LBLO_REF_PUP_LEN 15 #define PHY_RFIP_TXLDOONPS_TX_LDO_LBLO_REF_PUP_MSK 0xfffe0000 #define PHY_RFIP_TXLDORFOFFPS_TX_LDO_LBLO_REF_PUP_POS 17 #define PHY_RFIP_TXLDORFOFFPS_TX_LDO_LBLO_REF_PUP_LEN 15 #define PHY_RFIP_TXLDORFOFFPS_TX_LDO_LBLO_REF_PUP_MSK 0xfffe0000 #define PHY_RFIP_TXLDOLQPS_CONFIG_LOW_BAND_RF 0x00024F36 #define PHY_RFIP_TXLDOONPS_CONFIG_LOW_BAND_RF 0x00024F36 #define PHY_RFIP_TXLDORFOFFPS_CONFIG_LOW_BAND_RF 0x00024F36 #define PHY_RFIP_TXLDOOFFPS_CONFIG_HIGH_BAND_RF 0x00010040 #define PHY_RFIP_PS_CONFIG_LOW_BAND_IQCAL_LB 0x00024F36 #define PHY_RFIP_TXLDOSUPPLIEDPS_CONFIG_HIGH_BAND_RF 0x0001105A #define PHY_RFIP_PS_CONFIG_HIGH_BAND_IQCAL_HB 0x000170FE #define PHY_RFIP_PS_CONFIG_TEST_ABBOUT 0x00000032 #define PHY_RFIP_PS_CONFIG_TEST_TX_DAC_OUT_TEST 0x00004032 #define PHY_RFIP_PS_CONFIG_TEST_ABB_TEST_LB 0x00024F36 #define PHY_RFIP_TXLDOOFFPS_CONFIG_LOW_BAND_RF 0x00020100 #define PHY_RFIP_TXLDOSUPPLIEDPS_CONFIG_LOW_BAND_RF 0x00020516 #define PHY_RFIP_TXLDOBIASPS_CONFIG_LOW_BAND_RF 0x00020516 #define PHY_RFIP_TXLDOANAPS_CONFIG_LOW_BAND_RF 0x00020516 #define PHY_RFIP_TXLDOBIASPS_CONFIG_HIGH_BAND_RF 0x0001105A #define PHY_RFIP_TXLDOANAPS_CONFIG_HIGH_BAND_RF 0x0001105A #define PHY_RFIP_TXLDOLQPS_CONFIG_HIGH_BAND_RF 0x000170FA #define PHY_RFIP_TXLDOONPS_CONFIG_HIGH_BAND_RF 0x000170FA #define PHY_RFIP_PS_CONFIG_TEST_ABB_TEST_HB 0x000170FA #define PHY_RFIP_TXLDORFOFFPS_CONFIG_HIGH_BAND_RF 0x0001407A #define PHY_RFIP_PS_CONFIG_TEST_LDO_TEST_ENABLED 0x00000000 #define PHY_RFIP_PS_CONFIG_TEST_GPADC_BAT_SENSOR 0x00004000 #define PHY_RFIP_PS_CONFIG_ATE__FULL_LDO_ON 0x0003155E /* This is automatically generated description for register: RFIP_TXCFG */ #define PHY_RFIP_TXCFG_TX_DAC_DEMEN_POS 0 #define PHY_RFIP_TXCFG_TX_DAC_DEMEN_LEN 3 #define PHY_RFIP_TXCFG_TX_DAC_DEMEN_MSK 0x7 #define PHY_RFIP_TXCFG_TX_DACANA_TEST_POS 3 #define PHY_RFIP_TXCFG_TX_DACANA_TEST_LEN 4 #define PHY_RFIP_TXCFG_TX_DACANA_TEST_MSK 0x78 #define PHY_RFIP_TXCFG_TX_TEST_SEL_POS 7 #define PHY_RFIP_TXCFG_TX_TEST_SEL_LEN 1 #define PHY_RFIP_TXCFG_TX_TEST_SEL_MSK 0x80 #define PHY_RFIP_TXCFG_TX_TEST_SEL_EN 0x80 #define PHY_RFIP_TXCFG_TX_ABB_ICW_POS 8 #define PHY_RFIP_TXCFG_TX_ABB_ICW_LEN 8 #define PHY_RFIP_TXCFG_TX_ABB_ICW_MSK 0xff00 #define PHY_RFIP_TXCFG_TX_ABB_TEST_POS 16 #define PHY_RFIP_TXCFG_TX_ABB_TEST_LEN 5 #define PHY_RFIP_TXCFG_TX_ABB_TEST_MSK 0x1f0000 #define PHY_RFIP_TXCFG_TX_LO_BANDSEL_POS 21 #define PHY_RFIP_TXCFG_TX_LO_BANDSEL_LEN 1 #define PHY_RFIP_TXCFG_TX_LO_BANDSEL_MSK 0x200000 #define PHY_RFIP_TXCFG_TX_LO_BANDSEL_EN 0x200000 #define PHY_RFIP_TXCFG_TX_RF_BANDSEL_POS 22 #define PHY_RFIP_TXCFG_TX_RF_BANDSEL_LEN 1 #define PHY_RFIP_TXCFG_TX_RF_BANDSEL_MSK 0x400000 #define PHY_RFIP_TXCFG_TX_RF_BANDSEL_EN 0x400000 #define PHY_RFIP_TXCFG_TX_IQCAL_BANDSEL_POS 23 #define PHY_RFIP_TXCFG_TX_IQCAL_BANDSEL_LEN 1 #define PHY_RFIP_TXCFG_TX_IQCAL_BANDSEL_MSK 0x800000 #define PHY_RFIP_TXCFG_TX_IQCAL_BANDSEL_EN 0x800000 #define PHY_RFIP_TXCFG_TX_IQCAL_PUP_POS 24 #define PHY_RFIP_TXCFG_TX_IQCAL_PUP_LEN 1 #define PHY_RFIP_TXCFG_TX_IQCAL_PUP_MSK 0x1000000 #define PHY_RFIP_TXCFG_TX_IQCAL_PUP_EN 0x1000000 #define PHY_RFIP_TXCFG_TX_ABB_GCW_POS 25 #define PHY_RFIP_TXCFG_TX_ABB_GCW_LEN 5 #define PHY_RFIP_TXCFG_TX_ABB_GCW_MSK 0x3e000000 #define PHY_RFIP_TXCFG_TX_DIG_TEST_MODE_POS 30 #define PHY_RFIP_TXCFG_TX_DIG_TEST_MODE_LEN 1 #define PHY_RFIP_TXCFG_TX_DIG_TEST_MODE_MSK 0x40000000 #define PHY_RFIP_TXCFG_TX_DIG_TEST_MODE_EN 0x40000000 #define PHY_RFIP_TXCFG_TX_DAC_DELAY_CELL_POS 31 #define PHY_RFIP_TXCFG_TX_DAC_DELAY_CELL_LEN 1 #define PHY_RFIP_TXCFG_TX_DAC_DELAY_CELL_MSK 0x80000000 #define PHY_RFIP_TXCFG_CONFIG_MODE_TX_LB_DAC_PLL_TEST 0x48001F09 #define PHY_RFIP_TXCFG_CONFIG_MODE_TX_IQCAL_LB 0x09001F01 #define PHY_RFIP_TXCFG_CONFIG_MODE_TX_HB_DAC_PLL_TEST 0x48E01F09 #define PHY_RFIP_TXCFG_CONFIG_MODE_TX_ACTIVE_HB 0x0AE01F01 #define PHY_RFIP_TXCFG_CONFIG_MODE_TX_IQCAL_HB 0x0BE01F01 #define PHY_RFIP_TXCFG_CONFIG_MODE_TX_DAC_TEST 0x00001F09 #define PHY_RFIP_TXCFG_CONFIG_MODE_LDO_TEST 0x00000000 #define PHY_RFIP_TXCFG_CONFIG_MODE_TX_ABB_LB_TEST 0x08001F09 #define PHY_RFIP_TXCFG_CONFIG_MODE_TX_ABB_HB_TEST 0x08E01F09 #define PHY_RFIP_TXCFG_CONFIG_MODE_TX_ACTIVE_LB 0x08001F01 /* This is automatically generated description for register: RFIP_TXLDOCFG */ #define PHY_RFIP_TXLDOCFG_TXFORCELDOON_POS 0 #define PHY_RFIP_TXLDOCFG_TXFORCELDOON_LEN 1 #define PHY_RFIP_TXLDOCFG_TXFORCELDOON_MSK 0x1 #define PHY_RFIP_TXLDOCFG_TXFORCELDOON_EN 0x1 #define PHY_RFIP_TXLDOCFG_TX_ABB_LDO_BYP_POS 1 #define PHY_RFIP_TXLDOCFG_TX_ABB_LDO_BYP_LEN 1 #define PHY_RFIP_TXLDOCFG_TX_ABB_LDO_BYP_MSK 0x2 #define PHY_RFIP_TXLDOCFG_TX_ABB_LDO_BYP_EN 0x2 #define PHY_RFIP_TXLDOCFG_TX_ABB_LDO_TST_POS 2 #define PHY_RFIP_TXLDOCFG_TX_ABB_LDO_TST_LEN 1 #define PHY_RFIP_TXLDOCFG_TX_ABB_LDO_TST_MSK 0x4 #define PHY_RFIP_TXLDOCFG_TX_ABB_LDO_TST_EN 0x4 #define PHY_RFIP_TXLDOCFG_TX_RF_LDO_ENDYNCTRL_POS 3 #define PHY_RFIP_TXLDOCFG_TX_RF_LDO_ENDYNCTRL_LEN 2 #define PHY_RFIP_TXLDOCFG_TX_RF_LDO_ENDYNCTRL_MSK 0x18 #define PHY_RFIP_TXLDOCFG_TX_LO_HB_LDO_BYP_POS 5 #define PHY_RFIP_TXLDOCFG_TX_LO_HB_LDO_BYP_LEN 1 #define PHY_RFIP_TXLDOCFG_TX_LO_HB_LDO_BYP_MSK 0x20 #define PHY_RFIP_TXLDOCFG_TX_LO_HB_LDO_BYP_EN 0x20 #define PHY_RFIP_TXLDOCFG_TX_LO_HB_LDO_TST_POS 6 #define PHY_RFIP_TXLDOCFG_TX_LO_HB_LDO_TST_LEN 1 #define PHY_RFIP_TXLDOCFG_TX_LO_HB_LDO_TST_MSK 0x40 #define PHY_RFIP_TXLDOCFG_TX_LO_HB_LDO_TST_EN 0x40 #define PHY_RFIP_TXLDOCFG_TX_LO_LB_LDO_BYP_POS 7 #define PHY_RFIP_TXLDOCFG_TX_LO_LB_LDO_BYP_LEN 1 #define PHY_RFIP_TXLDOCFG_TX_LO_LB_LDO_BYP_MSK 0x80 #define PHY_RFIP_TXLDOCFG_TX_LO_LB_LDO_BYP_EN 0x80 #define PHY_RFIP_TXLDOCFG_TX_LO_LB_LDO_TST_POS 8 #define PHY_RFIP_TXLDOCFG_TX_LO_LB_LDO_TST_LEN 1 #define PHY_RFIP_TXLDOCFG_TX_LO_LB_LDO_TST_MSK 0x100 #define PHY_RFIP_TXLDOCFG_TX_LO_LB_LDO_TST_EN 0x100 #define PHY_RFIP_TXLDOCFG_TX_RF_LDO_LB_BYP_POS 9 #define PHY_RFIP_TXLDOCFG_TX_RF_LDO_LB_BYP_LEN 1 #define PHY_RFIP_TXLDOCFG_TX_RF_LDO_LB_BYP_MSK 0x200 #define PHY_RFIP_TXLDOCFG_TX_RF_LDO_LB_BYP_EN 0x200 #define PHY_RFIP_TXLDOCFG_TX_RF_LDO_LB_TST_POS 10 #define PHY_RFIP_TXLDOCFG_TX_RF_LDO_LB_TST_LEN 4 #define PHY_RFIP_TXLDOCFG_TX_RF_LDO_LB_TST_MSK 0x3c00 #define PHY_RFIP_TXLDOCFG_TX_RF_LDO_HB_BYP_POS 14 #define PHY_RFIP_TXLDOCFG_TX_RF_LDO_HB_BYP_LEN 1 #define PHY_RFIP_TXLDOCFG_TX_RF_LDO_HB_BYP_MSK 0x4000 #define PHY_RFIP_TXLDOCFG_TX_RF_LDO_HB_BYP_EN 0x4000 #define PHY_RFIP_TXLDOCFG_TX_RF_LDO_HB_TST_POS 15 #define PHY_RFIP_TXLDOCFG_TX_RF_LDO_HB_TST_LEN 17 #define PHY_RFIP_TXLDOCFG_TX_RF_LDO_HB_TST_MSK 0xffff8000 #define PHY_RFIP_TXLDOCFG_CONFIG_MODE_TX_DIG_LDO_TEST 0x00000000 #define PHY_RFIP_TXLDOCFG_CONFIG_MODE_TX_LO_HB_LDO_TEST 0x00000000 #define PHY_RFIP_TXLDOCFG_CONFIG_MODE_TX_LO_LB_LDO_TEST 0x00000000 #define PHY_RFIP_TXLDOCFG_CONFIG_MODE_TX_ABB_LDO_TEST 0x00000000 #define PHY_RFIP_TXLDOCFG_CONFIG_MODE_TX_ACTIVE 0x00000009 /* This is automatically generated description for register: RFIP_TXRFCFG */ #define PHY_RFIP_TXRFCFG_TX_LO_TEST_POS 0 #define PHY_RFIP_TXRFCFG_TX_LO_TEST_LEN 4 #define PHY_RFIP_TXRFCFG_TX_LO_TEST_MSK 0xf #define PHY_RFIP_TXRFCFG_TX_RF_CASC_CTRL_POS 4 #define PHY_RFIP_TXRFCFG_TX_RF_CASC_CTRL_LEN 4 #define PHY_RFIP_TXRFCFG_TX_RF_CASC_CTRL_MSK 0xf0 #define PHY_RFIP_TXRFCFG_TX_LPF2_TUNE_POS 8 #define PHY_RFIP_TXRFCFG_TX_LPF2_TUNE_LEN 3 #define PHY_RFIP_TXRFCFG_TX_LPF2_TUNE_MSK 0x700 #define PHY_RFIP_TXRFCFG_TX_IPTAT_CTRL_POS 11 #define PHY_RFIP_TXRFCFG_TX_IPTAT_CTRL_LEN 3 #define PHY_RFIP_TXRFCFG_TX_IPTAT_CTRL_MSK 0x3800 #define PHY_RFIP_TXRFCFG_TX_IPTAT_BCK_POS 14 #define PHY_RFIP_TXRFCFG_TX_IPTAT_BCK_LEN 3 #define PHY_RFIP_TXRFCFG_TX_IPTAT_BCK_MSK 0x1c000 #define PHY_RFIP_TXRFCFG_TX_IPTAT_START_POS 17 #define PHY_RFIP_TXRFCFG_TX_IPTAT_START_LEN 1 #define PHY_RFIP_TXRFCFG_TX_IPTAT_START_MSK 0x20000 #define PHY_RFIP_TXRFCFG_TX_IPTAT_START_EN 0x20000 #define PHY_RFIP_TXRFCFG_TX_IBLEED_CTRL_POS 18 #define PHY_RFIP_TXRFCFG_TX_IBLEED_CTRL_LEN 2 #define PHY_RFIP_TXRFCFG_TX_IBLEED_CTRL_MSK 0xc0000 #define PHY_RFIP_TXRFCFG_TX_LO_LB_2_5_CTRL_POS 20 #define PHY_RFIP_TXRFCFG_TX_LO_LB_2_5_CTRL_LEN 6 #define PHY_RFIP_TXRFCFG_TX_LO_LB_2_5_CTRL_MSK 0x3f00000 #define PHY_RFIP_TXRFCFG_TX_PA_ESDCLAMP_DIS_POS 26 #define PHY_RFIP_TXRFCFG_TX_PA_ESDCLAMP_DIS_LEN 6 #define PHY_RFIP_TXRFCFG_TX_PA_ESDCLAMP_DIS_MSK 0xfc000000 #define PHY_RFIP_TXRFCFG_CONFIG_HIGH_BAND_TX_ACTIVE 0x04042010 #define PHY_RFIP_TXRFCFG_CONFIG_LOW_BAND_TX_ACTIVE1 0x04002010 /* This is automatically generated description for register: RFIP_TXCALCFG */ #define PHY_RFIP_TXCALCFG_TX_IQCAL_GCW_POS 0 #define PHY_RFIP_TXCALCFG_TX_IQCAL_GCW_LEN 11 #define PHY_RFIP_TXCALCFG_TX_IQCAL_GCW_MSK 0x7ff #define PHY_RFIP_TXCALCFG_TX_ADC_CALEN_POS 11 #define PHY_RFIP_TXCALCFG_TX_ADC_CALEN_LEN 1 #define PHY_RFIP_TXCALCFG_TX_ADC_CALEN_MSK 0x800 #define PHY_RFIP_TXCALCFG_TX_ADC_CALEN_EN 0x800 #define PHY_RFIP_TXCALCFG_TX_ADC_TEST_POS 12 #define PHY_RFIP_TXCALCFG_TX_ADC_TEST_LEN 6 #define PHY_RFIP_TXCALCFG_TX_ADC_TEST_MSK 0x3f000 #define PHY_RFIP_TXCALCFG_TX_ADC_AUTOSLEEPEN_POS 18 #define PHY_RFIP_TXCALCFG_TX_ADC_AUTOSLEEPEN_LEN 1 #define PHY_RFIP_TXCALCFG_TX_ADC_AUTOSLEEPEN_MSK 0x40000 #define PHY_RFIP_TXCALCFG_TX_PCL_AUTOSLEEPEN_POS 19 #define PHY_RFIP_TXCALCFG_TX_PCL_AUTOSLEEPEN_LEN 1 #define PHY_RFIP_TXCALCFG_TX_PCL_AUTOSLEEPEN_MSK 0x80000 #define PHY_RFIP_TXCALCFG_TX_VBATSENS_AUTOSLEEPEN_POS 20 #define PHY_RFIP_TXCALCFG_TX_VBATSENS_AUTOSLEEPEN_LEN 1 #define PHY_RFIP_TXCALCFG_TX_VBATSENS_AUTOSLEEPEN_MSK 0xFFF00000 #define PHY_RFIP_TXCALCFG_CONFIG_MODE_AUX_ADC_POW_MES 0x00000000 #define PHY_RFIP_TXCALCFG_CONFIG_MODE_AUX_ADC_TEMP_MES 0x00000000 #define PHY_RFIP_TXCALCFG_CONFIG_MODE_AUX_ADC_CAL 0x00000000 #define PHY_RFIP_TXCALCFG_CONFIG_MODE_IQ_CALIBRATION_HB 0x00000302 #define PHY_RFIP_TXCALCFG_CONFIG_MODE_IQ_CALIBRATION_LB 0x00000383 #define PHY_RFIP_TXCALCFG_CONFIG_MODE_TX_ACTIVE 0x00000000 /* This is automatically generated description for register: RFIP_TXPACFG */ #define PHY_RFIP_TXPACFG_TX_PA_POWER_ICW_POS 0 #define PHY_RFIP_TXPACFG_TX_PA_POWER_ICW_LEN 3 #define PHY_RFIP_TXPACFG_TX_PA_POWER_ICW_MSK 0x7 #define PHY_RFIP_TXPACFG_TX_PA_DRIVER_ICW_POS 3 #define PHY_RFIP_TXPACFG_TX_PA_DRIVER_ICW_LEN 3 #define PHY_RFIP_TXPACFG_TX_PA_DRIVER_ICW_MSK 0x38 #define PHY_RFIP_TXPACFG_TX_PA_NETWORK_IN_CTRL_POS 6 #define PHY_RFIP_TXPACFG_TX_PA_NETWORK_IN_CTRL_LEN 2 #define PHY_RFIP_TXPACFG_TX_PA_NETWORK_IN_CTRL_MSK 0xc0 #define PHY_RFIP_TXPACFG_TX_PA_NETWORK_INTER_CTRL_POS 8 #define PHY_RFIP_TXPACFG_TX_PA_NETWORK_INTER_CTRL_LEN 2 #define PHY_RFIP_TXPACFG_TX_PA_NETWORK_INTER_CTRL_MSK 0x300 #define PHY_RFIP_TXPACFG_TX_PA_NETWORK_OUT_CTRL_POS 10 #define PHY_RFIP_TXPACFG_TX_PA_NETWORK_OUT_CTRL_LEN 2 #define PHY_RFIP_TXPACFG_TX_PA_NETWORK_OUT_CTRL_MSK 0xc00 #define PHY_RFIP_TXPACFG_TX_PA_DRIVER_CASC_CTRL_POS 12 #define PHY_RFIP_TXPACFG_TX_PA_DRIVER_CASC_CTRL_LEN 6 #define PHY_RFIP_TXPACFG_TX_PA_DRIVER_CASC_CTRL_MSK 0x3f000 #define PHY_RFIP_TXPACFG_TX_PA_POWER_CASC_CTRL_POS 18 #define PHY_RFIP_TXPACFG_TX_PA_POWER_CASC_CTRL_LEN 6 #define PHY_RFIP_TXPACFG_TX_PA_POWER_CASC_CTRL_MSK 0xfc0000 #define PHY_RFIP_TXPACFG_TX_PDET_CTRL_POS 24 #define PHY_RFIP_TXPACFG_TX_PDET_CTRL_LEN 8 #define PHY_RFIP_TXPACFG_TX_PDET_CTRL_MSK 0xff000000 #define PHY_RFIP_TXPACFG_CONFIG_MODE_DEFAULT 0x21924000 /* This is automatically generated description for register: RFIP_TXPSDELAY */ #define PHY_RFIP_TXPSDELAY_TXBIASONDELAY_POS 0 #define PHY_RFIP_TXPSDELAY_TXBIASONDELAY_LEN 16 #define PHY_RFIP_TXPSDELAY_TXBIASONDELAY_MSK 0xffff #define PHY_RFIP_TXPSDELAY_TXLDOLQDELAY_POS 16 #define PHY_RFIP_TXPSDELAY_TXLDOLQDELAY_LEN 16 #define PHY_RFIP_TXPSDELAY_TXLDOLQDELAY_MSK 0xffff0000 #define PHY_RFIP_TXPSDELAY_CONFIG_MODE_DEFAULT 0x00500050 /* This is automatically generated description for register: RFIP_TXRFOFFDELAY */ #define PHY_RFIP_TXRFOFFDELAY_CONFIG_MODE_DEFAULT 0x000000A0 /* This is automatically generated description for register: RFIP_TXRFLDOHBCFG */ #define PHY_RFIP_TXRFLDOHBCFG_TX_RF_LDO_HB_CTRL_0_POS 0 #define PHY_RFIP_TXRFLDOHBCFG_TX_RF_LDO_HB_CTRL_0_LEN 8 #define PHY_RFIP_TXRFLDOHBCFG_TX_RF_LDO_HB_CTRL_0_MSK 0xff #define PHY_RFIP_TXRFLDOHBCFG_TX_RF_LDO_HB_CTRL_1_POS 8 #define PHY_RFIP_TXRFLDOHBCFG_TX_RF_LDO_HB_CTRL_1_LEN 8 #define PHY_RFIP_TXRFLDOHBCFG_TX_RF_LDO_HB_CTRL_1_MSK 0xff00 #define PHY_RFIP_TXRFLDOHBCFG_TX_RF_LDO_HB_CTRL_2_POS 16 #define PHY_RFIP_TXRFLDOHBCFG_TX_RF_LDO_HB_CTRL_2_LEN 8 #define PHY_RFIP_TXRFLDOHBCFG_TX_RF_LDO_HB_CTRL_2_MSK 0xff0000 #define PHY_RFIP_TXRFLDOHBCFG_TX_RF_LDO_HB_CTRL_3_POS 24 #define PHY_RFIP_TXRFLDOHBCFG_TX_RF_LDO_HB_CTRL_3_LEN 8 #define PHY_RFIP_TXRFLDOHBCFG_TX_RF_LDO_HB_CTRL_3_MSK 0xff000000 #define PHY_RFIP_TXRFLDOHBCFG_CONFIG_MODE_DEFAULT 0x07030100 /* This is automatically generated description for register: RFIP_TXRFLDOHBCFG2 */ #define PHY_RFIP_TXRFLDOHBCFG2_TX_RF_LDO_HB_CTRL_4_POS 0 #define PHY_RFIP_TXRFLDOHBCFG2_TX_RF_LDO_HB_CTRL_4_LEN 8 #define PHY_RFIP_TXRFLDOHBCFG2_TX_RF_LDO_HB_CTRL_4_MSK 0xff #define PHY_RFIP_TXRFLDOHBCFG2_TX_RF_LDO_HB_CTRL_5_POS 8 #define PHY_RFIP_TXRFLDOHBCFG2_TX_RF_LDO_HB_CTRL_5_LEN 8 #define PHY_RFIP_TXRFLDOHBCFG2_TX_RF_LDO_HB_CTRL_5_MSK 0xff00 #define PHY_RFIP_TXRFLDOHBCFG2_TX_RF_LDO_HB_CTRL_6_POS 16 #define PHY_RFIP_TXRFLDOHBCFG2_TX_RF_LDO_HB_CTRL_6_LEN 8 #define PHY_RFIP_TXRFLDOHBCFG2_TX_RF_LDO_HB_CTRL_6_MSK 0xff0000 #define PHY_RFIP_TXRFLDOHBCFG2_TX_RF_LDO_HB_CTRL_7_POS 24 #define PHY_RFIP_TXRFLDOHBCFG2_TX_RF_LDO_HB_CTRL_7_LEN 8 #define PHY_RFIP_TXRFLDOHBCFG2_TX_RF_LDO_HB_CTRL_7_MSK 0xff000000 #define PHY_RFIP_TXRFLDOHBCFG2_CONFIG_MODE_DEFAULT 0x7F3F1F0F /* This is automatically generated description for register: RFIP_TXRFLDOHBLBCFG */ #define PHY_RFIP_TXRFLDOHBLBCFG_TX_RF_LDO_HB_CTRL_8_POS 0 #define PHY_RFIP_TXRFLDOHBLBCFG_TX_RF_LDO_HB_CTRL_8_LEN 8 #define PHY_RFIP_TXRFLDOHBLBCFG_TX_RF_LDO_HB_CTRL_8_MSK 0xff #define PHY_RFIP_TXRFLDOHBLBCFG_TX_RF_LDO_LB_CTRL_8_POS 8 #define PHY_RFIP_TXRFLDOHBLBCFG_TX_RF_LDO_LB_CTRL_8_LEN 24 #define PHY_RFIP_TXRFLDOHBLBCFG_TX_RF_LDO_LB_CTRL_8_MSK 0xffffff00 #define PHY_RFIP_TXRFLDOHBLBCFG_CONFIG_MODE_DEFAULT 0x0000FFFF /* This is automatically generated description for register: RFIP_TXRFLDOLBCFG */ #define PHY_RFIP_TXRFLDOLBCFG_TX_RF_LDO_LB_CTRL_0_POS 0 #define PHY_RFIP_TXRFLDOLBCFG_TX_RF_LDO_LB_CTRL_0_LEN 8 #define PHY_RFIP_TXRFLDOLBCFG_TX_RF_LDO_LB_CTRL_0_MSK 0xff #define PHY_RFIP_TXRFLDOLBCFG_TX_RF_LDO_LB_CTRL_1_POS 8 #define PHY_RFIP_TXRFLDOLBCFG_TX_RF_LDO_LB_CTRL_1_LEN 8 #define PHY_RFIP_TXRFLDOLBCFG_TX_RF_LDO_LB_CTRL_1_MSK 0xff00 #define PHY_RFIP_TXRFLDOLBCFG_TX_RF_LDO_LB_CTRL_2_POS 16 #define PHY_RFIP_TXRFLDOLBCFG_TX_RF_LDO_LB_CTRL_2_LEN 8 #define PHY_RFIP_TXRFLDOLBCFG_TX_RF_LDO_LB_CTRL_2_MSK 0xff0000 #define PHY_RFIP_TXRFLDOLBCFG_TX_RF_LDO_LB_CTRL_3_POS 24 #define PHY_RFIP_TXRFLDOLBCFG_TX_RF_LDO_LB_CTRL_3_LEN 8 #define PHY_RFIP_TXRFLDOLBCFG_TX_RF_LDO_LB_CTRL_3_MSK 0xff000000 #define PHY_RFIP_TXRFLDOLBCFG_CONFIG_MODE_DEFAULT 0x07030100 /* This is automatically generated description for register: RFIP_TXRFLDOLBCFG2 */ #define PHY_RFIP_TXRFLDOLBCFG2_TX_RF_LDO_LB_CTRL_4_POS 0 #define PHY_RFIP_TXRFLDOLBCFG2_TX_RF_LDO_LB_CTRL_4_LEN 8 #define PHY_RFIP_TXRFLDOLBCFG2_TX_RF_LDO_LB_CTRL_4_MSK 0xff #define PHY_RFIP_TXRFLDOLBCFG2_TX_RF_LDO_LB_CTRL_5_POS 8 #define PHY_RFIP_TXRFLDOLBCFG2_TX_RF_LDO_LB_CTRL_5_LEN 8 #define PHY_RFIP_TXRFLDOLBCFG2_TX_RF_LDO_LB_CTRL_5_MSK 0xff00 #define PHY_RFIP_TXRFLDOLBCFG2_TX_RF_LDO_LB_CTRL_6_POS 16 #define PHY_RFIP_TXRFLDOLBCFG2_TX_RF_LDO_LB_CTRL_6_LEN 8 #define PHY_RFIP_TXRFLDOLBCFG2_TX_RF_LDO_LB_CTRL_6_MSK 0xff0000 #define PHY_RFIP_TXRFLDOLBCFG2_TX_RF_LDO_LB_CTRL_7_POS 24 #define PHY_RFIP_TXRFLDOLBCFG2_TX_RF_LDO_LB_CTRL_7_LEN 8 #define PHY_RFIP_TXRFLDOLBCFG2_TX_RF_LDO_LB_CTRL_7_MSK 0xff000000 #define PHY_RFIP_TXRFLDOLBCFG2_CONFIG_MODE_DEFAULT 0x7F3F1F0F /* This is automatically generated description for register: RFIP_RFPLLCFG */ #define PHY_RFIP_RFPLLCFG_PLL_PFD_PUP_POS 0 #define PHY_RFIP_RFPLLCFG_PLL_PFD_PUP_LEN 1 #define PHY_RFIP_RFPLLCFG_PLL_PFD_PUP_MSK 0x1 #define PHY_RFIP_RFPLLCFG_PLL_PFD_PUP_EN 0x1 #define PHY_RFIP_RFPLLCFG_PLL_CP_PUP_POS 1 #define PHY_RFIP_RFPLLCFG_PLL_CP_PUP_LEN 2 #define PHY_RFIP_RFPLLCFG_PLL_CP_PUP_MSK 0x6 #define PHY_RFIP_RFPLLCFG_PLL_CP_LDO_PUP_POS 3 #define PHY_RFIP_RFPLLCFG_PLL_CP_LDO_PUP_LEN 1 #define PHY_RFIP_RFPLLCFG_PLL_CP_LDO_PUP_MSK 0x8 #define PHY_RFIP_RFPLLCFG_PLL_CP_LDO_PUP_EN 0x8 #define PHY_RFIP_RFPLLCFG_PLL_DIG_LDO_PUP_CFG_POS 4 #define PHY_RFIP_RFPLLCFG_PLL_DIG_LDO_PUP_CFG_LEN 1 #define PHY_RFIP_RFPLLCFG_PLL_DIG_LDO_PUP_CFG_MSK 0x10 #define PHY_RFIP_RFPLLCFG_PLL_DIG_LDO_PUP_CFG_EN 0x10 #define PHY_RFIP_RFPLLCFG_PLL_PIP_LDO_PUP_POS 5 #define PHY_RFIP_RFPLLCFG_PLL_PIP_LDO_PUP_LEN 1 #define PHY_RFIP_RFPLLCFG_PLL_PIP_LDO_PUP_MSK 0x20 #define PHY_RFIP_RFPLLCFG_PLL_PIP_LDO_PUP_EN 0x20 #define PHY_RFIP_RFPLLCFG_PLL_VREFBUFF_PUP_POS 6 #define PHY_RFIP_RFPLLCFG_PLL_VREFBUFF_PUP_LEN 1 #define PHY_RFIP_RFPLLCFG_PLL_VREFBUFF_PUP_MSK 0x40 #define PHY_RFIP_RFPLLCFG_PLL_VREFBUFF_PUP_EN 0x40 #define PHY_RFIP_RFPLLCFG_PLL_DCW_POS 7 #define PHY_RFIP_RFPLLCFG_PLL_DCW_LEN 1 #define PHY_RFIP_RFPLLCFG_PLL_DCW_MSK 0x80 #define PHY_RFIP_RFPLLCFG_PLL_DCW_EN 0x80 #define PHY_RFIP_RFPLLCFG_PLL_SW_POS 8 #define PHY_RFIP_RFPLLCFG_PLL_SW_LEN 4 #define PHY_RFIP_RFPLLCFG_PLL_SW_MSK 0xf00 #define PHY_RFIP_RFPLLCFG_PLL_FCOMPSEL_POS 12 #define PHY_RFIP_RFPLLCFG_PLL_FCOMPSEL_LEN 1 #define PHY_RFIP_RFPLLCFG_PLL_FCOMPSEL_MSK 0x1000 #define PHY_RFIP_RFPLLCFG_PLL_FCOMPSEL_EN 0x1000 #define PHY_RFIP_RFPLLCFG_PLL_FREFSEL_POS 13 #define PHY_RFIP_RFPLLCFG_PLL_FREFSEL_LEN 1 #define PHY_RFIP_RFPLLCFG_PLL_FREFSEL_MSK 0x2000 #define PHY_RFIP_RFPLLCFG_PLL_FREFSEL_EN 0x2000 #define PHY_RFIP_RFPLLCFG_PLL_CP_ICW_POS 14 #define PHY_RFIP_RFPLLCFG_PLL_CP_ICW_LEN 3 #define PHY_RFIP_RFPLLCFG_PLL_CP_ICW_MSK 0x1c000 #define PHY_RFIP_RFPLLCFG_PLL_CP_ISEL_POS 17 #define PHY_RFIP_RFPLLCFG_PLL_CP_ISEL_LEN 1 #define PHY_RFIP_RFPLLCFG_PLL_CP_ISEL_MSK 0x20000 #define PHY_RFIP_RFPLLCFG_PLL_CP_ISEL_EN 0x20000 #define PHY_RFIP_RFPLLCFG_PLL_SDFILTERSEL_POS 18 #define PHY_RFIP_RFPLLCFG_PLL_SDFILTERSEL_LEN 1 #define PHY_RFIP_RFPLLCFG_PLL_SDFILTERSEL_MSK 0x40000 #define PHY_RFIP_RFPLLCFG_PLL_SDFILTERSEL_EN 0x40000 #define PHY_RFIP_RFPLLCFG_PLL_SD_OCW_POS 19 #define PHY_RFIP_RFPLLCFG_PLL_SD_OCW_LEN 2 #define PHY_RFIP_RFPLLCFG_PLL_SD_OCW_MSK 0x180000 #define PHY_RFIP_RFPLLCFG_PLL_SDFILTRSTN_POS 21 #define PHY_RFIP_RFPLLCFG_PLL_SDFILTRSTN_LEN 1 #define PHY_RFIP_RFPLLCFG_PLL_SDFILTRSTN_MSK 0x200000 #define PHY_RFIP_RFPLLCFG_PLL_SDFILTRSTN_EN 0x200000 #define PHY_RFIP_RFPLLCFG_PLL_SDCLKEN_POS 22 #define PHY_RFIP_RFPLLCFG_PLL_SDCLKEN_LEN 1 #define PHY_RFIP_RFPLLCFG_PLL_SDCLKEN_MSK 0x400000 #define PHY_RFIP_RFPLLCFG_PLL_SDCLKEN_EN 0x400000 #define PHY_RFIP_RFPLLCFG_PLL_SDRSTN_POS 23 #define PHY_RFIP_RFPLLCFG_PLL_SDRSTN_LEN 1 #define PHY_RFIP_RFPLLCFG_PLL_SDRSTN_MSK 0x800000 #define PHY_RFIP_RFPLLCFG_PLL_SDRSTN_EN 0x800000 #define PHY_RFIP_RFPLLCFG_PLL_SDMASHRSTN_POS 24 #define PHY_RFIP_RFPLLCFG_PLL_SDMASHRSTN_LEN 1 #define PHY_RFIP_RFPLLCFG_PLL_SDMASHRSTN_MSK 0x1000000 #define PHY_RFIP_RFPLLCFG_PLL_SDMASHRSTN_EN 0x1000000 #define PHY_RFIP_RFPLLCFG_PLL_SDMASHCLK_POS 25 #define PHY_RFIP_RFPLLCFG_PLL_SDMASHCLK_LEN 2 #define PHY_RFIP_RFPLLCFG_PLL_SDMASHCLK_MSK 0x6000000 #define PHY_RFIP_RFPLLCFG_PLL_DIG_LDO_TEST_POS 27 #define PHY_RFIP_RFPLLCFG_PLL_DIG_LDO_TEST_LEN 1 #define PHY_RFIP_RFPLLCFG_PLL_DIG_LDO_TEST_MSK 0x8000000 #define PHY_RFIP_RFPLLCFG_PLL_DIG_LDO_TEST_EN 0x8000000 #define PHY_RFIP_RFPLLCFG_PLL_PIP_LDO_TEST_POS 28 #define PHY_RFIP_RFPLLCFG_PLL_PIP_LDO_TEST_LEN 4 #define PHY_RFIP_RFPLLCFG_PLL_PIP_LDO_TEST_MSK 0xf0000000 #define PHY_RFIP_RFPLLCFG_CONFIG_MODE_PLL_LDO_ON 0x000370B8 #define PHY_RFIP_RFPLLCFG_CONFIG_MODE_PLL_ANALOG_ON 0x000370FB #define PHY_RFIP_RFPLLCFG_CONFIG_MODE_PLL_ENABLED 0x03E370FB #define PHY_RFIP_RFPLLCFG_CONFIG_MODE_TEST_ALL_LDO_ON 0x000370B8 #define PHY_RFIP_RFPLLCFG_CONFIG_MODE_PLL_DISABLED 0x00037080 /* This is automatically generated description for register: RFIP_RFPLLCFG2 */ #define PHY_RFIP_RFPLLCFG2_PLL_REFFREQ_SEL_POS 0 #define PHY_RFIP_RFPLLCFG2_PLL_REFFREQ_SEL_LEN 2 #define PHY_RFIP_RFPLLCFG2_PLL_REFFREQ_SEL_MSK 0x3 #define PHY_RFIP_RFPLLCFG2_PLL_DIVRSTN_POS 2 #define PHY_RFIP_RFPLLCFG2_PLL_DIVRSTN_LEN 1 #define PHY_RFIP_RFPLLCFG2_PLL_DIVRSTN_MSK 0x4 #define PHY_RFIP_RFPLLCFG2_PLL_DIVRSTN_EN 0x4 #define PHY_RFIP_RFPLLCFG2_PLL_RSTN_CFG_POS 3 #define PHY_RFIP_RFPLLCFG2_PLL_RSTN_CFG_LEN 1 #define PHY_RFIP_RFPLLCFG2_PLL_RSTN_CFG_MSK 0x8 #define PHY_RFIP_RFPLLCFG2_PLL_RSTN_CFG_EN 0x8 #define PHY_RFIP_RFPLLCFG2_PLL_CLKCTRL_RSTN_POS 4 #define PHY_RFIP_RFPLLCFG2_PLL_CLKCTRL_RSTN_LEN 1 #define PHY_RFIP_RFPLLCFG2_PLL_CLKCTRL_RSTN_MSK 0x10 #define PHY_RFIP_RFPLLCFG2_PLL_CLKCTRL_RSTN_EN 0x10 #define PHY_RFIP_RFPLLCFG2_PLL_SYNC_RSTN_POS 5 #define PHY_RFIP_RFPLLCFG2_PLL_SYNC_RSTN_LEN 1 #define PHY_RFIP_RFPLLCFG2_PLL_SYNC_RSTN_MSK 0x20 #define PHY_RFIP_RFPLLCFG2_PLL_SYNC_RSTN_EN 0x20 #define PHY_RFIP_RFPLLCFG2_PLL_CPLDO_TEST_POS 6 #define PHY_RFIP_RFPLLCFG2_PLL_CPLDO_TEST_LEN 1 #define PHY_RFIP_RFPLLCFG2_PLL_CPLDO_TEST_MSK 0x40 #define PHY_RFIP_RFPLLCFG2_PLL_CPLDO_TEST_EN 0x40 #define PHY_RFIP_RFPLLCFG2_PLL_TEST_COMP_POS 7 #define PHY_RFIP_RFPLLCFG2_PLL_TEST_COMP_LEN 1 #define PHY_RFIP_RFPLLCFG2_PLL_TEST_COMP_MSK 0x80 #define PHY_RFIP_RFPLLCFG2_PLL_TEST_COMP_EN 0x80 #define PHY_RFIP_RFPLLCFG2_PLL_TEST_REF_POS 8 #define PHY_RFIP_RFPLLCFG2_PLL_TEST_REF_LEN 1 #define PHY_RFIP_RFPLLCFG2_PLL_TEST_REF_MSK 0x100 #define PHY_RFIP_RFPLLCFG2_PLL_TEST_REF_EN 0x100 #define PHY_RFIP_RFPLLCFG2_PLL_DOWNSPLIT_POS 9 #define PHY_RFIP_RFPLLCFG2_PLL_DOWNSPLIT_LEN 2 #define PHY_RFIP_RFPLLCFG2_PLL_DOWNSPLIT_MSK 0x600 #define PHY_RFIP_RFPLLCFG2_PLL_DIGLDO_BYP_POS 11 #define PHY_RFIP_RFPLLCFG2_PLL_DIGLDO_BYP_LEN 1 #define PHY_RFIP_RFPLLCFG2_PLL_DIGLDO_BYP_MSK 0x800 #define PHY_RFIP_RFPLLCFG2_PLL_DIGLDO_BYP_EN 0x800 #define PHY_RFIP_RFPLLCFG2_PLL_DIV2P_LB_PUP_POS 12 #define PHY_RFIP_RFPLLCFG2_PLL_DIV2P_LB_PUP_LEN 1 #define PHY_RFIP_RFPLLCFG2_PLL_DIV2P_LB_PUP_MSK 0x1000 #define PHY_RFIP_RFPLLCFG2_PLL_DIV2P_LB_PUP_EN 0x1000 #define PHY_RFIP_RFPLLCFG2_PLL_DIV2M_LB_PUP_POS 13 #define PHY_RFIP_RFPLLCFG2_PLL_DIV2M_LB_PUP_LEN 1 #define PHY_RFIP_RFPLLCFG2_PLL_DIV2M_LB_PUP_MSK 0x2000 #define PHY_RFIP_RFPLLCFG2_PLL_DIV2M_LB_PUP_EN 0x2000 #define PHY_RFIP_RFPLLCFG2_PLL_PIP_LB_PUP_POS 14 #define PHY_RFIP_RFPLLCFG2_PLL_PIP_LB_PUP_LEN 1 #define PHY_RFIP_RFPLLCFG2_PLL_PIP_LB_PUP_MSK 0x4000 #define PHY_RFIP_RFPLLCFG2_PLL_PIP_LB_PUP_EN 0x4000 #define PHY_RFIP_RFPLLCFG2_PLL_PIP_HB_PUP_POS 15 #define PHY_RFIP_RFPLLCFG2_PLL_PIP_HB_PUP_LEN 1 #define PHY_RFIP_RFPLLCFG2_PLL_PIP_HB_PUP_MSK 0x8000 #define PHY_RFIP_RFPLLCFG2_PLL_PIP_HB_PUP_EN 0x8000 #define PHY_RFIP_RFPLLCFG2_PLL_CPLDO_LQB_POS 16 #define PHY_RFIP_RFPLLCFG2_PLL_CPLDO_LQB_LEN 1 #define PHY_RFIP_RFPLLCFG2_PLL_CPLDO_LQB_MSK 0x10000 #define PHY_RFIP_RFPLLCFG2_PLL_CPLDO_LQB_EN 0x10000 #define PHY_RFIP_RFPLLCFG2_PLL_CPLDO_BYP_POS 17 #define PHY_RFIP_RFPLLCFG2_PLL_CPLDO_BYP_LEN 1 #define PHY_RFIP_RFPLLCFG2_PLL_CPLDO_BYP_MSK 0x20000 #define PHY_RFIP_RFPLLCFG2_PLL_CPLDO_BYP_EN 0x20000 #define PHY_RFIP_RFPLLCFG2_PLL_VCOLDO_LQB_POS 18 #define PHY_RFIP_RFPLLCFG2_PLL_VCOLDO_LQB_LEN 1 #define PHY_RFIP_RFPLLCFG2_PLL_VCOLDO_LQB_MSK 0x40000 #define PHY_RFIP_RFPLLCFG2_PLL_VCOLDO_LQB_EN 0x40000 #define PHY_RFIP_RFPLLCFG2_PLL_VCOLDO_BYP_POS 19 #define PHY_RFIP_RFPLLCFG2_PLL_VCOLDO_BYP_LEN 1 #define PHY_RFIP_RFPLLCFG2_PLL_VCOLDO_BYP_MSK 0x80000 #define PHY_RFIP_RFPLLCFG2_PLL_VCOLDO_BYP_EN 0x80000 #define PHY_RFIP_RFPLLCFG2_PLL_DIGLDO_LQB_POS 20 #define PHY_RFIP_RFPLLCFG2_PLL_DIGLDO_LQB_LEN 1 #define PHY_RFIP_RFPLLCFG2_PLL_DIGLDO_LQB_MSK 0x100000 #define PHY_RFIP_RFPLLCFG2_PLL_DIGLDO_LQB_EN 0x100000 #define PHY_RFIP_RFPLLCFG2_PLL_PIPLDO_LQB_POS 21 #define PHY_RFIP_RFPLLCFG2_PLL_PIPLDO_LQB_LEN 1 #define PHY_RFIP_RFPLLCFG2_PLL_PIPLDO_LQB_MSK 0x200000 #define PHY_RFIP_RFPLLCFG2_PLL_PIPLDO_LQB_EN 0x200000 #define PHY_RFIP_RFPLLCFG2_PLL_PIPLDO_BYP_POS 22 #define PHY_RFIP_RFPLLCFG2_PLL_PIPLDO_BYP_LEN 1 #define PHY_RFIP_RFPLLCFG2_PLL_PIPLDO_BYP_MSK 0x400000 #define PHY_RFIP_RFPLLCFG2_PLL_PIPLDO_BYP_EN 0x400000 #define PHY_RFIP_RFPLLCFG2_PLL_SELFCOMPMES_POS 23 #define PHY_RFIP_RFPLLCFG2_PLL_SELFCOMPMES_LEN 4 #define PHY_RFIP_RFPLLCFG2_PLL_SELFCOMPMES_MSK 0x7800000 #define PHY_RFIP_RFPLLCFG2_PLL_SPARE_OUT_POS 27 #define PHY_RFIP_RFPLLCFG2_PLL_SPARE_OUT_LEN 5 #define PHY_RFIP_RFPLLCFG2_PLL_SPARE_OUT_MSK 0xf8000000 #define PHY_RFIP_RFPLLCFG2_CONFIG_LOW_BAND_VCOHB_PLL_ANALOG_ON 0x00008201 #define PHY_RFIP_RFPLLCFG2_CONFIG_LOW_BAND_VCOLB_PLL_ANALOG_ON1 0x00007201 #define PHY_RFIP_RFPLLCFG2_CONFIG_HIGH_BAND_PLL_LDO_ON 0x00000201 #define PHY_RFIP_RFPLLCFG2_CONFIG_LOW_BAND_VCOHB_PLL_ENABLED 0x0000823D #define PHY_RFIP_RFPLLCFG2_CONFIG_LOW_BAND_VCOLB_PLL_ENABLED4 0x0000723D #define PHY_RFIP_RFPLLCFG2_CONFIG_HIGH_BAND_PLL_ANALOG_ON5 0x00008201 #define PHY_RFIP_RFPLLCFG2_CONFIG_HIGH_BAND_PLL_ENABLED6 0x0000823D #define PHY_RFIP_RFPLLCFG2_CONFIG_HIGH_BAND_PLL_LDO_FULL_MODE 0x0035823D #define PHY_RFIP_RFPLLCFG2_CONFIG_LOW_BAND_VCOHB_PLL_LDO_FULL_MODE8 0x0035823D #define PHY_RFIP_RFPLLCFG2_CONFIG_LOW_BAND_VCOLB_PLL_LDO_FULL_MODE9 0x0035723D #define PHY_RFIP_RFPLLCFG2_CONFIG_LOW_BAND_VCOHB_PLL_DISABLED 0x00000201 #define PHY_RFIP_RFPLLCFG2_CONFIG_LOW_BAND_VCOLB_PLL_DISABLED11 0x00000201 #define PHY_RFIP_RFPLLCFG2_CONFIG_ATE_RFIP_OFF_LDO_ON 0x00000000 #define PHY_RFIP_RFPLLCFG2_CONFIG_LOW_BAND_VCOHB_PLL_LDO_ON13 0x00000201 #define PHY_RFIP_RFPLLCFG2_CONFIG_LOW_BAND_VCOLB_PLL_LDO_ON14 0x00000201 #define PHY_RFIP_RFPLLCFG2_CONFIG_HIGH_BAND_PLL_DISABLED15 0x00000201 /* This is automatically generated description for register: RFIP_VCOCFG */ #define PHY_RFIP_VCOCFG_VCO_BUF_HB_PUP_POS 0 #define PHY_RFIP_VCOCFG_VCO_BUF_HB_PUP_LEN 1 #define PHY_RFIP_VCOCFG_VCO_BUF_HB_PUP_MSK 0x1 #define PHY_RFIP_VCOCFG_VCO_BUF_HB_PUP_EN 0x1 #define PHY_RFIP_VCOCFG_VCO_BUF_LB_PUP_POS 1 #define PHY_RFIP_VCOCFG_VCO_BUF_LB_PUP_LEN 2 #define PHY_RFIP_VCOCFG_VCO_BUF_LB_PUP_MSK 0x6 #define PHY_RFIP_VCOCFG_VCO_HB_PUP_POS 3 #define PHY_RFIP_VCOCFG_VCO_HB_PUP_LEN 1 #define PHY_RFIP_VCOCFG_VCO_HB_PUP_MSK 0x8 #define PHY_RFIP_VCOCFG_VCO_HB_PUP_EN 0x8 #define PHY_RFIP_VCOCFG_VCO_LB_PUP_POS 4 #define PHY_RFIP_VCOCFG_VCO_LB_PUP_LEN 1 #define PHY_RFIP_VCOCFG_VCO_LB_PUP_MSK 0x10 #define PHY_RFIP_VCOCFG_VCO_LB_PUP_EN 0x10 #define PHY_RFIP_VCOCFG_VCO_DIV2_PUP_POS 5 #define PHY_RFIP_VCOCFG_VCO_DIV2_PUP_LEN 5 #define PHY_RFIP_VCOCFG_VCO_DIV2_PUP_MSK 0x3e0 #define PHY_RFIP_VCOCFG_VCO_SEL_POS 10 #define PHY_RFIP_VCOCFG_VCO_SEL_LEN 3 #define PHY_RFIP_VCOCFG_VCO_SEL_MSK 0x1c00 #define PHY_RFIP_VCOCFG_VCO_CALREQ_POS 13 #define PHY_RFIP_VCOCFG_VCO_CALREQ_LEN 3 #define PHY_RFIP_VCOCFG_VCO_CALREQ_MSK 0xe000 #define PHY_RFIP_VCOCFG_VCO_ALC_FORCE_POS 16 #define PHY_RFIP_VCOCFG_VCO_ALC_FORCE_LEN 3 #define PHY_RFIP_VCOCFG_VCO_ALC_FORCE_MSK 0x70000 #define PHY_RFIP_VCOCFG_VCO_IBUFF_POS 19 #define PHY_RFIP_VCOCFG_VCO_IBUFF_LEN 2 #define PHY_RFIP_VCOCFG_VCO_IBUFF_MSK 0x180000 #define PHY_RFIP_VCOCFG_VCO_LDO_PUP_POS 21 #define PHY_RFIP_VCOCFG_VCO_LDO_PUP_LEN 1 #define PHY_RFIP_VCOCFG_VCO_LDO_PUP_MSK 0x200000 #define PHY_RFIP_VCOCFG_VCO_LDO_PUP_EN 0x200000 #define PHY_RFIP_VCOCFG_VCO_LDO_TST_POS 22 #define PHY_RFIP_VCOCFG_VCO_LDO_TST_LEN 10 #define PHY_RFIP_VCOCFG_VCO_LDO_TST_MSK 0xffc00000 #define PHY_RFIP_VCOCFG_CONFIG_LOW_BAND_VCOHB_PLL_ANALOG_ON 0x0020002A #define PHY_RFIP_VCOCFG_CONFIG_LOW_BAND_VCOLB_PLL_ANALOG_ON1 0x00200412 #define PHY_RFIP_VCOCFG_CONFIG_HIGH_BAND_PLL_LDO_ON 0x00200000 #define PHY_RFIP_VCOCFG_CONFIG_LOW_BAND_VCOHB_PLL_ENABLED 0x0020002A #define PHY_RFIP_VCOCFG_CONFIG_LOW_BAND_VCOLB_PLL_ENABLED4 0x00200412 #define PHY_RFIP_VCOCFG_CONFIG_HIGH_BAND_PLL_ANALOG_ON5 0x00200029 #define PHY_RFIP_VCOCFG_CONFIG_HIGH_BAND_PLL_ENABLED6 0x00200029 #define PHY_RFIP_VCOCFG_CONFIG_HIGH_BAND_PLL_ACTIVE 0x00202029 #define PHY_RFIP_VCOCFG_CONFIG_LOW_BAND_VCOHB_PLL_ACTIVE8 0x0020202A #define PHY_RFIP_VCOCFG_CONFIG_LOW_BAND_VCOLB_PLL_ACTIVE9 0x00202412 #define PHY_RFIP_VCOCFG_CONFIG_LOW_BAND_VCOHB_PLL_DISABLED 0x00000000 #define PHY_RFIP_VCOCFG_CONFIG_LOW_BAND_VCOLB_PLL_DISABLED11 0x00000000 #define PHY_RFIP_VCOCFG_CONFIG_LOW_BAND_VCOHB_PLL_LDO_ON12 0x00200000 #define PHY_RFIP_VCOCFG_CONFIG_LOW_BAND_VCOLB_PLL_LDO_ON13 0x00200000 #define PHY_RFIP_VCOCFG_CONFIG_HIGH_BAND_PLL_DISABLED14 0x00000000 /* This is automatically generated description for register: RFIP_VCOCAL */ #define PHY_RFIP_VCOCAL_VCO_AMPCALSEL_POS 0 #define PHY_RFIP_VCOCAL_VCO_AMPCALSEL_LEN 1 #define PHY_RFIP_VCOCAL_VCO_AMPCALSEL_MSK 0x1 #define PHY_RFIP_VCOCAL_VCO_AMPCALSEL_EN 0x1 #define PHY_RFIP_VCOCAL_VCO_FREQCALSEL_POS 1 #define PHY_RFIP_VCOCAL_VCO_FREQCALSEL_LEN 1 #define PHY_RFIP_VCOCAL_VCO_FREQCALSEL_MSK 0x2 #define PHY_RFIP_VCOCAL_VCO_FREQCALSEL_EN 0x2 #define PHY_RFIP_VCOCAL_VCO_AMPCAL_POS 2 #define PHY_RFIP_VCOCAL_VCO_AMPCAL_LEN 8 #define PHY_RFIP_VCOCAL_VCO_AMPCAL_MSK 0x3fc #define PHY_RFIP_VCOCAL_VCO_FREQCAL_POS 10 #define PHY_RFIP_VCOCAL_VCO_FREQCAL_LEN 8 #define PHY_RFIP_VCOCAL_VCO_FREQCAL_MSK 0x3fc00 #define PHY_RFIP_VCOCAL_VCO_CALRSTN_POS 18 #define PHY_RFIP_VCOCAL_VCO_CALRSTN_LEN 14 #define PHY_RFIP_VCOCAL_VCO_CALRSTN_MSK 0xfffc0000 #define PHY_RFIP_VCOCAL_CONFIG_MODE_PLL_LDO_ON 0x00000000 #define PHY_RFIP_VCOCAL_CONFIG_MODE_PLL_ANALOG_ON 0x00000000 #define PHY_RFIP_VCOCAL_CONFIG_MODE_PLL_ENABLED 0x00000000 #define PHY_RFIP_VCOCAL_CONFIG_MODE_PLL_ACTIVE 0x00040000 #define PHY_RFIP_VCOCAL_CONFIG_MODE_PLL_DISABLED 0x00000000 /* This is automatically generated description for register: RFIP_RFPLLFRACINT */ #define PHY_RFIP_RFPLLFRACINT_PLL_FRAC_POS 0 #define PHY_RFIP_RFPLLFRACINT_PLL_FRAC_LEN 21 #define PHY_RFIP_RFPLLFRACINT_PLL_FRAC_MSK 0x1fffff #define PHY_RFIP_RFPLLFRACINT_PLL_INT_POS 21 #define PHY_RFIP_RFPLLFRACINT_PLL_INT_LEN 11 #define PHY_RFIP_RFPLLFRACINT_PLL_INT_MSK 0xffe00000 #define PHY_RFIP_RFPLLFRACINT_CONFIG_MODE_PLL_LDO_ON 0x00000000 #define PHY_RFIP_RFPLLFRACINT_CONFIG_MODE_PLL_ANALOG_ON 0x00000000 #define PHY_RFIP_RFPLLFRACINT_CONFIG_MODE_PLL_ENABLED 0x00000000 #define PHY_RFIP_RFPLLFRACINT_CONFIG_MODE_PLL_DISABLED 0x00000000 /* This is automatically generated description for register: RFIP_RCCALCTRL */ #define PHY_RFIP_RCCALCTRL_RCCAL_CEN_POS 0 #define PHY_RFIP_RCCALCTRL_RCCAL_CEN_LEN 1 #define PHY_RFIP_RCCALCTRL_RCCAL_CEN_MSK 0x1 #define PHY_RFIP_RCCALCTRL_RCCAL_CEN_EN 0x1 #define PHY_RFIP_RCCALCTRL_RCCAL_REN_POS 1 #define PHY_RFIP_RCCALCTRL_RCCAL_REN_LEN 1 #define PHY_RFIP_RCCALCTRL_RCCAL_REN_MSK 0x2 #define PHY_RFIP_RCCALCTRL_RCCAL_REN_EN 0x2 #define PHY_RFIP_RCCALCTRL_RCCAL_DEBUG_POS 2 #define PHY_RFIP_RCCALCTRL_RCCAL_DEBUG_LEN 1 #define PHY_RFIP_RCCALCTRL_RCCAL_DEBUG_MSK 0x4 #define PHY_RFIP_RCCALCTRL_RCCAL_DEBUG_EN 0x4 #define PHY_RFIP_RCCALCTRL_RX_ADC_RC_UPDATE_CFG_POS 3 #define PHY_RFIP_RCCALCTRL_RX_ADC_RC_UPDATE_CFG_LEN 1 #define PHY_RFIP_RCCALCTRL_RX_ADC_RC_UPDATE_CFG_MSK 0x8 #define PHY_RFIP_RCCALCTRL_RX_ADC_RC_UPDATE_CFG_EN 0x8 #define PHY_RFIP_RCCALCTRL_RX_LPF_RC_UPDATE_CFG_POS 4 #define PHY_RFIP_RCCALCTRL_RX_LPF_RC_UPDATE_CFG_LEN 1 #define PHY_RFIP_RCCALCTRL_RX_LPF_RC_UPDATE_CFG_MSK 0x10 #define PHY_RFIP_RCCALCTRL_RX_LPF_RC_UPDATE_CFG_EN 0x10 #define PHY_RFIP_RCCALCTRL_TX_LPF_RC_UPDATE_CFG_POS 5 #define PHY_RFIP_RCCALCTRL_TX_LPF_RC_UPDATE_CFG_LEN 2 #define PHY_RFIP_RCCALCTRL_TX_LPF_RC_UPDATE_CFG_MSK 0x60 #define PHY_RFIP_RCCALCTRL_RX_ADC_RCAL_FO_POS 7 #define PHY_RFIP_RCCALCTRL_RX_ADC_RCAL_FO_LEN 1 #define PHY_RFIP_RCCALCTRL_RX_ADC_RCAL_FO_MSK 0x80 #define PHY_RFIP_RCCALCTRL_RX_ADC_RCAL_FO_EN 0x80 #define PHY_RFIP_RCCALCTRL_RX_LPF_CCAL_FO_POS 8 #define PHY_RFIP_RCCALCTRL_RX_LPF_CCAL_FO_LEN 1 #define PHY_RFIP_RCCALCTRL_RX_LPF_CCAL_FO_MSK 0x100 #define PHY_RFIP_RCCALCTRL_RX_LPF_CCAL_FO_EN 0x100 #define PHY_RFIP_RCCALCTRL_TX_LPF_CCAL_FO_POS 9 #define PHY_RFIP_RCCALCTRL_TX_LPF_CCAL_FO_LEN 2 #define PHY_RFIP_RCCALCTRL_TX_LPF_CCAL_FO_MSK 0x600 #define PHY_RFIP_RCCALCTRL_RCCAL_RTMAX_POS 11 #define PHY_RFIP_RCCALCTRL_RCCAL_RTMAX_LEN 6 #define PHY_RFIP_RCCALCTRL_RCCAL_RTMAX_MSK 0x1f800 #define PHY_RFIP_RCCALCTRL_RCCAL_CTMAX_POS 17 #define PHY_RFIP_RCCALCTRL_RCCAL_CTMAX_LEN 6 #define PHY_RFIP_RCCALCTRL_RCCAL_CTMAX_MSK 0x7e0000 #define PHY_RFIP_RCCALCTRL_RCCAL_RFORCE_POS 23 #define PHY_RFIP_RCCALCTRL_RCCAL_RFORCE_LEN 1 #define PHY_RFIP_RCCALCTRL_RCCAL_RFORCE_MSK 0x800000 #define PHY_RFIP_RCCALCTRL_RCCAL_RFORCE_EN 0x800000 #define PHY_RFIP_RCCALCTRL_RCCAL_CFORCE_POS 24 #define PHY_RFIP_RCCALCTRL_RCCAL_CFORCE_LEN 8 #define PHY_RFIP_RCCALCTRL_RCCAL_CFORCE_MSK 0xff000000 #define PHY_RFIP_RCCALCTRL_CONFIG_MODE_RC_CAL_ENABLED 0x00300001 #define PHY_RFIP_RCCALCTRL_CONFIG_MODE_RC_CAL_UPDATE 0x00300030 #define PHY_RFIP_RCCALCTRL_CONFIG_MODE_RC_CAL_TEST 0x003003B8 #define PHY_RFIP_RCCALCTRL_CONFIG_MODE_RC_CAL_MANUAL 0x0180003B #define PHY_RFIP_RCCALCTRL_CONFIG_MODE_RC_CAL_DISABLED 0x00300000 /* This is automatically generated description for register: RFIP_RCCALDELAY */ #define PHY_RFIP_RCCALDELAY_RCCAL_RSAMP_DEL_POS 0 #define PHY_RFIP_RCCALDELAY_RCCAL_RSAMP_DEL_LEN 9 #define PHY_RFIP_RCCALDELAY_RCCAL_RSAMP_DEL_MSK 0x1ff #define PHY_RFIP_RCCALDELAY_RCCAL_CSAMP_DEL_POS 9 #define PHY_RFIP_RCCALDELAY_RCCAL_CSAMP_DEL_LEN 23 #define PHY_RFIP_RCCALDELAY_RCCAL_CSAMP_DEL_MSK 0xfffffe00 #define PHY_RFIP_RCCALDELAY_CONFIG_MODE_DEFAULT 0x0000140A /* This is automatically generated description for register: RFIP_RCCALOFFSET */ #define PHY_RFIP_RCCALOFFSET_RX_ADC_RCAL_OFFSET_POS 0 #define PHY_RFIP_RCCALOFFSET_RX_ADC_RCAL_OFFSET_LEN 4 #define PHY_RFIP_RCCALOFFSET_RX_ADC_RCAL_OFFSET_MSK 0xf #define PHY_RFIP_RCCALOFFSET_RX_LPF_CCAL_OFFSET_POS 4 #define PHY_RFIP_RCCALOFFSET_RX_LPF_CCAL_OFFSET_LEN 5 #define PHY_RFIP_RCCALOFFSET_RX_LPF_CCAL_OFFSET_MSK 0x1f0 #define PHY_RFIP_RCCALOFFSET_TX_LPF_CCAL_OFFSET_POS 9 #define PHY_RFIP_RCCALOFFSET_TX_LPF_CCAL_OFFSET_LEN 23 #define PHY_RFIP_RCCALOFFSET_TX_LPF_CCAL_OFFSET_MSK 0xfffffe00 #define PHY_RFIP_RCCALOFFSET_CONFIG_MODE_TYPICAL_OFFSET_VALUE 0x00000000 /* This is automatically generated description for register: RFIP_RCCALTEST */ #define PHY_RFIP_RCCALTEST_RCCAL_RFORCE_VAL_POS 0 #define PHY_RFIP_RCCALTEST_RCCAL_RFORCE_VAL_LEN 4 #define PHY_RFIP_RCCALTEST_RCCAL_RFORCE_VAL_MSK 0xf #define PHY_RFIP_RCCALTEST_RCCAL_RFORCE_ADD_POS 4 #define PHY_RFIP_RCCALTEST_RCCAL_RFORCE_ADD_LEN 4 #define PHY_RFIP_RCCALTEST_RCCAL_RFORCE_ADD_MSK 0xf0 #define PHY_RFIP_RCCALTEST_RCCAL_CFORCE_VAL_POS 8 #define PHY_RFIP_RCCALTEST_RCCAL_CFORCE_VAL_LEN 5 #define PHY_RFIP_RCCALTEST_RCCAL_CFORCE_VAL_MSK 0x1f00 #define PHY_RFIP_RCCALTEST_RCCAL_CFORCE_ADD_POS 13 #define PHY_RFIP_RCCALTEST_RCCAL_CFORCE_ADD_LEN 19 #define PHY_RFIP_RCCALTEST_RCCAL_CFORCE_ADD_MSK 0xffffe000 #define PHY_RFIP_RCCALTEST_CONFIG_MODE_MANUAL_CALIBRATION 0x00000906 #define PHY_RFIP_RCCALTEST_CONFIG_MODE_DEFAULT 0x00000000 /* This is automatically generated description for register: RFIP_ADCCAL_CFG */ #define PHY_RFIP_ADCCAL_CFG_RX_ADCCAL_START_POS 0 #define PHY_RFIP_ADCCAL_CFG_RX_ADCCAL_START_LEN 1 #define PHY_RFIP_ADCCAL_CFG_RX_ADCCAL_START_MSK 0x1 #define PHY_RFIP_ADCCAL_CFG_RX_ADCCAL_START_EN 0x1 #define PHY_RFIP_ADCCAL_CFG_RX_ADCCAL_SWRST_POS 1 #define PHY_RFIP_ADCCAL_CFG_RX_ADCCAL_SWRST_LEN 1 #define PHY_RFIP_ADCCAL_CFG_RX_ADCCAL_SWRST_MSK 0x2 #define PHY_RFIP_ADCCAL_CFG_RX_ADCCAL_SWRST_EN 0x2 #define PHY_RFIP_ADCCAL_CFG_RX_ADCCAL_IQSEL_POS 2 #define PHY_RFIP_ADCCAL_CFG_RX_ADCCAL_IQSEL_LEN 1 #define PHY_RFIP_ADCCAL_CFG_RX_ADCCAL_IQSEL_MSK 0x4 #define PHY_RFIP_ADCCAL_CFG_RX_ADCCAL_IQSEL_EN 0x4 #define PHY_RFIP_ADCCAL_CFG_RX_ADCCAL_CNT1_POS 3 #define PHY_RFIP_ADCCAL_CFG_RX_ADCCAL_CNT1_LEN 3 #define PHY_RFIP_ADCCAL_CFG_RX_ADCCAL_CNT1_MSK 0x38 #define PHY_RFIP_ADCCAL_CFG_RX_ADCCAL_CNT2_POS 11 #define PHY_RFIP_ADCCAL_CFG_RX_ADCCAL_CNT2_LEN 3 #define PHY_RFIP_ADCCAL_CFG_RX_ADCCAL_CNT2_MSK 0x3800 #define PHY_RFIP_ADCCAL_CFG_RX_ADCCAL_THRESHOLD_POS 19 #define PHY_RFIP_ADCCAL_CFG_RX_ADCCAL_THRESHOLD_LEN 8 #define PHY_RFIP_ADCCAL_CFG_RX_ADCCAL_THRESHOLD_MSK 0x7f80000 #define PHY_RFIP_ADCCAL_CFG_RX_ADCCAL_START_OFFSET_POS 27 #define PHY_RFIP_ADCCAL_CFG_RX_ADCCAL_START_OFFSET_LEN 5 #define PHY_RFIP_ADCCAL_CFG_RX_ADCCAL_START_OFFSET_MSK 0xf8000000 #define PHY_RFIP_ADCCAL_CFG_CONFIG_DEFAULT5 0x13E8381C #define PHY_RFIP_ADCCAL_CFG_CONFIG_DEFAULT7 0x13E8381D #define PHY_RFIP_ADCCAL_CFG_CONFIG_MODE_DEFAULT 0x13E8381E /* This is automatically generated description for register: RFIP_TESTMODE */ #define PHY_RFIP_TESTMODE_CONFIG_MODE_IQCAL 0x00000007 /* This is automatically generated description for register: HIF_GENERAL_PURPOSE */ #define PHY_HIF_GENERAL_PURPOSE_REFCLKCONFIG0_POS 0 #define PHY_HIF_GENERAL_PURPOSE_REFCLKCONFIG0_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_REFCLKCONFIG0_MSK 0x1 #define PHY_HIF_GENERAL_PURPOSE_REFCLKCONFIG0_EN 0x1 #define PHY_HIF_GENERAL_PURPOSE_REFCLKCONFIG1_POS 1 #define PHY_HIF_GENERAL_PURPOSE_REFCLKCONFIG1_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_REFCLKCONFIG1_MSK 0x2 #define PHY_HIF_GENERAL_PURPOSE_REFCLKCONFIG1_EN 0x2 #define PHY_HIF_GENERAL_PURPOSE_REFCLKCONFIG2_POS 2 #define PHY_HIF_GENERAL_PURPOSE_REFCLKCONFIG2_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_REFCLKCONFIG2_MSK 0x4 #define PHY_HIF_GENERAL_PURPOSE_REFCLKCONFIG2_EN 0x4 #define PHY_HIF_GENERAL_PURPOSE_REFCLKCONFIG3_POS 3 #define PHY_HIF_GENERAL_PURPOSE_REFCLKCONFIG3_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_REFCLKCONFIG3_MSK 0x8 #define PHY_HIF_GENERAL_PURPOSE_REFCLKCONFIG3_EN 0x8 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV0_POS 4 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV0_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV0_MSK 0x10 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV0_EN 0x10 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV1_POS 5 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV1_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV1_MSK 0x20 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV1_EN 0x20 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV2_POS 6 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV2_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV2_MSK 0x40 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV2_EN 0x40 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV3_POS 7 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV3_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV3_MSK 0x80 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV3_EN 0x80 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV4_POS 8 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV4_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV4_MSK 0x100 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV4_EN 0x100 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV5_POS 9 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV5_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV5_MSK 0x200 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV5_EN 0x200 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV6_POS 10 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV6_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV6_MSK 0x400 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV6_EN 0x400 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV7_POS 11 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV7_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV7_MSK 0x800 #define PHY_HIF_GENERAL_PURPOSE_DPLLNDIV7_EN 0x800 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRACCTRL_POS 12 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRACCTRL_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRACCTRL_MSK 0x1000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRACCTRL_EN 0x1000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC0_POS 13 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC0_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC0_MSK 0x2000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC0_EN 0x2000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC1_POS 14 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC1_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC1_MSK 0x4000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC1_EN 0x4000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC2_POS 15 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC2_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC2_MSK 0x8000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC2_EN 0x8000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC3_POS 16 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC3_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC3_MSK 0x10000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC3_EN 0x10000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC4_POS 17 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC4_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC4_MSK 0x20000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC4_EN 0x20000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC5_POS 18 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC5_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC5_MSK 0x40000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC5_EN 0x40000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC6_POS 19 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC6_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC6_MSK 0x80000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC6_EN 0x80000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC7_POS 20 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC7_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC7_MSK 0x100000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC7_EN 0x100000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC8_POS 21 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC8_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC8_MSK 0x200000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC8_EN 0x200000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC9_POS 22 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC9_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC9_MSK 0x400000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC9_EN 0x400000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC10_POS 23 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC10_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC10_MSK 0x800000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC10_EN 0x800000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC11_POS 24 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC11_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC11_MSK 0x1000000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC11_EN 0x1000000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC12_POS 25 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC12_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC12_MSK 0x2000000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC12_EN 0x2000000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC13_POS 26 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC13_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC13_MSK 0x4000000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC13_EN 0x4000000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC14_POS 27 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC14_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC14_MSK 0x8000000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC14_EN 0x8000000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC15_POS 28 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC15_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC15_MSK 0x10000000 #define PHY_HIF_GENERAL_PURPOSE_DPLLFRAC15_EN 0x10000000 #define PHY_HIF_GENERAL_PURPOSE_DPLLDITHERDIS0_POS 29 #define PHY_HIF_GENERAL_PURPOSE_DPLLDITHERDIS0_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLDITHERDIS0_MSK 0x20000000 #define PHY_HIF_GENERAL_PURPOSE_DPLLDITHERDIS0_EN 0x20000000 #define PHY_HIF_GENERAL_PURPOSE_DPLLDITHERDIS1_POS 30 #define PHY_HIF_GENERAL_PURPOSE_DPLLDITHERDIS1_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLDITHERDIS1_MSK 0x40000000 #define PHY_HIF_GENERAL_PURPOSE_DPLLDITHERDIS1_EN 0x40000000 #define PHY_HIF_GENERAL_PURPOSE_DPLLEN_POS 31 #define PHY_HIF_GENERAL_PURPOSE_DPLLEN_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_DPLLEN_MSK 0x80000000 #define PHY_HIF_GENERAL_PURPOSE_CONFIG_6_DPLL_ENABLED 0x8EC4F121 #define PHY_HIF_GENERAL_PURPOSE_CONFIG_MODE_DPLL_SETTINGS 0x0EC4F121 /* This is automatically generated description for register: HIF_GENERAL_PURPOSE_1 */ #define PHY_HIF_GENERAL_PURPOSE_1_DCXOSTART_POS 0 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOSTART_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOSTART_MSK 0x1 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOSTART_EN 0x1 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM0_POS 1 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM0_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM0_MSK 0x2 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM0_EN 0x2 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM1_POS 2 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM1_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM1_MSK 0x4 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM1_EN 0x4 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM2_POS 3 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM2_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM2_MSK 0x8 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM2_EN 0x8 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM3_POS 4 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM3_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM3_MSK 0x10 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM3_EN 0x10 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM4_POS 5 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM4_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM4_MSK 0x20 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM4_EN 0x20 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM5_POS 6 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM5_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM5_MSK 0x40 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM5_EN 0x40 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM6_POS 7 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM6_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM6_MSK 0x80 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM6_EN 0x80 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM7_POS 8 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM7_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM7_MSK 0x100 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOTRIM7_EN 0x100 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_TRIM0_POS 9 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_TRIM0_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_TRIM0_MSK 0x200 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_TRIM0_EN 0x200 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_TRIM1_POS 10 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_TRIM1_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_TRIM1_MSK 0x400 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_TRIM1_EN 0x400 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_TRIM2_POS 11 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_TRIM2_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_TRIM2_MSK 0x800 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_TRIM2_EN 0x800 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_TRIM3_POS 12 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_TRIM3_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_TRIM3_MSK 0x1000 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_TRIM3_EN 0x1000 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_TRIM4_POS 13 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_TRIM4_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_TRIM4_MSK 0x2000 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_TRIM4_EN 0x2000 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_CTRL0_POS 14 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_CTRL0_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_CTRL0_MSK 0x4000 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_CTRL0_EN 0x4000 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_CTRL1_POS 15 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_CTRL1_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_CTRL1_MSK 0x8000 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_CTRL1_EN 0x8000 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_CTRL2_POS 16 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_CTRL2_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_CTRL2_MSK 0x10000 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_CTRL2_EN 0x10000 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_CTRL3_POS 17 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_CTRL3_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_CTRL3_MSK 0x20000 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_CTRL3_EN 0x20000 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_CTRL4_POS 18 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_CTRL4_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_CTRL4_MSK 0x40000 #define PHY_HIF_GENERAL_PURPOSE_1_MAIN_BGAP_CTRL4_EN 0x40000 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOMODE0_POS 19 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOMODE0_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOMODE0_MSK 0x80000 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOMODE0_EN 0x80000 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOMODE1_POS 20 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOMODE1_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOMODE1_MSK 0x100000 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOMODE1_EN 0x100000 #define PHY_HIF_GENERAL_PURPOSE_1_LDODCXOEN_POS 21 #define PHY_HIF_GENERAL_PURPOSE_1_LDODCXOEN_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_LDODCXOEN_MSK 0x200000 #define PHY_HIF_GENERAL_PURPOSE_1_LDODCXOEN_EN 0x200000 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOCTRL0_POS 22 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOCTRL0_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOCTRL0_MSK 0x400000 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOCTRL0_EN 0x400000 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOCTRL1_POS 23 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOCTRL1_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOCTRL1_MSK 0x800000 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOCTRL1_EN 0x800000 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOCTRL2_POS 24 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOCTRL2_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOCTRL2_MSK 0x1000000 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOCTRL2_EN 0x1000000 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOCTRL3_POS 25 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOCTRL3_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOCTRL3_MSK 0x2000000 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOCTRL3_EN 0x2000000 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOCTRL4_POS 26 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOCTRL4_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOCTRL4_MSK 0x4000000 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOCTRL4_EN 0x4000000 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOLDOINRUSHB_POS 27 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOLDOINRUSHB_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOLDOINRUSHB_MSK 0x8000000 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOLDOINRUSHB_EN 0x8000000 #define PHY_HIF_GENERAL_PURPOSE_1_FREFDIGEN_POS 28 #define PHY_HIF_GENERAL_PURPOSE_1_FREFDIGEN_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_FREFDIGEN_MSK 0x10000000 #define PHY_HIF_GENERAL_PURPOSE_1_FREFDIGEN_EN 0x10000000 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOMODEDETECTEN_POS 29 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOMODEDETECTEN_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOMODEDETECTEN_MSK 0x20000000 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOMODEDETECTEN_EN 0x20000000 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOCKDIGEN_POS 30 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOCKDIGEN_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOCKDIGEN_MSK 0x40000000 #define PHY_HIF_GENERAL_PURPOSE_1_DCXOCKDIGEN_EN 0x40000000 #define PHY_HIF_GENERAL_PURPOSE_1_DCXO_ALC_EN_POS 31 #define PHY_HIF_GENERAL_PURPOSE_1_DCXO_ALC_EN_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_1_DCXO_ALC_EN_MSK 0x80000000 #define PHY_HIF_GENERAL_PURPOSE_1_CONFIG_2_BG_START_RELEASE 0x01B82080 #define PHY_HIF_GENERAL_PURPOSE_1_CONFIG_2_DCXO_LDO_INRUSH_RELEASE 0x09B82080 #define PHY_HIF_GENERAL_PURPOSE_1_CONFIG_2_DCXO_DIG_ENABLED 0x49B82080 #define PHY_HIF_GENERAL_PURPOSE_1_CONFIG_MODE_DCXO_LDO_START__DCXO_OFF_0x01B86080 /* This is automatically generated description for register: HIF_GENERAL_PURPOSE_2 */ #define PHY_HIF_GENERAL_PURPOSE_2_RX_LNA_TRIM0_POS 0 #define PHY_HIF_GENERAL_PURPOSE_2_RX_LNA_TRIM0_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_2_RX_LNA_TRIM0_MSK 0x1 #define PHY_HIF_GENERAL_PURPOSE_2_RX_LNA_TRIM0_EN 0x1 #define PHY_HIF_GENERAL_PURPOSE_2_RX_LNA_TRIM1_POS 1 #define PHY_HIF_GENERAL_PURPOSE_2_RX_LNA_TRIM1_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_2_RX_LNA_TRIM1_MSK 0x2 #define PHY_HIF_GENERAL_PURPOSE_2_RX_LNA_TRIM1_EN 0x2 #define PHY_HIF_GENERAL_PURPOSE_2_RX_LNA_TRIM2_POS 2 #define PHY_HIF_GENERAL_PURPOSE_2_RX_LNA_TRIM2_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_2_RX_LNA_TRIM2_MSK 0x4 #define PHY_HIF_GENERAL_PURPOSE_2_RX_LNA_TRIM2_EN 0x4 #define PHY_HIF_GENERAL_PURPOSE_2_TX_DAC_TRIM0_POS 3 #define PHY_HIF_GENERAL_PURPOSE_2_TX_DAC_TRIM0_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_2_TX_DAC_TRIM0_MSK 0x8 #define PHY_HIF_GENERAL_PURPOSE_2_TX_DAC_TRIM0_EN 0x8 #define PHY_HIF_GENERAL_PURPOSE_2_TX_DAC_TRIM1_POS 4 #define PHY_HIF_GENERAL_PURPOSE_2_TX_DAC_TRIM1_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_2_TX_DAC_TRIM1_MSK 0x10 #define PHY_HIF_GENERAL_PURPOSE_2_TX_DAC_TRIM1_EN 0x10 #define PHY_HIF_GENERAL_PURPOSE_2_TX_DAC_TRIM2_POS 5 #define PHY_HIF_GENERAL_PURPOSE_2_TX_DAC_TRIM2_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_2_TX_DAC_TRIM2_MSK 0x20 #define PHY_HIF_GENERAL_PURPOSE_2_TX_DAC_TRIM2_EN 0x20 #define PHY_HIF_GENERAL_PURPOSE_2_TX_DAC_TRIM3_POS 6 #define PHY_HIF_GENERAL_PURPOSE_2_TX_DAC_TRIM3_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_2_TX_DAC_TRIM3_MSK 0x40 #define PHY_HIF_GENERAL_PURPOSE_2_TX_DAC_TRIM3_EN 0x40 #define PHY_HIF_GENERAL_PURPOSE_2_CTRL_BIAS_RES_TRIM0_POS 7 #define PHY_HIF_GENERAL_PURPOSE_2_CTRL_BIAS_RES_TRIM0_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_2_CTRL_BIAS_RES_TRIM0_MSK 0x80 #define PHY_HIF_GENERAL_PURPOSE_2_CTRL_BIAS_RES_TRIM0_EN 0x80 #define PHY_HIF_GENERAL_PURPOSE_2_CTRL_BIAS_RES_TRIM1_POS 8 #define PHY_HIF_GENERAL_PURPOSE_2_CTRL_BIAS_RES_TRIM1_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_2_CTRL_BIAS_RES_TRIM1_MSK 0x100 #define PHY_HIF_GENERAL_PURPOSE_2_CTRL_BIAS_RES_TRIM1_EN 0x100 #define PHY_HIF_GENERAL_PURPOSE_2_CTRL_BIAS_RES_TRIM2_POS 9 #define PHY_HIF_GENERAL_PURPOSE_2_CTRL_BIAS_RES_TRIM2_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_2_CTRL_BIAS_RES_TRIM2_MSK 0x200 #define PHY_HIF_GENERAL_PURPOSE_2_CTRL_BIAS_RES_TRIM2_EN 0x200 #define PHY_HIF_GENERAL_PURPOSE_2_CTRL_BIAS_RES_TRIM3_POS 10 #define PHY_HIF_GENERAL_PURPOSE_2_CTRL_BIAS_RES_TRIM3_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_2_CTRL_BIAS_RES_TRIM3_MSK 0x400 #define PHY_HIF_GENERAL_PURPOSE_2_CTRL_BIAS_RES_TRIM3_EN 0x400 #define PHY_HIF_GENERAL_PURPOSE_2_TX_PADRIVER_TRIM0_POS 11 #define PHY_HIF_GENERAL_PURPOSE_2_TX_PADRIVER_TRIM0_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_2_TX_PADRIVER_TRIM0_MSK 0x800 #define PHY_HIF_GENERAL_PURPOSE_2_TX_PADRIVER_TRIM0_EN 0x800 #define PHY_HIF_GENERAL_PURPOSE_2_TX_PADRIVER_TRIM1_POS 12 #define PHY_HIF_GENERAL_PURPOSE_2_TX_PADRIVER_TRIM1_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_2_TX_PADRIVER_TRIM1_MSK 0x1000 #define PHY_HIF_GENERAL_PURPOSE_2_TX_PADRIVER_TRIM1_EN 0x1000 #define PHY_HIF_GENERAL_PURPOSE_2_TX_PADRIVER_TRIM2_POS 13 #define PHY_HIF_GENERAL_PURPOSE_2_TX_PADRIVER_TRIM2_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_2_TX_PADRIVER_TRIM2_MSK 0x2000 #define PHY_HIF_GENERAL_PURPOSE_2_TX_PADRIVER_TRIM2_EN 0x2000 #define PHY_HIF_GENERAL_PURPOSE_2_TX_PADRIVER_TRIM3_POS 14 #define PHY_HIF_GENERAL_PURPOSE_2_TX_PADRIVER_TRIM3_LEN 14 #define PHY_HIF_GENERAL_PURPOSE_2_TX_PADRIVER_TRIM3_MSK 0xfffc000 #define PHY_HIF_GENERAL_PURPOSE_2_FORCEDCXOLSN_POS 28 #define PHY_HIF_GENERAL_PURPOSE_2_FORCEDCXOLSN_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_2_FORCEDCXOLSN_MSK 0x10000000 #define PHY_HIF_GENERAL_PURPOSE_2_FORCEDCXOLSN_EN 0x10000000 #define PHY_HIF_GENERAL_PURPOSE_2_LDORFDIGEN_POS 29 #define PHY_HIF_GENERAL_PURPOSE_2_LDORFDIGEN_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_2_LDORFDIGEN_MSK 0x20000000 #define PHY_HIF_GENERAL_PURPOSE_2_LDORFDIGEN_EN 0x20000000 #define PHY_HIF_GENERAL_PURPOSE_2_DIGLDOBYP_POS 30 #define PHY_HIF_GENERAL_PURPOSE_2_DIGLDOBYP_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_2_DIGLDOBYP_MSK 0x40000000 #define PHY_HIF_GENERAL_PURPOSE_2_DIGLDOBYP_EN 0x40000000 #define PHY_HIF_GENERAL_PURPOSE_2_BBDIGENABLE_POS 31 #define PHY_HIF_GENERAL_PURPOSE_2_BBDIGENABLE_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_2_BBDIGENABLE_MSK 0x80000000 #define PHY_HIF_GENERAL_PURPOSE_2_CONFIG_5_ENABLE_RF_DIG_LDO__BBDIG 0xB000039C #define PHY_HIF_GENERAL_PURPOSE_2_CONFIG_MODE_TRIMMING_SETTINGS_ENABLE_DCXO_LS0x1000039C /* This is automatically generated description for register: HIF_GENERAL_PURPOSE_3 */ #define PHY_HIF_GENERAL_PURPOSE_3_UNUSED_POS 0 #define PHY_HIF_GENERAL_PURPOSE_3_UNUSED_LEN 18 #define PHY_HIF_GENERAL_PURPOSE_3_UNUSED_MSK 0x3ffff #define PHY_HIF_GENERAL_PURPOSE_3_LDO_RFDIG_LS_EN_POS 18 #define PHY_HIF_GENERAL_PURPOSE_3_LDO_RFDIG_LS_EN_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_3_LDO_RFDIG_LS_EN_MSK 0x40000 #define PHY_HIF_GENERAL_PURPOSE_3_LDO_RFDIG_LS_EN_EN 0x40000 #define PHY_HIF_GENERAL_PURPOSE_3_EXTERNAL_LS_EN_POS 19 #define PHY_HIF_GENERAL_PURPOSE_3_EXTERNAL_LS_EN_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_3_EXTERNAL_LS_EN_MSK 0x80000 #define PHY_HIF_GENERAL_PURPOSE_3_EXTERNAL_LS_EN_EN 0x80000 #define PHY_HIF_GENERAL_PURPOSE_3_LPCLK_ENABLE_POS 20 #define PHY_HIF_GENERAL_PURPOSE_3_LPCLK_ENABLE_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_3_LPCLK_ENABLE_MSK 0x100000 #define PHY_HIF_GENERAL_PURPOSE_3_LPCLK_ENABLE_EN 0x100000 #define PHY_HIF_GENERAL_PURPOSE_3_ISOLATION_CELLS_EN_POS 21 #define PHY_HIF_GENERAL_PURPOSE_3_ISOLATION_CELLS_EN_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_3_ISOLATION_CELLS_EN_MSK 0x200000 #define PHY_HIF_GENERAL_PURPOSE_3_ISOLATION_CELLS_EN_EN 0x200000 #define PHY_HIF_GENERAL_PURPOSE_3_CLOCKS_ENABLE_POS 22 #define PHY_HIF_GENERAL_PURPOSE_3_CLOCKS_ENABLE_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_3_CLOCKS_ENABLE_MSK 0x400000 #define PHY_HIF_GENERAL_PURPOSE_3_CLOCKS_ENABLE_EN 0x400000 #define PHY_HIF_GENERAL_PURPOSE_3_DCXO_CONFIGURATION_EN_POS 23 #define PHY_HIF_GENERAL_PURPOSE_3_DCXO_CONFIGURATION_EN_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_3_DCXO_CONFIGURATION_EN_MSK 0x800000 #define PHY_HIF_GENERAL_PURPOSE_3_DCXO_CONFIGURATION_EN_EN 0x800000 #define PHY_HIF_GENERAL_PURPOSE_3_DPLL_CONFIGURATION_EN_POS 24 #define PHY_HIF_GENERAL_PURPOSE_3_DPLL_CONFIGURATION_EN_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_3_DPLL_CONFIGURATION_EN_MSK 0x1000000 #define PHY_HIF_GENERAL_PURPOSE_3_DPLL_CONFIGURATION_EN_EN 0x1000000 #define PHY_HIF_GENERAL_PURPOSE_3_RELEASESLEEPNOT_POS 25 #define PHY_HIF_GENERAL_PURPOSE_3_RELEASESLEEPNOT_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_3_RELEASESLEEPNOT_MSK 0x2000000 #define PHY_HIF_GENERAL_PURPOSE_3_RELEASESLEEPNOT_EN 0x2000000 #define PHY_HIF_GENERAL_PURPOSE_3_BYPASSRESET_EN_POS 26 #define PHY_HIF_GENERAL_PURPOSE_3_BYPASSRESET_EN_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_3_BYPASSRESET_EN_MSK 0x4000000 #define PHY_HIF_GENERAL_PURPOSE_3_BYPASSRESET_EN_EN 0x4000000 #define PHY_HIF_GENERAL_PURPOSE_3_WLAN_LDO1_DISABLE_POS 27 #define PHY_HIF_GENERAL_PURPOSE_3_WLAN_LDO1_DISABLE_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_3_WLAN_LDO1_DISABLE_MSK 0x8000000 #define PHY_HIF_GENERAL_PURPOSE_3_WLAN_LDO1_DISABLE_EN 0x8000000 #define PHY_HIF_GENERAL_PURPOSE_3_WLAN_LDO2_DISABLE_POS 28 #define PHY_HIF_GENERAL_PURPOSE_3_WLAN_LDO2_DISABLE_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_3_WLAN_LDO2_DISABLE_MSK 0x10000000 #define PHY_HIF_GENERAL_PURPOSE_3_WLAN_LDO2_DISABLE_EN 0x10000000 #define PHY_HIF_GENERAL_PURPOSE_3_LSGO2TESTCONTROL_POS 29 #define PHY_HIF_GENERAL_PURPOSE_3_LSGO2TESTCONTROL_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_3_LSGO2TESTCONTROL_MSK 0x20000000 #define PHY_HIF_GENERAL_PURPOSE_3_LSGO2TESTCONTROL_EN 0x20000000 #define PHY_HIF_GENERAL_PURPOSE_3_EXT_CLK_EN_POS 30 #define PHY_HIF_GENERAL_PURPOSE_3_EXT_CLK_EN_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_3_EXT_CLK_EN_MSK 0x40000000 #define PHY_HIF_GENERAL_PURPOSE_3_EXT_CLK_EN_EN 0x40000000 #define PHY_HIF_GENERAL_PURPOSE_3_ISOLATE_DPLLN_POS 31 #define PHY_HIF_GENERAL_PURPOSE_3_ISOLATE_DPLLN_LEN 1 #define PHY_HIF_GENERAL_PURPOSE_3_ISOLATE_DPLLN_MSK 0x80000000 #define PHY_HIF_GENERAL_PURPOSE_3_CONFIG_MODE_SWITCH_REGION_WAKE_UP 0x39840000 #define PHY_HIF_GENERAL_PURPOSE_3_CONFIG_MODE_ENABLE_ISOLATION_CELLS 0x3BA40000 #define PHY_HIF_GENERAL_PURPOSE_3_CONFIG_MODE_EXTERNAL_RESET_ENABLED 0x3FA40000 #define PHY_HIF_GENERAL_PURPOSE_3_CONFIG_7_DPLL_CLOCK_ENABLED 0xBFA40000 #define PHY_HIF_GENERAL_PURPOSE_3_CONFIG_7_CLOCK_ENABLED 0xBFE40000 #define PHY_HIF_GENERAL_PURPOSE_3_CONFIG_MODE_DISABLE_REGULATOR_ENABLE_SWITCH0x39840000 /* This is automatically generated description for register: APB_MIR_WRITE_REG5 */ #define PHY_APB_MIR_WRITE_REG5_CONFIG_14_AUX_ADC 0x100007FF #define PHY_APB_MIR_WRITE_REG5_CONFIG_14_BBDIG_RFIF_I 0x07FF8000 #define PHY_APB_MIR_WRITE_REG5_CONFIG_14_BBDIG_RFIF_Q 0x00000FFF #define PHY_APB_MIR_WRITE_REG5_CONFIG_14_BBDIG_RX_OTHER_I 0x17FF8000 #define PHY_APB_MIR_WRITE_REG5_CONFIG_14_BBDIG_RX_OTHER_Q 0x00002FFF #define PHY_APB_MIR_WRITE_REG5_CONFIG_0AA80000_APB_MIR_ATE_ADC_TEST 0x00003FFF /* This is automatically generated description for register: PHYTESTSETUP */ #define PHY_PHYTESTSETUP_CONFIG_0_BBDIG_DEBUG_BUS 0x00000010 #define PHY_PHYTESTSETUP_CONFIG_ABD0000_PHY__ATE_ADC_TEST 0x000000B0 /* This is automatically generated description for register: RITESTSETUPBBDIG */ #define PHY_RITESTSETUPBBDIG_CONFIG_0_DECBY2_11J_20MHZ 0x00000002 #define PHY_RITESTSETUPBBDIG_CONFIG_0_DECBY2_40MHZ 0x00000003 #define PHY_RITESTSETUPBBDIG_CONFIG_0_AFTER_IQ_CORR_20MHZ 0x00000004 #define PHY_RITESTSETUPBBDIG_CONFIG_0_RXOFDMDEC_20MHZ 0x00000005 #define PHY_RITESTSETUPBBDIG_CONFIG_0_AUCADC 0x00000019 #define PHY_RITESTSETUPBBDIG_CONFIG_ABB8000_BBDIG_RFIF_80MZ 0x00000001 /* This is automatically generated description for register: RITONECTL */ #define PHY_RITONECTL_GEN1_POS 0 #define PHY_RITONECTL_GEN1_LEN 2 #define PHY_RITONECTL_GEN1_MSK 0x3 #define PHY_RITONECTL_GEN2_POS 2 #define PHY_RITONECTL_GEN2_LEN 2 #define PHY_RITONECTL_GEN2_MSK 0xc #define PHY_RITONECTL_MODE_POS 4 #define PHY_RITONECTL_MODE_LEN 28 #define PHY_RITONECTL_MODE_MSK 0xfffffff0 #define PHY_RITONECTL_CONFIG_DEFAULT9 0x8800000F #define PHY_RITONECTL_CONFIG_DEFAULT14 0x8800000F #define PHY_RITONECTL_CONFIG_ABB8000_BBDIG_SINGLE_TONE_QUADRATURE 0x0000001A /* This is automatically generated description for register: RIALCCTL */ #define PHY_RIALCCTL_SEL_POS 0 #define PHY_RIALCCTL_SEL_LEN 1 #define PHY_RIALCCTL_SEL_MSK 0x1 #define PHY_RIALCCTL_SEL_EN 0x1 #define PHY_RIALCCTL_TXPW_POS 1 #define PHY_RIALCCTL_TXPW_LEN 4 #define PHY_RIALCCTL_TXPW_MSK 0x1e #define PHY_RIALCCTL_MEAS_POS 5 #define PHY_RIALCCTL_MEAS_LEN 1 #define PHY_RIALCCTL_MEAS_MSK 0x20 #define PHY_RIALCCTL_MEAS_EN 0x20 #define PHY_RIALCCTL_REP_POS 6 #define PHY_RIALCCTL_REP_LEN 1 #define PHY_RIALCCTL_REP_MSK 0x40 #define PHY_RIALCCTL_REP_EN 0x40 #define PHY_RIALCCTL_SLEEP_POS 7 #define PHY_RIALCCTL_SLEEP_LEN 1 #define PHY_RIALCCTL_SLEEP_MSK 0x80 #define PHY_RIALCCTL_SLEEP_EN 0x80 #define PHY_RIALCCTL_DACGAIN_POS 8 #define PHY_RIALCCTL_DACGAIN_LEN 1 #define PHY_RIALCCTL_DACGAIN_MSK 0x100 #define PHY_RIALCCTL_DACGAIN_EN 0x100 #define PHY_RIALCCTL_MODE_POS 9 #define PHY_RIALCCTL_MODE_LEN 3 #define PHY_RIALCCTL_MODE_MSK 0xe00 #define PHY_RIALCCTL_FORCEON_POS 12 #define PHY_RIALCCTL_FORCEON_LEN 1 #define PHY_RIALCCTL_FORCEON_MSK 0x1000 #define PHY_RIALCCTL_FORCEON_EN 0x1000 #define PHY_RIALCCTL_OVR_POS 13 #define PHY_RIALCCTL_OVR_LEN 1 #define PHY_RIALCCTL_OVR_MSK 0x2000 #define PHY_RIALCCTL_OVR_EN 0x2000 #define PHY_RIALCCTL_ADCINSEL_POS 14 #define PHY_RIALCCTL_ADCINSEL_LEN 2 #define PHY_RIALCCTL_ADCINSEL_MSK 0xC000 #define PHY_RIALCCTL_HB_PDET_CD_POS 16 #define PHY_RIALCCTL_HB_PDET_CD_LEN 2 #define PHY_RIALCCTL_HB_PDET_CD_MSK 0x30000 #define PHY_RIALCCTL_LB_PDET_CD_POS 18 #define PHY_RIALCCTL_LB_PDET_CD_LEN 2 #define PHY_RIALCCTL_LB_PDET_CD_MSK 0xC0000 #define PHY_RIALCCTL_VBAT_CD_POS 20 #define PHY_RIALCCTL_VBAT_CD_LEN 2 #define PHY_RIALCCTL_VBAT_CD_MSK 0x300000 #define PHY_RIALCCTL_TEMP_CD_POS 22 #define PHY_RIALCCTL_TEMP_CD_LEN 2 #define PHY_RIALCCTL_TEMP_CD_MSK 0xC00000 /* This is automatically generated description for register: RICTRL */ #define PHY_RICTRL_BW_POS 0 #define PHY_RICTRL_BW_LEN 1 #define PHY_RICTRL_BW_MSK 0x1 #define PHY_RICTRL_BW_EN 0x1 #define PHY_RICTRL_BSEL_POS 1 #define PHY_RICTRL_BSEL_LEN 1 #define PHY_RICTRL_BSEL_MSK 0x2 #define PHY_RICTRL_BSEL_EN 0x2 #define PHY_RICTRL_MODE_POS 2 #define PHY_RICTRL_MODE_LEN 1 #define PHY_RICTRL_MODE_MSK 0x4 #define PHY_RICTRL_MODE_EN 0x4 #define PHY_RICTRL_RXSI_POS 3 #define PHY_RICTRL_RXSI_LEN 1 #define PHY_RICTRL_RXSI_MSK 0x8 #define PHY_RICTRL_RXSI_EN 0x8 #define PHY_RICTRL_TXSI_POS 4 #define PHY_RICTRL_TXSI_LEN 1 #define PHY_RICTRL_TXSI_MSK 0x10 #define PHY_RICTRL_TXSI_EN 0x10 #define PHY_RICTRL_CAL_POS 5 #define PHY_RICTRL_CAL_LEN 1 #define PHY_RICTRL_CAL_MSK 0x20 #define PHY_RICTRL_CAL_EN 0x20 #define PHY_RICTRL_TXBYP_POS 6 #define PHY_RICTRL_TXBYP_LEN 1 #define PHY_RICTRL_TXBYP_MSK 0x40 #define PHY_RICTRL_TXBYP_EN 0x40 #define PHY_RICTRL_RST_POS 7 #define PHY_RICTRL_RST_LEN 1 #define PHY_RICTRL_RST_MSK 0x80 #define PHY_RICTRL_RST_EN 0x80 #define PHY_RICTRL_LBM_POS 8 #define PHY_RICTRL_LBM_LEN 1 #define PHY_RICTRL_LBM_MSK 0x100 #define PHY_RICTRL_LBM_EN 0x100 #define PHY_RICTRL_RXFON_POS 9 #define PHY_RICTRL_RXFON_LEN 1 #define PHY_RICTRL_RXFON_MSK 0x200 #define PHY_RICTRL_RXFON_EN 0x200 #define PHY_RICTRL_TXFON_POS 10 #define PHY_RICTRL_TXFON_LEN 1 #define PHY_RICTRL_TXFON_MSK 0x400 #define PHY_RICTRL_TXFON_EN 0x400 #define PHY_RICTRL_AUXADCEN_POS 11 #define PHY_RICTRL_AUXADCEN_LEN 1 #define PHY_RICTRL_AUXADCEN_MSK 0x800 #define PHY_RICTRL_AUXADCEN_EN 0x800 #define PHY_RICTRL_RXSWCTRLEN_POS 12 #define PHY_RICTRL_RXSWCTRLEN_LEN 1 #define PHY_RICTRL_RXSWCTRLEN_MSK 0x1000 #define PHY_RICTRL_RXSWCTRLEN_EN 0x1000 #define PHY_RICTRL_RXEND_POS 13 #define PHY_RICTRL_RXEND_LEN 1 #define PHY_RICTRL_RXEND_MSK 0x2000 #define PHY_RICTRL_RXEND_EN 0x2000 #define PHY_RICTRL_RXDCSI_POS 14 #define PHY_RICTRL_RXDCSI_LEN 1 #define PHY_RICTRL_RXDCSI_MSK 0x4000 #define PHY_RICTRL_RXDCSI_EN 0x4000 #define PHY_RICTRL_RXRFEN_POS 15 #define PHY_RICTRL_RXRFEN_LEN 1 #define PHY_RICTRL_RXRFEN_MSK 0x8000 #define PHY_RICTRL_RXRFEN_EN 0x8000 #define PHY_RICTRL_TXRFEN_POS 16 #define PHY_RICTRL_TXRFEN_LEN 1 #define PHY_RICTRL_TXRFEN_MSK 0x10000 #define PHY_RICTRL_TXRFEN_EN 0x10000 #define PHY_RICTRL_RXONAIR_POS 17 #define PHY_RICTRL_RXONAIR_LEN 1 #define PHY_RICTRL_RXONAIR_MSK 0x20000 #define PHY_RICTRL_RXONAIR_EN 0x20000 #define PHY_RICTRL_SEL_RXRFEN_POS 18 #define PHY_RICTRL_SEL_RXRFEN_LEN 2 #define PHY_RICTRL_SEL_RXRFEN_MSK 0xc0000 #define PHY_RICTRL_SEL_TXRFEN_POS 20 #define PHY_RICTRL_SEL_TXRFEN_LEN 2 #define PHY_RICTRL_SEL_TXRFEN_MSK 0x300000 #define PHY_RICTRL_SEL_RXONAIR_POS 22 #define PHY_RICTRL_SEL_RXONAIR_LEN 2 #define PHY_RICTRL_SEL_RXONAIR_MSK 0xc00000 #define PHY_RICTRL_TXPOWER_POS 24 #define PHY_RICTRL_TXPOWER_LEN 4 #define PHY_RICTRL_TXPOWER_MSK 0xf000000 #define PHY_RICTRL_SEL_TXPOWER_POS 28 #define PHY_RICTRL_SEL_TXPOWER_LEN 1 #define PHY_RICTRL_SEL_TXPOWER_MSK 0x10000000 #define PHY_RICTRL_SEL_TXPOWER_EN 0x10000000 #define PHY_RICTRL_DCO_LOWTRKDIS_POS 29 #define PHY_RICTRL_DCO_LOWTRKDIS_LEN 3 #define PHY_RICTRL_DCO_LOWTRKDIS_MSK 0xe0000000 #define PHY_RICTRL_CONFIG_4_RX_CIC__FIFO_ENABLED 0x00088200 #define PHY_RICTRL_CONFIG_4_TX_FIFO_ENABLED 0x00110400 #define PHY_RICTRL_CONFIG_4_TXRX_FIFO_ENABLED 0x00198600 #define PHY_RICTRL_CONFIG_ABB8000_BBDIG_DEFAULFT 0x00A000A0 #define PHY_RICTRL_CONFIG_ABB8000_BBDIG_DEFAULFT6 0x00A00190 #define PHY_RICTRL_CONFIG_ABB8000_BBDIG_FIFOS_DISABLED 0x00000000 /* This is automatically generated description for register: RIRXAGC */ #define PHY_RIRXAGC_AGCLPF2_POS 0 #define PHY_RIRXAGC_AGCLPF2_LEN 2 #define PHY_RIRXAGC_AGCLPF2_MSK 0x3 #define PHY_RIRXAGC_LPF1_POS 2 #define PHY_RIRXAGC_LPF1_LEN 2 #define PHY_RIRXAGC_LPF1_MSK 0xc #define PHY_RIRXAGC_PMA_POS 4 #define PHY_RIRXAGC_PMA_LEN 1 #define PHY_RIRXAGC_PMA_MSK 0x10 #define PHY_RIRXAGC_PMA_EN 0x10 #define PHY_RIRXAGC_LNA_POS 5 #define PHY_RIRXAGC_LNA_LEN 1 #define PHY_RIRXAGC_LNA_MSK 0x20 #define PHY_RIRXAGC_LNA_EN 0x20 #define PHY_RIRXAGC_OVRD_POS 6 #define PHY_RIRXAGC_OVRD_LEN 1 #define PHY_RIRXAGC_OVRD_MSK 0x40 #define PHY_RIRXAGC_OVRD_EN 0x40 #define PHY_RIRXAGC_APBSEL_RXAGCVALID_POS 7 #define PHY_RIRXAGC_APBSEL_RXAGCVALID_LEN 1 #define PHY_RIRXAGC_APBSEL_RXAGCVALID_MSK 0x80 #define PHY_RIRXAGC_APBSEL_RXAGCVALID_EN 0x80 #define PHY_RIRXAGC_APB_RXAGCVALID_POS 8 #define PHY_RIRXAGC_APB_RXAGCVALID_LEN 24 #define PHY_RIRXAGC_APB_RXAGCVALID_MSK 0xffffff00 #define PHY_RIRXAGC_CONFIG_DEFAULT3 0x0000005A #endif //__PHY_REGS_H__