/*
 * Copyright (c) 2022, Artinchip Technology Co., Ltd
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef _AIC_HAL_QSPI_
#define _AIC_HAL_QSPI_
#include <aic_common.h>
#include <stdbool.h>

#ifdef __cplusplus
extern "C" {
#endif

#define HAL_QSPI_INVALID             (0xFFFFFFFF)
#define HAL_QSPI_BUS_WIDTH_SINGLE    1
#define HAL_QSPI_BUS_WIDTH_DUAL      2
#define HAL_QSPI_BUS_WIDTH_QUAD      4
#define HAL_QSPI_MAX_FREQ_HZ         133000000
#define HAL_QSPI_MIN_FREQ_HZ         3000
#define HAL_QSPI_CPOL_ACTIVE_HIGH    0
#define HAL_QSPI_CPOL_ACTIVE_LOW     1
#define HAL_QSPI_CPHA_FIRST_EDGE     0
#define HAL_QSPI_CPHA_SECOND_EDGE    1
#define HAL_QSPI_CS_POL_VALID_HIGH   0
#define HAL_QSPI_CS_POL_VALID_LOW    1

struct qspi_master_state;
typedef struct qspi_master_state qspi_master_handle;
typedef void (*qspi_master_async_cb)(qspi_master_handle *h, void *priv);

struct qspi_master_config {
    u32 idx;
    u32 clk_in_hz;
    u32 clk_id;
    bool bit_mode;
    bool wire3_en;
    bool lsb_en;
    bool cs_auto;
    u8 cs_polarity;
    u8 cpol;
    u8 cpha;
};

struct qspi_master_dma_config {
    u32 port_id;
    u32 tx_bus_width;
    u32 tx_max_burst;
    u32 rx_bus_width;
    u32 rx_max_burst;
};

struct qspi_transfer {
    u8 *tx_data;
    u8 *rx_data;
    u32 data_len;
};

#define HAL_QSPI_STATUS_OK           (0)
#define HAL_QSPI_STATUS_IN_PROGRESS  (0x1UL << 0)
#define HAL_QSPI_STATUS_RX_UNDER_RUN (0x1UL << 1)
#define HAL_QSPI_STATUS_RX_OVER_FLOW (0x1UL << 2)
#define HAL_QSPI_STATUS_TX_UNDER_RUN (0x1UL << 3)
#define HAL_QSPI_STATUS_TX_OVER_FLOW (0x1UL << 4)
/*
 * HAL QSPI internal state, HAL user should not modify it directly
 */
struct qspi_master_state {
    u32 idx;
    qspi_master_async_cb cb;
    void *cb_priv;
    u32 status;
    u32 clk_id;
    u32 bus_hz;
    u32 bus_width;
    struct qspi_master_dma_config dma_cfg;
    void *dma_tx;
    void *dma_rx;
    u8 *async_tx; /* Used in Async Non-DMA mode */
    u8 *async_rx; /* Used in Async Non-DMA mode */
    u32 async_tx_remain; /* Used in Async Non-DMA mode */
    u32 async_rx_remain; /* Used in Async Non-DMA mode */
    u32 work_mode;
    u32 done_mask;
};

int hal_qspi_master_init(qspi_master_handle *h, struct qspi_master_config *cfg);
int hal_qspi_master_deinit(qspi_master_handle *h);
int hal_qspi_master_set_cs(qspi_master_handle *h, u32 cs_num, bool enable);
int hal_qspi_master_set_bus_freq(qspi_master_handle *h, u32 bus_hz);
int hal_qspi_master_set_bus_width(qspi_master_handle *h, u32 bus_width);
int hal_qspi_master_transfer_sync(qspi_master_handle *h, struct qspi_transfer *t);
int hal_qspi_master_dma_config(qspi_master_handle *h, struct qspi_master_dma_config *cfg);
int hal_qspi_master_register_cb(qspi_master_handle *h, qspi_master_async_cb cb, void *priv);
int hal_qspi_master_transfer_async(qspi_master_handle *h, struct qspi_transfer *t);
int hal_qspi_master_get_status(qspi_master_handle *h);
void hal_qspi_master_irq_handler(qspi_master_handle *h);

#ifdef __cplusplus
}
#endif

#endif