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67 lines
1.5 KiB
C
67 lines
1.5 KiB
C
/*
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* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <aic_core.h>
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#include <aic_hal.h>
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#define align_cache_line(addr, len, a, l) \
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unsigned long a = (unsigned long)addr; \
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unsigned long l = (unsigned long)len; \
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if (addr % CACHE_LINE_SIZE) { \
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a -= (addr % CACHE_LINE_SIZE); \
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l += (addr % CACHE_LINE_SIZE); \
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} \
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if (l % CACHE_LINE_SIZE) { \
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l += CACHE_LINE_SIZE - (l % CACHE_LINE_SIZE); \
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}
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void aicmac_low_level_init(uint32_t port, bool en)
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{
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uint32_t id = CLK_GMAC0 + port;
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/* pin-mux */
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/* mac clock */
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if (en) {
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/* Set clock frequence = 50M */
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hal_clk_set_freq(id, 50000000);
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/* clock enable & reset deassert */
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hal_clk_enable_deassertrst_iter(id);
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} else {
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/* clock enable & reset deassert */
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hal_clk_disable_assertrst(id);
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}
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}
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void aicmac_dcache_clean(uintptr_t addr, uint32_t len)
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{
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#ifndef CONFIG_MAC_USE_UNCACHE_BUF
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align_cache_line(addr, len, a, l);
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aicos_dcache_clean_range((unsigned long *)a, (int64_t)l);
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#endif
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}
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void aicmac_dcache_invalid(uintptr_t addr, uint32_t len)
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{
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#ifndef CONFIG_MAC_USE_UNCACHE_BUF
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align_cache_line(addr, len, a, l);
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aicos_dcache_invalid_range((unsigned long *)a, (int64_t)l);
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#endif
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}
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void aicmac_dcache_clean_invalid(uintptr_t addr, uint32_t len)
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{
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#ifndef CONFIG_MAC_USE_UNCACHE_BUF
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align_cache_line(addr, len, a, l);
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aicos_dcache_clean_invalid_range((unsigned long *)a, (int64_t)l);
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#endif
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}
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void aicmac_gdma_sync(void)
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{
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aicos_dma_sync();
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}
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