mirror of
https://gitee.com/Vancouver2017/luban-lite.git
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137 lines
3.5 KiB
C
137 lines
3.5 KiB
C
/*
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* Copyright (c) 2024, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: Xuan.Wen <xuan.wen@artinchip.com>
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*/
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#include <string.h>
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#include <finsh.h>
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#include <rtdevice.h>
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#include <aic_core.h>
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#include <drv_qspi.h>
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#include "test_spislave.h"
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struct bus_cfg {
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u8 cmd; /* CMD bus width */
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u8 addr; /* Address bus width */
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u8 dmycyc; /* Dummy clock cycle */
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u8 data; /* Data bus width */
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};
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extern void slave_dump_data(char *msg, u8 *buf, u32 len);
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void master_tx(struct rt_qspi_device *qspi, u8 bus_width, u8 *buf, u32 datalen)
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{
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struct rt_qspi_message msg;
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struct bus_cfg cfg;
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rt_size_t ret;
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cfg.cmd = 0;
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cfg.addr = 0;
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cfg.dmycyc = 0;
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cfg.data = bus_width;
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rt_memset(&msg, 0, sizeof(msg));
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msg.qspi_data_lines = cfg.data;
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msg.parent.recv_buf = NULL;
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msg.parent.send_buf = buf;
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msg.parent.length = datalen;
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msg.parent.cs_take = 1;
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msg.parent.cs_release = 1;
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rt_spi_take_bus((struct rt_spi_device *)qspi);
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ret = rt_qspi_transfer_message(qspi, &msg);
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if (ret != datalen) {
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printf("master tx failed. ret 0x%x\n", ret);
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}
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rt_spi_release_bus((struct rt_spi_device *)qspi);
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}
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void master_rx(struct rt_qspi_device *qspi, u8 bus_width, u8 *buf, u32 datalen)
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{
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struct rt_qspi_message msg;
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struct bus_cfg cfg;
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rt_size_t ret;
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cfg.cmd = 0;
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cfg.addr = 0;
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cfg.dmycyc = 0;
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cfg.data = bus_width;
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rt_memset(&msg, 0, sizeof(msg));
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msg.qspi_data_lines = cfg.data;
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msg.parent.recv_buf = buf;
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msg.parent.send_buf = NULL;
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msg.parent.length = datalen;
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msg.parent.cs_take = 1;
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msg.parent.cs_release = 1;
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rt_spi_take_bus((struct rt_spi_device *)qspi);
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ret = rt_qspi_transfer_message(qspi, &msg);
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if (ret != datalen) {
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printf("master tx failed. ret 0x%x\n", ret);
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}
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rt_spi_release_bus((struct rt_spi_device *)qspi);
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}
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static void slave_get_status(struct rt_qspi_device *qspi, u8 bus_width, u8 *buf,
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u32 datalen)
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{
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master_rx(qspi, bus_width, buf, datalen);
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}
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void slave_write(struct rt_qspi_device *qspi, u8 bus_width, u8 *buf, u32 datalen, u32 addr)
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{
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u8 *work_buf;
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u32 status;
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work_buf = aicos_malloc_align(0, datalen + 4, CACHE_LINE_SIZE);
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work_buf[0] = MEM_CMD_WRITE;
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memcpy(&work_buf[1], &addr, 3);
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memcpy(&work_buf[4], buf, datalen);
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master_tx(qspi, bus_width, work_buf, datalen + 4);
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rt_thread_mdelay(10);
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do {
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status = 0;
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slave_get_status(qspi, bus_width, (void *)&status, 4);
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printf("write status 0x%x\n", status);
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rt_thread_mdelay(1000);
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} while (status != WRITE_STATUS_VAL);
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aicos_free_align(0, work_buf);
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}
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static void slave_load_data(struct rt_qspi_device *qspi, u8 bus_width, u32 addr)
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{
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u8 work_buf[4];
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work_buf[0] = MEM_CMD_LOAD;
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memcpy(&work_buf[1], &addr, 3);
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master_tx(qspi, bus_width, work_buf, 4);
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}
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static void slave_read_data(struct rt_qspi_device *qspi, u8 bus_width,
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u8 *buf, u32 datalen)
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{
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master_rx(qspi, bus_width, buf, datalen);
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}
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void slave_read(struct rt_qspi_device *qspi, u8 bus_width, u8 *buf, u32 datalen,
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u32 addr)
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{
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u32 status;
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slave_load_data(qspi, bus_width, addr);
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rt_thread_mdelay(100);
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do {
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status = 0;
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slave_get_status(qspi, bus_width, (void *)&status, 4);
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printf("load status 0x%x\n", status);
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rt_thread_mdelay(1000);
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} while (status != LOAD_STATUS_VAL);
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slave_read_data(qspi, bus_width, buf, datalen);
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}
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