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368 lines
11 KiB
C
368 lines
11 KiB
C
/**
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****************************************************************************************
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*
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* @file ipc_shared.h
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*
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* @brief Shared data between both IPC modules.
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*
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* Copyright (C) ASR 2011-2016
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*
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****************************************************************************************
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*/
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#ifndef _IPC_SHARED_H_
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#define _IPC_SHARED_H_
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/**
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****************************************************************************************
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* @defgroup IPC IPC
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* @ingroup PLATFORM_DRIVERS
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* @brief Inter Processor Communication module.
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*
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* The IPC module implements the protocol to communicate between the Host CPU
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* and the Embedded CPU.
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*
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* A typical use case of the IPC Tx path API:
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* @msc
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* hscale = "2";
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*
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* a [label=Driver],
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* b [label="IPC host"],
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* c [label="IPC emb"],
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* d [label=Firmware];
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*
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* --- [label="Tx descriptor queue example"];
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* a=>a [label="Driver receives a Tx packet from OS"];
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* a=>b [label="ipc_host_txdesc_get()"];
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* a<<b [label="struct txdesc_host *"];
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* a=>a [label="Driver fill the descriptor"];
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* a=>b [label="ipc_host_txdesc_push()"];
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* ... [label="(several Tx desc can be pushed)"];
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* b:>c [label="Tx desc queue filled IRQ"];
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* c=>>d [label="IPC emb Tx desc callback"];
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* ... [label="(several Tx desc can be popped)"];
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* d=>d [label="Packets are sent or discarded"];
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* --- [label="Tx confirm queue example"];
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* c<=d [label="ipc_emb_txcfm_push()"];
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* c>>d [label="Request accepted"];
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* ... [label="(several Tx cfm can be pushed)"];
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* b<:c [label="Tx cfm queue filled IRQ"];
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* a<<=b [label="Driver's Tx Confirm callback"];
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* a=>b [label="ipc_host_txcfm_pop()"];
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* a<<b [label="struct ipc_txcfm"];
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* a<=a [label="Packets are freed by the driver"];
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* @endmsc
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*
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* A typical use case of the IPC Rx path API:
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* @msc
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* hscale = "2";
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*
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* a [label=Firmware],
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* b [label="IPC emb"],
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* c [label="IPC host"],
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* d [label=Driver];
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*
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* --- [label="Rx buffer and desc queues usage example"];
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* d=>c [label="ipc_host_rxbuf_push()"];
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* d=>c [label="ipc_host_rxbuf_push()"];
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* d=>c [label="ipc_host_rxbuf_push()"];
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* ... [label="(several Rx buffer are pushed)"];
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* a=>a [label=" Frame is received\n from the medium"];
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* a<<b [label="struct ipc_rxbuf"];
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* a=>a [label=" Firmware fill the buffer\n with received frame"];
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* a<<b [label="Push accepted"];
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* ... [label="(several Rx desc can be pushed)"];
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* b:>c [label="Rx desc queue filled IRQ"];
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* c=>>d [label="Driver Rx packet callback"];
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* c<=d [label="ipc_host_rxdesc_pop()"];
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* d=>d [label="Rx packet is handed \nover to the OS "];
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* ... [label="(several Rx desc can be poped)"];
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* --- [label="Rx buffer request exemple"];
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* b:>c [label="Low Rx buffer count IRQ"];
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* a<<b [label="struct ipc_rxbuf"];
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* c=>>d [label="Driver Rx buffer callback"];
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* d=>c [label="ipc_host_rxbuf_push()"];
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* d=>c [label="ipc_host_rxbuf_push()"];
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* d=>c [label="ipc_host_rxbuf_push()"];
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* ... [label="(several Rx buffer are pushed)"];
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* @endmsc
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*
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* @{
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****************************************************************************************
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*/
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/*
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* INCLUDE FILES
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****************************************************************************************
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*/
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//#include "co_int.h"
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//#include "dma.h"
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#include "asr_config.h"
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/*
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* DEFINES AND MACROS
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****************************************************************************************
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*/
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/// Number of IPC TX queues
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#define IPC_TXQUEUE_CNT NX_TXQ_CNT
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#define IPC_RXDESC_CNT 15
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//but when wrap exceed the maximum index 15, then 6 is the maximum rx_aggr_max_num, as port index 0 and 1 is reversed for log and msg
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//
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#define RX_AGGR_BUF_NUM 8 // 6
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/*
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* Number of Host buffers available for Data Rx handling
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*/
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#ifdef SDIO_DEAGGR
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#define IPC_RXBUF_CNT 1 //
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#else
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#define IPC_RXBUF_CNT 5 // 7 // 8 // 8*6
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#endif
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/*
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* RX Data buffers size (in bytes) need adjust
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*/
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#define IPC_RXBUF_SIZE ASR_ALIGN_BLKSZ_HI(1696)*(RX_AGGR_BUF_NUM) //13568 //1696*8
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#define IPC_RXMSGBUF_CNT 2
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#define IPC_RXMSGBUF_SIZE ASR_ALIGN_BLKSZ_HI(1696)
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/*
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* Number of Host buffers available for Data Rx handling
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*/
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#define IPC_RXBUF_CNT_SPLIT 1
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/*
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* RX Data buffers size (in bytes) need adjust
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*/
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#define IPC_RXBUF_SIZE_SPLIT (WLAN_AMSDU_RX_LEN)
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#define IPC_HIF_TXBUF_SIZE ASR_ALIGN_BLKSZ_HI(13568) //1696*8
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#ifdef SDIO_DEAGGR
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#define IPC_RXBUF_CNT_SDIO_DEAGG (30) // (26) // (26)
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#define IPC_RXBUF_SIZE_SDIO_DEAGG (1696)
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#endif
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/// Number of Host buffers available for Emb->App MSGs sending (through DMA)
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#define IPC_MSGE2A_BUF_CNT 5 //64
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/// Length used in APP2EMB MSGs structures
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#define IPC_A2E_MSG_BUF_SIZE 127 // size in 4-byte words
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/// Length used in EMB2APP MSGs structures
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#define IPC_E2A_MSG_PARAM_SIZE 256 // size in 4-byte words
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/// Length for dbg log
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#define IPC_DBG_PARAM_SIZE 512
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/**
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* Define used for MSG buffers validity.
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* This value will be written only when a MSG buffer is used for sending from Emb to App.
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*/
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#define IPC_MSGE2A_VALID_PATTERN 0xADDEDE2A
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#ifndef __packed
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#define __packed __attribute__ ((__packed__)) __attribute__((aligned(1)))
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#endif
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/// Message structure for MSGs from Emb to App
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struct ipc_e2a_msg
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{
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uint16_t id; ///< Message id.
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uint16_t dummy_dest_id; ///< Not used
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uint16_t dummy_src_id; ///< Not used
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uint16_t param_len; ///< Parameter embedded struct length.
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uint32_t param[IPC_E2A_MSG_PARAM_SIZE]; ///< Parameter embedded struct. Must be word-aligned.
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};
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/// Message structure for Debug messages from Emb to App
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struct ipc_dbg_msg
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{
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uint16_t id;
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uint8_t string[IPC_DBG_PARAM_SIZE]; ///< Debug string
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};
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/// Message structure for MSGs from App to Emb.
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/// Actually a sub-structure will be used when filling the messages.
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struct ipc_a2e_msg
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{
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uint32_t dummy_word; ///< used to cope with kernel message structure
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uint32_t msg[IPC_A2E_MSG_BUF_SIZE]; ///< body of the msg
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};
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struct ipc_ooo_rxdesc_buf_hdr
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{
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uint16_t id;
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//#ifdef CONFIG_ASR_SDIO
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uint16_t sdio_rx_len;
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//#endif
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uint8_t rxu_stat_desc_cnt;
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/*The rxu_stat_val start here. */
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} __packed;
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/// RX status value structure (as expected by Upper Layers)
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struct rxu_stat_val
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{
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// out-of-order value.
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//struct rxu_cntrl_ooo_val ooo_val;
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// use (sta_idx/tid/seq_num/fn_num) to identify one out-of-order pkt.
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uint8_t sta_idx;
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uint8_t tid;
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uint16_t seq_num;
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uint16_t amsdu_fn_num;
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/// Status (@ref rx_status_bits)
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uint8_t status;
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} __packed;
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/// Information provided by host to indentify RX buffer
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struct ipc_shared_rx_buf
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{
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/// ptr to hostbuf client (ipc_host client) structure
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volatile uint32_t hostid;
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/// ptr to real hostbuf dma address
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volatile uint32_t dma_addr;
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};
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/// Information provided by host to indentify RX desc
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struct ipc_shared_rx_desc
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{
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/// DMA Address
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volatile uint32_t dma_addr;
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};
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/*
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* TYPE and STRUCT DEFINITIONS
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****************************************************************************************
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*/
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/// Descriptor filled by the Host
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struct hostdesc
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{
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// tx len filled by host when use tx aggregation mode
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uint16_t sdio_tx_len;
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// tx total len: used for host
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uint16_t sdio_tx_total_len;
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// queue id
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uint8_t queue_idx; //VO VI BE BK
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/// Pointer to packet payload
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uint8_t packet_offset;
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/// Size of the payload
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uint16_t packet_len;
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/// Packet TID
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uint8_t tid;
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/// VIF index
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uint8_t vif_idx;
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/// Station Id (0xFF if station is unknown)
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uint8_t staid;
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// agg_num
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uint8_t agg_num;
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/// TX flags
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uint16_t flags;
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/// Timestamp of first transmission of this MPDU
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uint16_t timestamp;
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/// address of buffer from hostdesc in fw
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uint32_t packet_addr;
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/// PN that was used for first transmission of this MPDU
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uint32_t txq;
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uint32_t reserved;
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/// Sequence Number used for first transmission of this MPDU
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uint16_t sn;
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/// Ethernet Type
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uint16_t ethertype;
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/// Destination Address
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struct mac_addr eth_dest_addr;
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/// Source Address
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struct mac_addr eth_src_addr;
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};
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/// Description of the TX API
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struct txdesc_api
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{
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/// Information provided by Host
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struct hostdesc host;
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};
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/// Descriptor used for Host/Emb TX frame information exchange
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struct txdesc_host
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{
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/// Flag indicating if the TX descriptor is ready (different from 0) or not (equal to 0)
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uint32_t ready;
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/// API of the embedded part
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struct txdesc_api api;
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};
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// Indexes are defined in the MIB shared structure
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/// Structure describing the IPC data shared with the host CPU
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struct ipc_shared_env_tag
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{
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/// Room for MSG to be sent from App to Emb
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volatile struct ipc_a2e_msg msg_a2e_buf;
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/// Room to build the Emb->App MSGs Xferred
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volatile struct ipc_e2a_msg msg_e2a_buf;
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/// DMA descriptor for Emb->App MSGs Xfers
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//volatile struct dma_desc msg_dma_desc;
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/// Host buffer addresses for Emb->App MSGs DMA Xfers
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//volatile uint32_t msg_e2a_hostbuf_addr [IPC_MSGE2A_BUF_CNT];
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#if NX_DEBUG_DUMP
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/// Host buffer address for the debug dump information
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volatile uint32_t la_dbginfo_addr;
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#endif
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/// Host buffer address for the TX payload descriptor pattern
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volatile uint32_t pattern_addr;
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/// Array of TX descriptors for the BK queue
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volatile struct txdesc_host txdesc0[RW_USER_MAX][NX_TXDESC_CNT0];
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/// Array of TX descriptors for the BE queue
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volatile struct txdesc_host txdesc1[RW_USER_MAX][NX_TXDESC_CNT1];
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/// Array of TX descriptors for the VI queue
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volatile struct txdesc_host txdesc2[RW_USER_MAX][NX_TXDESC_CNT2];
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/// Array of TX descriptors for the VO queue
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volatile struct txdesc_host txdesc3[RW_USER_MAX][NX_TXDESC_CNT3];
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/// Array of TX descriptors for the BC/MC queue
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volatile struct txdesc_host txdesc4[1][NX_TXDESC_CNT4];
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/// RX Descriptors Array
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volatile struct ipc_shared_rx_desc host_rxdesc[IPC_RXDESC_CNT];
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/// RX Buffers Array
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volatile struct ipc_shared_rx_buf host_rxbuf[IPC_RXBUF_CNT];
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#if NX_TRACE
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/// Pattern for host to check if trace is initialized
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volatile uint16_t trace_pattern;
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/// Index (in 16bits word) of the first trace within the trace buffer
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volatile uint32_t trace_start;
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/// Index (in 16bits word) of the last trace within the trace buffer
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volatile uint32_t trace_end;
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/// Size (in 16bits word) of the trace buffer
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volatile uint32_t trace_size;
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/// Offset (in bytes) from here to the start of the trace buffer
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volatile uint32_t trace_offset;
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#endif
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};
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/// IPC Shared environment
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//extern struct ipc_shared_env_tag ipc_shared_env;
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/*
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* TYPE and STRUCT DEFINITIONS
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****************************************************************************************
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*/
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#endif // _IPC_SHARED_H_
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