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200 lines
7.2 KiB
C
200 lines
7.2 KiB
C
/*
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* Copyright (c) 2024-2025, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: jiji.chen <jiji.chen@artinchip.com>
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*/
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#ifndef _AIC_HAL_SYSCFG_REGS_H_
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#define _AIC_HAL_SYSCFG_REGS_H_
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#include <aic_common.h>
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#include <aic_soc.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* The register definition of SYSCFG V12 */
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#define LDO25_CFG (SYSCFG_BASE + 0x020)
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#define LDO18_CFG (SYSCFG_BASE + 0x024)
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#define LDO1x_CFG (SYSCFG_BASE + 0x028)
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#define ATB_CFG (SYSCFG_BASE + 0x070)
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#define PSEN_CFG (SYSCFG_BASE + 0x0C0)
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#define PSEN_CNT_VAL (SYSCFG_BASE + 0x0C4)
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#define SYS_SRAM_PAR (SYSCFG_BASE + 0x100)
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#define CPU_SRAM_PAR (SYSCFG_BASE + 0x104)
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#define VE_SRAM_PAR (SYSCFG_BASE + 0x10C)
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#define GE_SRAM_PAR (SYSCFG_BASE + 0x110)
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#define DE_SRAM_PAR (SYSCFG_BASE + 0x114)
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#define SRAM_CLK_CFG (SYSCFG_BASE + 0x140)
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#define VE_SRAM_MAP (SYSCFG_BASE + 0x164)
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#define FLASH_CFG (SYSCFG_BASE + 0x1F0)
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#define SYSCFG_VER (SYSCFG_BASE + 0xFFC)
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/* The field definition of LDO25_CFG */
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#define LDO25_CFG_ATB_ANA_EN BIT(27)
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#define LDO25_CFG_ATB_ANA_SEL_MASK GENMASK(26, 24)
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#define LDO25_CFG_ATB_ANA_SEL_SHIFT (24)
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#define LDO25_CFG_ATB_BIAS_SEL_MASK GENMASK(21, 20)
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#define LDO25_CFG_ATB_BIAS_SEL_SHIFT (20)
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#define LDO25_CFG_RESEVER_IBIAS_EN BIT(18)
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#define LDO25_CFG_XSPI_DLLC1_IBIAS_EN BIT(17)
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#define LDO25_CFG_XSPI_DLLC0_IBIAS_EN BIT(16)
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#define LDO25_CFG_BG_CTRL_MASK GENMASK(15, 8)
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#define LDO25_CFG_BG_CTRL_SHIFT (8)
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#define LDO25_CFG_LDO25_EN BIT(4)
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#define LDO25_CFG_LDO25_VAL_MASK GENMASK(2, 0)
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#define LDO25_CFG_LDO25_VAL_SHIFT (0)
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/* The field definition of LDO18_CFG */
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#define LDO18_CFG_LDO18_PD_FAST BIT(5)
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#define LDO18_CFG_LDO18_EN BIT(4)
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#define LDO18_CFG_LDO18_VAL_MASK GENMASK(2, 0)
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#define LDO18_CFG_LDO18_VAL_SHIFT (0)
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/* The field definition of LDO1x_CFG */
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#define LDO1x_CFG_LDO1X_SOFT_EN BIT(6)
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#define LDO1x_CFG_LDO1X_PD_FAST BIT(5)
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#define LDO1x_CFG_LDO1X_EN BIT(4)
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#define LDO1x_CFG_LDO1X_VAL_MASK GENMASK(3, 0)
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#define LDO1x_CFG_LDO1X_VAL_SHIFT (0)
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/* The field definition of ATB_CFG */
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#define ATB_CFG_ATB3_SEL_MASK GENMASK(26, 25)
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#define ATB_CFG_ATB3_SEL_SHIFT (25)
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#define ATB_CFG_ATB3_OUT_EN BIT(24)
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#define ATB_CFG_ATB2_SEL_MASK GENMASK(18, 17)
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#define ATB_CFG_ATB2_SEL_SHIFT (17)
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#define ATB_CFG_ATB2_OUT_EN BIT(16)
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#define ATB_CFG_ATB1_SEL_MASK GENMASK(10, 9)
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#define ATB_CFG_ATB1_SEL_SHIFT (9)
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#define ATB_CFG_ATB1_OUT_EN BIT(8)
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#define ATB_CFG_ATB0_SEL_MASK GENMASK(3, 1)
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#define ATB_CFG_ATB0_SEL_SHIFT (1)
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#define ATB_CFG_ATB0_OUT_EN BIT(0)
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/* The field definition of PSEN_CFG */
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#define PSEN_CFG_CNT_TIME_MASK GENMASK(31, 16)
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#define PSEN_CFG_CNT_TIME_SHIFT (16)
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#define PSEN_CFG_RO_SEL_MASK GENMASK(3, 1)
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#define PSEN_CFG_RO_SEL_SHIFT (1)
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#define PSEN_CFG_PSEN_START BIT(0)
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/* The field definition of PSEN_CNT_VAL */
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#define PSEN_CNT_VAL_CNT_VAL_MASK GENMASK(15, 0)
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#define PSEN_CNT_VAL_CNT_VAL_SHIFT (0)
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/* The field definition of SYS_SRAM_PAR */
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#define SYS_SRAM_PAR_SRAM_PAR_MASK GENMASK(23, 0)
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#define SYS_SRAM_PAR_SRAM_PAR_SHIFT (0)
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/* The field definition of CPU_SRAM_PAR */
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#define CPU_SRAM_PAR_SRAM_PAR_MASK1 GENMASK(23, 16)
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#define CPU_SRAM_PAR_SRAM_PAR_SHIFT1 (16)
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#define CPU_SRAM_PAR_SRAM_PAR_MASK0 GENMASK(7, 0)
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#define CPU_SRAM_PAR_SRAM_PAR_SHIFT0 (0)
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/* The field definition of VE_SRAM_PAR */
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#define VE_SRAM_PAR_SRAM_PAR_MASK GENMASK(15, 0)
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#define VE_SRAM_PAR_SRAM_PAR_SHIFT (0)
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/* The field definition of GE_SRAM_PAR */
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#define GE_SRAM_PAR_SRAM_PAR_MASK GENMASK(15, 0)
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#define GE_SRAM_PAR_SRAM_PAR_SHIFT (0)
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/* The field definition of DE_SRAM_PAR */
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#define DE_SRAM_PAR_SRAM_PAR_MASK GENMASK(15, 0)
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#define DE_SRAM_PAR_SRAM_PAR_SHIFT (0)
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/* The field definition of SRAM_CLK_CFG */
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#define SRAM_CLK_CFG_SRAM_CLK_UNGATE_MASK GENMASK(18, 0)
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#define SRAM_CLK_CFG_SRAM_CLK_UNGATE_SHIFT (0)
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/* The field definition of VE_SRAM_MAP */
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#define VE_SRAM_MAP_SRAM BIT(0)
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/* The field definition of FLASH_CFG */
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#define FLASH_CFG_FLASH_IOMAP_012_MASK GENMASK(14, 12)
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#define FLASH_CFG_FLASH_IOMAP_012_SHIFT (12)
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#define FLASH_CFG_FLASH_IOMAP_345_MASK GENMASK(10, 8)
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#define FLASH_CFG_FLASH_IOMAP_345_SHIFT (8)
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#define FLASH_CFG_FLASH_SRCSEL_MASK GENMASK(1, 0)
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#define FLASH_CFG_FLASH_SRCSEL_SHIFT (0)
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#define FLASH_CFG_FLASH_SRCSEL_VAL(v) (((v) << FLASH_CFG_FLASH_SRCSEL_SHIFT) & FLASH_CFG_FLASH_SRCSEL_MASK)
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/* The field definition of SYSCFG_VER */
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#define SYSCFG_VER_VERSION_MASK GENMASK(31, 0)
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#define SYSCFG_VER_VERSION_SHIFT (0)
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#define IOMAP_EFUSE_WID 7
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#define EFUSE_DATA_IOMAP_POS 8
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#define REFERENCE_VOLTAGE 24000
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#define VOLTAGE_SPACING 1000
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static inline u32 syscfg_hw_read_ldo_cfg(void)
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{
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u32 ldo25_val;
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ldo25_val = readl(LDO25_CFG);
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ldo25_val &= LDO25_CFG_LDO25_VAL_MASK;
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return ldo25_val * VOLTAGE_SPACING + REFERENCE_VOLTAGE;
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}
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static inline void syscfg_hw_ldo1x_enable(u8 v_level)
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{
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u32 val = 0;
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/*SD suggest: set the LDO1X_CFG_LDO1X_PD_FAST_SHIFT to 0, other bit not use.*/
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val |= (v_level & LDO1x_CFG_LDO1X_VAL_MASK);
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writel(val, LDO1x_CFG);
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}
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static inline void syscfg_hw_ldo1x_disable()
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{
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u32 val = 0;
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val = readl(LDO1x_CFG);
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val &= LDO1x_CFG_LDO1X_VAL_MASK;
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/*BIT4, BIT5, BIT6, DISABLE*/
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writel(val, LDO1x_CFG);
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val |= LDO1x_CFG_LDO1X_SOFT_EN;
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writel(val, LDO1x_CFG);
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}
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#if defined(AIC_SYSCFG_SIP_FLASH_ENABLE)
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static inline void syscfg_hw_sip_flash_init(void)
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{
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u32 val, ctrl_id;
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ctrl_id = 2 + AIC_SIP_FLASH_ACCESS_QSPI_ID;
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#if defined(AIC_USING_SID)
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u32 map;
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/* 1. Read eFuse to set SiP flash IO mapping */
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hal_efuse_clk_enable();
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hal_efuse_read(IOMAP_EFUSE_WID, &val);
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hal_efuse_clk_disable();
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map = (val >> EFUSE_DATA_IOMAP_POS) & 0xFF;
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/* 2. Set the SiP flash's access Controller */
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val = map << 8 | (ctrl_id & 0x3);
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#else /* AIC_USING_SID */
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val = readl(FLASH_CFG);
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val &= ~FLASH_CFG_FLASH_SRCSEL_MASK;
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val |= ctrl_id;
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#endif
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writel(val, FLASH_CFG);
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}
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
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