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39 lines
1.5 KiB
C
39 lines
1.5 KiB
C
/*
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* Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <aic_core.h>
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#include "aic_hal_clk.h"
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#ifdef FPGA_BOARD_ARTINCHIP
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const unsigned long fpga_board_rate[] = {
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[CLK_OSC24M] = CLOCK_24M, [CLK_OSC32K] = CLOCK_32K,
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[CLK_PLL_INT0] = CLOCK_60M, [CLK_PLL_INT1] = CLOCK_60M,
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[CLK_PLL_FRA0] = CLOCK_60M, [CLK_PLL_FRA2] = CLOCK_60M,
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[CLK_AXI_AHB_SRC1] = CLOCK1_FREQ, [CLK_APB0_SRC1] = CLOCK_30M,
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[CLK_CPU_SRC1] = CLOCK_60M, [CLK_AXI0] = CLOCK1_FREQ,
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[CLK_AHB0] = CLOCK1_FREQ, [CLK_APB0] = CLOCK_30M,
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[CLK_APB1] = CLOCK_24M, [CLK_CPU] = CLOCK_60M,
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[CLK_DMA] = CLOCK_60M,
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[CLK_XSPI] = CLOCK_24M, [CLK_QSPI0] = CLOCK1_FREQ,
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[CLK_QSPI1] = CLOCK1_FREQ, [CLK_SDMC0] = CLOCK1_FREQ,
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[CLK_SDMC1] = CLOCK1_FREQ,
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[CLK_SYSCFG] = CLOCK_24M, [CLK_GPIO] = CLOCK_24M,
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[CLK_CODEC] = CLOCK_AUDIO, [CLK_RGB] = CLOCK_100M,
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[CLK_DE] = CLOCK_36M, [CLK_GE] = CLOCK_36M,
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[CLK_VE] = CLOCK_36M, [CLK_WDT] = CLOCK_32K,
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[CLK_SID] = CLOCK_24M, [CLK_GTC] = CLOCK_24M,
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[CLK_UART0] = CLOCK_24M, [CLK_UART1] = CLOCK_24M,
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[CLK_UART2] = CLOCK_24M, [CLK_UART3] = CLOCK_24M,
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[CLK_I2C0] = CLOCK_24M, [CLK_I2C1] = CLOCK_24M,
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[CLK_CAN0] = CLOCK_24M, [CLK_CAN1] = CLOCK_24M,
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[CLK_PWM] = CLOCK_24M, [CLK_ADCIM] = CLOCK_24M,
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[CLK_GPAI] = CLOCK_24M, [CLK_RTP] = CLOCK_24M,
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[CLK_TSEN] = CLOCK_24M,
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};
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#endif
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