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179 lines
7.6 KiB
C
179 lines
7.6 KiB
C
/**************************************************************************************************************
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* altobeam RTOS wifi hmac source code
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*
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* Copyright (c) 2018, altobeam.inc All rights reserved.
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*
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* The source code contains proprietary information of AltoBeam, and shall not be distributed,
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* copied, reproduced, or disclosed in whole or in part without prior written permission of AltoBeam.
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*****************************************************************************************************************/
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#ifndef ATBMWIFI__HWIO_SDIO_H_INCLUDED
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#define ATBMWIFI__HWIO_SDIO_H_INCLUDED
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#include "atbm_sbus.h"
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/* DPLL initial values */
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#define DPLL_INIT_VAL_9000 (0x00000191)
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#define DPLL_INIT_VAL_CW1200 (0x0EC4F121)
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#define ALTOBEAM_WIFI_HDR_FLAG (0x34353677)
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#if (PROJ_TYPE>=ARES_A)
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#define DOWNLOAD_ITCM_ADDR (0x00010000)
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#else
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#define DOWNLOAD_ITCM_ADDR (0x00000000)
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#endif
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#if CONFIG_WIFI_BT_COMB
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#define DOWNLOAD_BLE_SRAM_ADDR (0x09018000)
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#define BLE_SRAM_CODE_SIZE 0x10000
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#else//#ifdef CONFIG_WIFI_BT_COMB
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#define DOWNLOAD_BLE_SRAM_ADDR (0x0900A000)
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#define BLE_SRAM_CODE_SIZE 0x16000
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#endif //#ifdef CONFIG_WIFI_BT_COMB
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#define DOWNLOAD_ITCM_SIZE (160*1024)
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#define DOWNLOAD_DTCM_ADDR (0x00800000)
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#define DOWNLOAD_DTCM_SIZE (48*1024)
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#define DOWNLOAD_BLOCK_SIZE (256)
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#define SYS_BASE_ADDR_SILICON (0)
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#define PAC_BASE_ADDRESS_SILICON (SYS_BASE_ADDR_SILICON + 0x09000000)
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#define PAC_SHARED_MEMORY_SILICON (PAC_BASE_ADDRESS_SILICON)
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#define CW12000_APB(addr) (PAC_SHARED_MEMORY_SILICON + (addr))
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/* ***************************************************************
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*Device register definitions
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*************************************************************** */
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/* WBF - SPI Register Addresses */
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#define ATBM_HIFREG_ADDR_ID_BASE (0x0000)
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/* 16/32 bits */
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#define ATBM_HIFREG_CONFIG_REG_ID (0x0000)
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/* 16/32 bits */
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#define ATBM_HIFREG_CONTROL_REG_ID (0x0001)
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/* 16 bits, Q mode W/R */
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#define ATBM_HIFREG_IN_OUT_QUEUE_REG_ID (0x0002)
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/* 32 bits, AHB bus R/W */
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#define ATBM_HIFREG_AHB_DPORT_REG_ID (0x0003)
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/* 16/32 bits */
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#define ATBM_HIFREG_SRAM_BASE_ADDR_REG_ID (0x0004)
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/* 32 bits, APB bus R/W */
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#define ATBM_HIFREG_SRAM_DPORT_REG_ID (0x0005)
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/* 32 bits, t_settle/general */
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#define ATBM_HIFREG_TSET_GEN_R_W_REG_ID (0x0006)
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/* 16 bits, Q mode read, no length */
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#define ATBM_HIFREG_FRAME_OUT_REG_ID (0x0007)
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#define ATBM_HIFREG_ADDR_ID_MAX (ATBM_HIFREG_FRAME_OUT_REG_ID)
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/* WBF - Control register bit set */
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/* next o/p length, bit 11 to 0 */
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#define ATBM_HIFREG_CONT_NEXT_LEN_MASK (0xCFFF)
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#define ATBM_HIFREG_CONT_NEXT_LEN_LSB_MASK (0x0FFF)
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#define ATBM_HIFREG_CONT_NEXT_LEN_MSB_MASK (0xC000)
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#define ATBM_HIFREG_CONT_WUP_BIT (BIT(12))
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#define ATBM_HIFREG_CONT_RDY_BIT (BIT(13))
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#define ATBM_HIFREG_CONT_IRQ_ENABLE (BIT(14))
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#define ATBM_HIFREG_CONT_RDY_ENABLE (BIT(15))
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#define ATBM_HIFREG_CONT_IRQ_RDY_ENABLE (BIT(14)|BIT(15))
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#define ATBM_HIFREG_PS_SYNC_SDIO_FLAG (BIT(23))
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#define ATBM_HIFREG_PS_SYNC_SDIO_CLEAN (BIT(24))
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/* SPI Config register bit set */
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#define ATBM_HIFREG_CONFIG_FRAME_BIT (BIT(2))
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#define ATBM_HIFREG_CONFIG_WORD_MODE_BITS (BIT(3)|BIT(4))
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#define ATBM_HIFREG_CONFIG_WORD_MODE_1 (BIT(3))
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#define ATBM_HIFREG_CONFIG_WORD_MODE_2 (BIT(4))
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#define ATBM_HIFREG_CONFIG_ERROR_0_BIT (BIT(5))
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#define ATBM_HIFREG_CONFIG_ERROR_1_BIT (BIT(6))
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#define ATBM_HIFREG_CONFIG_ERROR_2_BIT (BIT(7))
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/* TBD: Sure??? */
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#define ATBM_HIFREG_CONFIG_CSN_FRAME_BIT (BIT(7))
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#define ATBM_HIFREG_CONFIG_ERROR_3_BIT (BIT(8))
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#define ATBM_HIFREG_CONFIG_ERROR_4_BIT (BIT(9))
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/* QueueM */
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#define ATBM_HIFREG_CONFIG_ACCESS_MODE_BIT (BIT(10))
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/* AHB bus */
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#define ATBM_HIFREG_CONFIG_AHB_PFETCH_BIT (BIT(11))
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#define ATBM_HIFREG_CONFIG_CPU_CLK_DIS_BIT (BIT(12))
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/* APB bus */
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#define ATBM_HIFREG_CONFIG_PFETCH_BIT (BIT(13))
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/* cpu reset */
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#define ATBM_HIFREG_CONFIG_CPU_RESET_BIT (BIT(14))
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#define ATBM_HIFREG_CONFIG_CLEAR_INT_BIT (BIT(15))
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/* For CW1200 the IRQ Enable and Ready Bits are in CONFIG register */
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#define ATBM_HIFREG_CONF_IRQ_RDY_ENABLE (BIT(16)|BIT(17))
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#define ATBM_HIFREG_CONF_RDY_IRQ_ENABLE (BIT(17))
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#define ATBM_HIFREG_CONF_DATA_IRQ_ENABLE (BIT(16))
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#define ATBM_HIFREG_CONFIG_CPU_RESET_BIT_2 (BIT(22))
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int atbm_data_read(struct atbmwifi_common *hw_priv,
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atbm_void *buf, atbm_uint32 buf_len);
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int atbm_data_write(struct atbmwifi_common *hw_priv, const atbm_void *buf,
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atbm_size_t buf_len);
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int atbm_reg_read_dpll(struct atbmwifi_common *hw_priv, atbm_uint16 addr,
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atbm_void *buf, atbm_uint32 buf_len);
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int atbm_reg_write_dpll(struct atbmwifi_common *hw_priv, atbm_uint16 addr,
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const atbm_void *buf, atbm_uint32 buf_len);
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int atbm_reg_read(struct atbmwifi_common *hw_priv, atbm_uint16 addr,
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atbm_void *buf, atbm_uint32 buf_len);
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int atbm_reg_write(struct atbmwifi_common *hw_priv, atbm_uint16 addr,
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const atbm_void *buf, atbm_uint32 buf_len);
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int atbm_indirect_read(struct atbmwifi_common *hw_priv, atbm_uint32 addr, atbm_void *buf,
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atbm_uint32 buf_len, atbm_uint32 prefetch, atbm_uint16 port_addr);
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int atbm_apb_write(struct atbmwifi_common *hw_priv, atbm_uint32 addr, const atbm_void *buf,
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atbm_uint32 buf_len);
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int atbm_ahb_write(struct atbmwifi_common *priv, atbm_uint32 addr, const atbm_void *buf,
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atbm_uint32 buf_len);
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int atbm_direct_read_reg_32(struct atbmwifi_common *hw_priv, atbm_uint32 addr, atbm_uint32 *val);
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int atbm_direct_write_reg_32(struct atbmwifi_common *hw_priv, atbm_uint32 addr, atbm_uint32 val);
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int __atbm_irq_enable(struct atbmwifi_common *priv, int enable);
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#define WRITE_32K_ADDR_MSK (0xfffff000)
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#define WRITE_32K_ADDR (0x16101000)
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extern struct sbus_ops atbm_sdio_sbus_ops;
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#define ATBM_SDIO_CCCR_IENx 0x04
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#define ATBM_SDIO_CCCR_IOEx 0x02
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#define ATBM_SDIO_CCCR_IORx 0x03
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#define ATBM_SDIO_CCCR_ABORT 0x06 /* function abort/card reset */
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#define ATBM_SDIO_CCCR_IF 0x07 /* bus interface controls */
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#define ATBM_SDIO_CCCR_SPEED 0x13
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#define ATBM_SDIO_SPEED_SHS 0x01 /* Supports High-Speed mode */
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#define ATBM_SDIO_SPEED_BSS_SHIFT 1
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#define ATBM_SDIO_SPEED_SDR25 (1<<ATBM_SDIO_SPEED_BSS_SHIFT)
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#define ATBM_SDIO_SPEED_EHS ATBM_SDIO_SPEED_SDR25 /* Enable High-Speed */
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#define ATBM_SDIO_BUS_WIDTH_4BIT 0x02
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#define ATBM_SDIO_FBR_BLKSIZE 0x10
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#define ATBM_SDIO_CCCR_POWER 0x12
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#define SDIO_POWER_SMPC 0x01 /* Supports Master Power Control */
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#define SDIO_POWER_EMPC 0x02 /* Enable Master Power Control */
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#define ATBM_SDIO_CCCR_CAPS 0x08
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#define SDIO_CCCR_CAP_SDC 0x01 /* can do CMD52 while data transfer */
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#define SDIO_CCCR_CAP_SMB 0x02 /* can do multi-block xfers (CMD53) */
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#define SDIO_CCCR_CAP_SRW 0x04 /* supports read-wait protocol */
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#define SDIO_CCCR_CAP_SBS 0x08 /* supports suspend/resume */
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#define SDIO_CCCR_CAP_S4MI 0x10 /* interrupt during 4-bit CMD53 */
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#define SDIO_CCCR_CAP_E4MI 0x20 /* enable ints during 4-bit CMD53 */
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#define SDIO_CCCR_CAP_LSC 0x40 /* low speed card */
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#define SDIO_CCCR_CAP_4BLS 0x80 /* 4 bit low speed card */
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#define ATBM_SDIO_CCCR_CCCR 0x00
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#define SDIO_CCCR_REV_1_00 0 /* CCCR/FBR Version 1.00 */
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#define SDIO_CCCR_REV_1_10 1 /* CCCR/FBR Version 1.10 */
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#define SDIO_CCCR_REV_1_20 2 /* CCCR/FBR Version 1.20 */
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#define SDIO_SDIO_REV_1_00 0 /* SDIO Spec Version 1.00 */
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#define SDIO_SDIO_REV_1_10 1 /* SDIO Spec Version 1.10 */
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#define SDIO_SDIO_REV_1_20 2 /* SDIO Spec Version 1.20 */
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#define SDIO_SDIO_REV_2_00 3 /* SDIO Spec Version 2.00 */
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atbm_void atbm_sdio_module_init(atbm_void);
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int atbm_sdio_set_block_size(struct sbus_priv *self, atbm_uint32 size);
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int atbm_sdio_suspend(struct atbmwifi_common *hw_priv);
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int atbm_sdio_resume(struct atbmwifi_common *hw_priv);
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atbm_void atbm_sdio_module_exit(atbm_void);
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#endif /* ATBMWIFI__HWIO_SDIO_H_INCLUDED */
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