mirror of
https://gitee.com/Vancouver2017/luban-lite.git
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299 lines
7.9 KiB
C
299 lines
7.9 KiB
C
/*
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* Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: zrq <ruiqi.zheng@artinchip.com>
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*/
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#include <drivers/rt_drv_pwm.h>
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#include <drivers/pm.h>
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#define LOG_TAG "EPWM"
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#include "aic_core.h"
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#include "aic_hal_clk.h"
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#include "hal_epwm.h"
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static struct rt_device_pwm g_aic_epwm = {0};
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static struct aic_epwm_pulse_para g_pulse_para[AIC_EPWM_CH_NUM] = {0};
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extern struct aic_epwm_arg epwm_pdata[];
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extern const int epwm_pdata_size;
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#if defined (AIC_EPWM_DRV_V11) || defined (AIC_EPWM_DRV_V12)
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static u8 g_epwm_pul_flag[AIC_EPWM_CH_NUM] = {0};
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#endif
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static rt_bool_t drv_epwm_ch_valid(struct rt_pwm_configuration *cfg)
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{
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if (cfg->channel > (AIC_EPWM_CH_NUM - 1)) {
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LOG_E("Invalid channel No.%d", cfg->channel);
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return RT_TRUE;
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}
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return RT_FALSE;
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}
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static rt_err_t drv_epwm_enable(struct rt_device_pwm *device,
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struct rt_pwm_configuration *cfg,
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rt_bool_t enable)
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{
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if (drv_epwm_ch_valid(cfg))
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return -RT_EINVAL;
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if (enable)
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return !hal_epwm_enable(cfg->channel) ? RT_EOK : -RT_ERROR;
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else
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return !hal_epwm_disable(cfg->channel) ? RT_EOK : -RT_ERROR;
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}
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static rt_err_t drv_epwm_set(struct rt_device_pwm *device,
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struct rt_pwm_configuration *cfg)
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{
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if (drv_epwm_ch_valid(cfg))
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return -RT_EINVAL;
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if (hal_epwm_set(cfg->channel, cfg->pulse, cfg->period, (rt_uint32_t)EPWM_SET_CMPA_CMPB))
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return -RT_ERROR;
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return RT_EOK;
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}
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static rt_err_t drv_epwm_set_output(struct rt_device_pwm *device,
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struct rt_pwm_configuration *cfg)
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{
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if (drv_epwm_ch_valid(cfg))
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return -RT_EINVAL;
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if (hal_epwm_set(cfg->channel, cfg->pulse, cfg->period, cfg->output))
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return -RT_ERROR;
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return RT_EOK;
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}
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static rt_err_t drv_epwm_set_pul(struct rt_device_pwm *device,
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struct rt_pwm_configuration *cfg)
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{
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if (drv_epwm_ch_valid(cfg))
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return -RT_EINVAL;
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g_pulse_para[cfg->channel].pulse_cnt = cfg->pul_cnt;
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g_pulse_para[cfg->channel].duty_ns = cfg->pulse;
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g_pulse_para[cfg->channel].prd_ns = cfg->period;
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#if defined (AIC_EPWM_DRV_V11) || defined (AIC_EPWM_DRV_V12)
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hal_epwm_pul_config(cfg->channel);
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g_epwm_pul_flag[cfg->channel] = 1;
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/* temporarily control two outputs simultaneously */
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if (hal_epwm_pul_set(cfg->channel, cfg->pulse, cfg->period, EPWM_SET_CMPA_CMPB, cfg->pul_cnt))
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return -RT_ERROR;
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hal_epwm_act_sw_ct(cfg->channel, EPWM_SET_CMPA_CMPB, EPWM_ACT_SW_NONE);
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hal_epwm_count_ct(cfg->channel, EPWM_MODE_UP_COUNT);
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hal_epwm_pul_sw_updt(cfg->channel);
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#elif defined (AIC_EPWM_DRV_V10)
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if (hal_epwm_set(cfg->channel, cfg->pulse, cfg->period, (rt_uint32_t)EPWM_SET_CMPA_CMPB))
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return -RT_ERROR;
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hal_epwm_int_config(cfg->channel, cfg->irq_mode, 1);
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hal_epwm_enable(cfg->channel);
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#endif
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return RT_EOK;
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}
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static rt_err_t drv_epwm_get(struct rt_device_pwm *device,
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struct rt_pwm_configuration *cfg)
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{
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if (drv_epwm_ch_valid(cfg))
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return -RT_EINVAL;
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if (hal_epwm_get(cfg->channel, (u32 *)&cfg->pulse, (u32 *)&cfg->period))
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return -RT_ERROR;
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return RT_EOK;
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}
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static rt_err_t drv_epwm_control(struct rt_device_pwm *device,
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int cmd, void *arg)
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{
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struct rt_pwm_configuration *cfg = (struct rt_pwm_configuration *)arg;
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switch (cmd) {
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case PWM_CMD_ENABLE:
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return drv_epwm_enable(device, cfg, RT_TRUE);
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case PWM_CMD_DISABLE:
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return drv_epwm_enable(device, cfg, RT_FALSE);
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case PWM_CMD_SET:
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return drv_epwm_set(device, cfg);
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case PWM_CMD_SET_OUTPUT:
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return drv_epwm_set_output(device, cfg);
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case PWM_CMD_GET:
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return drv_epwm_get(device, cfg);
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case PWM_CMD_SET_PUL:
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return drv_epwm_set_pul(device, cfg);
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default:
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LOG_I("Unsupported cmd: 0x%x", cmd);
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return -RT_EINVAL;
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}
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return RT_EOK;
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}
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static struct rt_pwm_ops aic_epwm_ops = {
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.control = drv_epwm_control
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};
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#ifdef RT_USING_PM
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static int drv_epwm_suspend(const struct rt_device *device, rt_uint8_t mode)
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{
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switch (mode)
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{
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case PM_SLEEP_MODE_IDLE:
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break;
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case PM_SLEEP_MODE_LIGHT:
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case PM_SLEEP_MODE_DEEP:
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case PM_SLEEP_MODE_STANDBY:
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hal_clk_disable(CLK_PWMCS);
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break;
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default:
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break;
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}
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return 0;
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}
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static void drv_epwm_resume(const struct rt_device *device, rt_uint8_t mode)
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{
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switch (mode)
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{
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case PM_SLEEP_MODE_IDLE:
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break;
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case PM_SLEEP_MODE_LIGHT:
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case PM_SLEEP_MODE_DEEP:
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case PM_SLEEP_MODE_STANDBY:
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#if defined (AIC_EPWM_DRV_V11)
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hal_clk_set_freq(CLK_PWMCS_SDFM, EPWM_CLK_RATE);
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#elif defined (AIC_EPWM_DRV_V10)
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hal_clk_set_freq(CLK_PWMCS, EPWM_CLK_RATE);
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#endif
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#if defined (AIC_EPWM_DRV_V10) || defined (AIC_EPWM_DRV_V11)
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hal_clk_enable(CLK_PWMCS);
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#endif
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break;
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default:
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break;
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}
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}
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static struct rt_device_pm_ops drv_epwm_pm_ops =
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{
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SET_LATE_DEVICE_PM_OPS(drv_epwm_suspend, drv_epwm_resume)
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NULL,
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};
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#endif
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irqreturn_t aic_epwm_irq(int irq, void *arg)
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{
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#if defined AIC_EPWM_DRV_V10
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static u32 isr_cnt[AIC_EPWM_CH_NUM] = {0};
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#endif
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#if defined (AIC_EPWM_DRV_V10) || defined (AIC_EPWM_DRV_V11)
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u32 stat;
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int i;
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for (i = 0; i < AIC_EPWM_CH_NUM; i++) {
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stat = hal_epwm_int_sts(i);
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if (stat & EPWM_INT_FLG) {
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#if defined (AIC_EPWM_DRV_V11)
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int level = hal_epwm_get_default_level(i);
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hal_epwm_act_sw_ct(i, EPWM_SET_CMPA_CMPB, level + EPWM_ACT_SW_LOW);
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if (g_epwm_pul_flag[i] == 0) {
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/* enable the EPWM_PUL_OUT_EN will enter the interrupt */
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hal_epwm_count_ct(i, (u32)EPWM_MODE_STOP_COUNT);
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}
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if (g_epwm_pul_flag[i] == 1) {
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g_epwm_pul_flag[i] = 0;
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}
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#elif defined (AIC_EPWM_DRV_V10)
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isr_cnt[i]++;
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if (isr_cnt[i] == g_pulse_para[i].pulse_cnt) {
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hal_epwm_set(i, g_pulse_para[i].prd_ns, g_pulse_para[i].prd_ns, (rt_uint32_t)EPWM_SET_CMPA_CMPB);
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hal_epwm_int_config(i, 0, 0);
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pr_info("\nisr cnt:%d,disabled the epwm%d interrupt now.\n", isr_cnt[i], i);
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isr_cnt[i] = 0;
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}
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#endif
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hal_epwm_clr_int(stat, i);
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}
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}
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#endif
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#ifdef AIC_EPWM_DRV_V12
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u32 stat;
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u32 ch = irq - EPWM0_IRQn;
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stat = hal_epwm_int_sts(ch);
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if (stat & EPWM_INT_FLG) {
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if (g_epwm_pul_flag[ch] == 0) {
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/* enable the EPWM_PUL_OUT_EN will enter the interrupt */
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hal_epwm_count_ct(ch, (u32)EPWM_MODE_STOP_COUNT);
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}
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if (g_epwm_pul_flag[ch] == 1) {
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g_epwm_pul_flag[ch] = 0;
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}
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hal_epwm_clr_int(stat, ch);
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}
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#endif
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return IRQ_HANDLED;
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}
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int drv_epwm_init(void)
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{
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int i, ret;
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ret = hal_epwm_init();
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if (ret < 0) {
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LOG_E("EPWM init failed!");
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return ret;
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}
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for (i = 0; i < epwm_pdata_size; i++) {
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hal_epwm_ch_init(&epwm_pdata[i]);
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#ifdef AIC_EPWM_DRV_V12
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aicos_request_irq(EPWM0_IRQn + epwm_pdata[i].id, aic_epwm_irq, 0, NULL, NULL);
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#endif
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}
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#if defined (AIC_EPWM_DRV_V10) || defined (AIC_EPWM_DRV_V11)
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aicos_request_irq(PWMCS_PWM_IRQn, aic_epwm_irq, 0, NULL, NULL);
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#endif
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if (rt_device_pwm_register(&g_aic_epwm, "epwm", &aic_epwm_ops, NULL))
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return -RT_ERROR;
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#ifdef RT_USING_PM
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rt_pm_device_register(&g_aic_epwm.parent, &drv_epwm_pm_ops);
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#endif
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LOG_I("ArtInChip EPWM loaded");
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return RT_EOK;
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}
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INIT_PREV_EXPORT(drv_epwm_init);
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#if defined(RT_USING_FINSH)
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#include <finsh.h>
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static void cmd_epwm_status(int argc, char **argv)
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{
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hal_epwm_status_show();
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}
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MSH_CMD_EXPORT_ALIAS(cmd_epwm_status, epwm_status, Show the status of EPWM);
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#endif
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