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https://gitee.com/Vancouver2017/luban-lite.git
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351 lines
9.4 KiB
C
351 lines
9.4 KiB
C
/*
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* Copyright (c) 2023-2025, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <aic_core.h>
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#include "aic_hal_clk.h"
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#define to_clk_auth(_hw) \
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container_of(_hw, struct aic_clk_auth_cfg, comm)
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int cmu_auth_lock(u32 auth, u32 key, u32 shift, u32 lock, u32 status, u32 who)
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{
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u32 val = (key << shift) | who;
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writel(val, cmu_reg(auth));
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aicos_udelay(100);
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val = readl(cmu_reg(lock));
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if (!(val & status)) {
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hal_log_err("Failed to request authorize %X for 0x%x!\n", key >> 8, who);
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return -EIO;
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}
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return 0;
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}
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int cmu_auth_request(u32 auth, u32 key, u32 shift, u32 status, u32 who)
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{
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return cmu_auth_lock(auth, key, shift, auth, status, who);
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}
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static int clk_auth_write(struct aic_clk_auth_cfg *mod, u32 val)
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{
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if (!mod->offset_wr_auth_reg || (mod->wr_auth_bit < 0) || mod->key_bit < 0) {
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hal_log_err("%s params error!\n", mod->comm.name);
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return -EINVAL;
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}
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if (cmu_auth_request(mod->offset_wr_auth_reg,
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mod->key_code, mod->key_bit, BIT(mod->wr_auth_bit),
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mod->offset_reg))
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return -EIO;
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writel(val, cmu_reg(mod->offset_reg));
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return 0;
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}
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static int clk_auth_enable(struct aic_clk_comm_cfg *comm_cfg)
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{
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struct aic_clk_auth_cfg *mod = to_clk_auth(comm_cfg);
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u32 i, val;
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if (!mod->table_gates) {
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hal_log_err("%s does not have valid table_gates\n", comm_cfg->name);
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return -EINVAL;
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}
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if (mod->table_gates[0] < 0)
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return 0;
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val = readl(cmu_reg(mod->offset_reg));
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for (i = 0; i < mod->num_gates; i++) {
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val |= (1 << mod->table_gates[i]);
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clk_auth_write(mod, val);
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}
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return 0;
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}
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static void clk_auth_disable(struct aic_clk_comm_cfg *comm_cfg)
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{
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struct aic_clk_auth_cfg *mod = to_clk_auth(comm_cfg);
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u32 val = 0;
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s32 i;
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if (!mod->table_gates) {
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hal_log_err("%s does not have valid table_gates\n", comm_cfg->name);
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return;
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}
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if (mod->table_gates[0] < 0)
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return;
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val = readl(cmu_reg(mod->offset_reg));
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for (i = mod->num_gates - 1; i >= 0; i--) {
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val &= ~(1 << mod->table_gates[i]);
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clk_auth_write(mod, val);
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}
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}
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static int clk_auth_enable_and_deassert_rst(struct aic_clk_comm_cfg *comm_cfg)
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{
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struct aic_clk_auth_cfg *mod = to_clk_auth(comm_cfg);
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u32 val;
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clk_auth_enable(comm_cfg);
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aicos_udelay(30);
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/* deassert rst */
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val = readl(cmu_reg(mod->offset_reg));
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val |= (1 << MOD_RSTN);
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clk_auth_write(mod, val);
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aicos_udelay(30);
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return 0;
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}
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static void clk_auth_disable_and_assert_rst(struct aic_clk_comm_cfg *comm_cfg)
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{
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struct aic_clk_auth_cfg *mod = to_clk_auth(comm_cfg);
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u32 val;
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/* assert rst */
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val = readl(cmu_reg(mod->offset_reg));
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val &= ~(1 << MOD_RSTN);
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clk_auth_write(mod, val);
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aicos_udelay(30);
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clk_auth_disable(comm_cfg);
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aicos_udelay(30);
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}
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static int clk_auth_mod_is_enabled(struct aic_clk_comm_cfg *comm_cfg)
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{
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struct aic_clk_auth_cfg *mod = to_clk_auth(comm_cfg);
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u32 val, i, ret = 1;
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if (!mod->table_gates) {
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hal_log_err("%s does not have valid table_gates\n", comm_cfg->name);
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return -EINVAL;
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}
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if (mod->table_gates[0] < 0)
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return ret;
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val = readl(cmu_reg(mod->offset_reg));
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for (i = 0; i < mod->num_gates; i++) {
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ret &= ((val & (1 << mod->table_gates[i])) >> mod->table_gates[i]);
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if (!ret)
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return ret;
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}
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return ret;
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}
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static unsigned long clk_auth_mod_recalc_rate(struct aic_clk_comm_cfg *comm_cfg,
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unsigned long parent_rate)
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{
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unsigned long rate, val, div = 0, div_mask, parent_index = 0;
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struct aic_clk_auth_cfg *mod = to_clk_auth(comm_cfg);
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if (!mod->table_div) {
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hal_log_err("%s does not have valid table_div\n", comm_cfg->name);
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return parent_rate;
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}
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parent_index = (readl(cmu_reg(mod->offset_reg)) >> mod->mux_bit) & mod->mux_mask;
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if (parent_index >= mod->num_parents) {
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hal_log_err("%s parent clock index error!\n", comm_cfg->name);
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return parent_rate;
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}
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if (mod->num_parents != mod->num_div) {
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hal_log_err("%s parent number is not equal to divider number!\n", comm_cfg->name);
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return parent_rate;
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}
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if (mod->table_div[parent_index].shift < 0) {
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rate = parent_rate / mod->table_div[parent_index].wd.div;
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} else {
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div_mask = (1 << mod->table_div[parent_index].wd.width) - 1;
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val = readl(cmu_reg(mod->offset_reg));
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div = (val >> mod->table_div[parent_index].shift) & div_mask;
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rate = parent_rate / (div + 1);
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}
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#ifdef CONFIG_DEBUG_ON_FPGA_BOARD_ARTINCHIP
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rate = fpga_board_rate[mod->id];
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#endif
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return rate;
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}
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static void try_best_divider(u32 rate, u32 parent_rate, u32 max_div, u32 *div)
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{
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u32 tmp, i, min_delta = U32_MAX, best_div = 0;
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for (i = 1; i <= max_div; i++) {
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tmp = i * rate;
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if (parent_rate == tmp) {
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best_div = i;
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goto __out;
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}
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if (abs(parent_rate - tmp) < min_delta) {
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min_delta = abs(parent_rate - tmp);
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best_div = i;
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}
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}
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__out:
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*div = best_div;
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}
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static unsigned int clk_auth_mod_get_parent(struct aic_clk_comm_cfg *comm_cfg)
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{
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struct aic_clk_auth_cfg *mod = to_clk_auth(comm_cfg);
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u32 parent_index = (readl(cmu_reg(mod->offset_reg)) >> mod->mux_bit) & mod->mux_mask;
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if (parent_index >= mod->num_parents) {
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hal_log_err("%s parent clock index error!\n", comm_cfg->name);
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return -EINVAL;
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}
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if (mod->num_parents != mod->num_div) {
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hal_log_err("%s parent number is not equal to divider number!\n", comm_cfg->name);
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return -EINVAL;
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}
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return mod->parent_ids[parent_index];
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}
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static int clk_auth_mod_set_parent(struct aic_clk_comm_cfg *comm_cfg,
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unsigned int parent_id)
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{
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struct aic_clk_auth_cfg *mod = to_clk_auth(comm_cfg);
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u32 i, val, parent_index = 0xFFFF;
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for (i = 0; i < mod->num_parents; i++) {
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if (parent_id == mod->parent_ids[i]) {
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parent_index = i;
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break;
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}
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}
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if (parent_index == 0xFFFF) {
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return -EINVAL;
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}
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val = readl(cmu_reg(mod->offset_reg));
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val &= ~(mod->mux_mask << mod->mux_bit);
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val |= parent_index << mod->mux_bit;
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clk_auth_write(mod, val);
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return 0;
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}
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static int clk_auth_mod_set_rate(struct aic_clk_comm_cfg *comm_cfg,
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unsigned long rate,
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unsigned long parent_rate)
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{
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struct aic_clk_auth_cfg *mod = to_clk_auth(comm_cfg);
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u32 val, parent_index;
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u32 div = 0, div_max, div_mask;
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if (!mod->table_div) {
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hal_log_err("%s does not have valid table_div\n", comm_cfg->name);
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return -EINVAL;
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}
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parent_index = (readl(cmu_reg(mod->offset_reg)) >> mod->mux_bit) & mod->mux_mask;
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if (parent_index >= mod->num_parents) {
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hal_log_err("%s parent clock index error!\n", comm_cfg->name);
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return -EINVAL;
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}
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if (mod->num_parents != mod->num_div) {
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hal_log_err("%s parent number is not equal to divider number!\n", comm_cfg->name);
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return -EINVAL;
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}
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if (mod->table_div[parent_index].shift < 0)
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return 0;
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div_max = 1 << mod->table_div[parent_index].wd.width;
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try_best_divider(rate, parent_rate, div_max, &div);
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div_mask = div_max - 1;
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val = readl(cmu_reg(mod->offset_reg));
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val &= ~(div_mask << mod->table_div[parent_index].shift);
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val |= (div - 1) << mod->table_div[parent_index].shift;
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clk_auth_write(mod, val);
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return 0;
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}
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static long clk_auth_mod_round_rate(struct aic_clk_comm_cfg *comm_cfg,
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unsigned long rate,
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unsigned long *prate)
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{
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u32 rrate, parent_rate, parent_index;
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u32 div = 0, div_max;
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struct aic_clk_auth_cfg *mod = to_clk_auth(comm_cfg);
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if (!mod->table_div) {
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hal_log_err("%s does not have valid table_div\n", comm_cfg->name);
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return *prate;
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}
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parent_rate = *prate;
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parent_index = (readl(cmu_reg(mod->offset_reg)) >> mod->mux_bit) & mod->mux_mask;
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if (parent_index >= mod->num_parents) {
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hal_log_err("%s parent clock index error!\n", comm_cfg->name);
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return parent_rate;
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}
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if (mod->num_parents != mod->num_div) {
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hal_log_err("%s parent number is not equal to divider number!\n", comm_cfg->name);
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return parent_rate;
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}
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if (mod->table_div[parent_index].shift < 0) {
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rrate = parent_rate / mod->table_div[parent_index].wd.div;
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} else {
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div_max = 1 << mod->table_div[parent_index].wd.width;
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try_best_divider(rate, parent_rate, div_max, &div);
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rrate = parent_rate / div;
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}
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#ifdef FPGA_BOARD_ARTINCHIP
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rrate = fpga_board_rate[mod->id];
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#endif
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return rrate;
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}
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const struct aic_clk_ops aic_clk_auth_ops = {
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.enable = clk_auth_enable,
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.disable = clk_auth_disable,
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.enable_clk_deassert_rst = clk_auth_enable_and_deassert_rst,
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.disable_clk_assert_rst = clk_auth_disable_and_assert_rst,
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.is_enabled = clk_auth_mod_is_enabled,
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.recalc_rate = clk_auth_mod_recalc_rate,
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.round_rate = clk_auth_mod_round_rate,
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.get_parent = clk_auth_mod_get_parent,
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.set_parent = clk_auth_mod_set_parent,
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.set_rate = clk_auth_mod_set_rate,
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};
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