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72 lines
1.5 KiB
C
72 lines
1.5 KiB
C
/*
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* Copyright (c) 2025, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: matteo <duanmt@artinchip.com>
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*/
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#ifndef _ARTINCHIP_HAL_PBUS_H__
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#define _ARTINCHIP_HAL_PBUS_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "aic_common.h"
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#define AIC_PBUS_SIZE (64 * 1024)
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enum aic_pbus_pol {
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AIC_PBUS_POL_LOW_ACTIVE = 0,
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AIC_PBUS_POL_HIGH_ACTIVE = 1,
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};
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enum aic_pbus_edge {
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AIC_PBUS_POL_FALL_EDGE = 0,
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AIC_PBUS_POL_RISE_EDGE = 1,
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};
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enum aic_pbus_clk_div {
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AIC_PBUS_CLK_DIV_UNDEF = 0,
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AIC_PBUS_CLK_DIV_2,
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AIC_PBUS_CLK_DIV_4,
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AIC_PBUS_CLK_DIV_8
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};
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struct aic_pbus_timing {
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u16 holdtime;
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u16 delaytime;
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};
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struct aic_pbus_cfg {
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bool bus_clk_enable;
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enum aic_pbus_edge bus_clk_pol;
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enum aic_pbus_clk_div bus_clk_div;
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enum aic_pbus_pol out_enable_pol;
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enum aic_pbus_pol wr_enable_pol;
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enum aic_pbus_pol addr_valid_pol;
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enum aic_pbus_pol cs_pol;
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struct aic_pbus_timing out_enable;
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struct aic_pbus_timing wr_data;
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struct aic_pbus_timing wr_rd;
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struct aic_pbus_timing addr_valid;
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struct aic_pbus_timing addr;
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struct aic_pbus_timing cs;
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};
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int hal_pbus_init(void);
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int hal_pbus_deinit(void);
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int hal_pbus_get_cfg(struct aic_pbus_cfg *cfg);
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int hal_pbus_set_cfg(struct aic_pbus_cfg *cfg);
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int hal_pbus_read(u32 offset, u8 *buf, u32 len);
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int hal_pbus_write(u32 offset, u8 *buf, u32 len);
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#ifdef __cplusplus
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}
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#endif
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#endif
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