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119 lines
3.6 KiB
C
119 lines
3.6 KiB
C
/**
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******************************************************************************
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*
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* @file rwnx_platorm.h
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*
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* Copyright (C) RivieraWaves 2012-2019
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*
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******************************************************************************
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*/
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#ifndef _RWNX_PLATFORM_H_
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#define _RWNX_PLATFORM_H_
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#include "lmac_msg.h"
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struct rwnx_hw;
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/**
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* struct rwnx_plat - Operation pointers for RWNX PCI platform
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*
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* @pci_dev: pointer to pci dev
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* @enabled: Set if embedded platform has been enabled (i.e. fw loaded and
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* ipc started)
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* @enable: Configure communication with the fw (i.e. configure the transfers
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* enable and register interrupt)
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* @disable: Stop communication with the fw
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* @deinit: Free all ressources allocated for the embedded platform
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* @get_address: Return the virtual address to access the requested address on
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* the platform.
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* @ack_irq: Acknowledge the irq at link level.
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* @get_config_reg: Return the list (size + pointer) of registers to restore in
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* order to reload the platform while keeping the current configuration.
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*
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* @priv Private data for the link driver
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*/
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struct rwnx_plat {
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#if 0
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struct pci_dev *pci_dev;
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#ifdef AICWF_SDIO_SUPPORT
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struct aic_sdio_dev *sdiodev;
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#endif
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#ifdef AICWF_USB_SUPPORT
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struct aic_usb_dev *usbdev;
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#endif
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#endif
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bool enabled;
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};
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extern u8 aic8800dc_rf_flag;
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extern u8 aic8800dc_calib_flag;
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extern struct rwnx_plat *g_rwnx_plat;
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int rwnx_platform_init(struct rwnx_plat *rwnx_plat, void **platform_data);
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void rwnx_platform_deinit(struct rwnx_hw *rwnx_hw);
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int rwnx_platform_on(struct rwnx_hw *rwnx_hw);
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void rwnx_platform_off(struct rwnx_hw *rwnx_hw);
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int rwnx_send_reboot(struct rwnx_hw *rwnx_hw);
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int aicwf_misc_ram_init_8800dc(struct rwnx_hw *rwnx_hw);
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int aicwf_patch_table_load(struct rwnx_hw *rwnx_hw);
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#ifdef CONFIG_DPD
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#define ROM_FMAC_CALIB_ADDR 0x00130000
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#define FW_PATH_MAX_LEN 200
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typedef struct {
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uint32_t bit_mask[3];
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uint32_t reserved;
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uint32_t dpd_high[96];
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uint32_t dpd_11b[96];
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uint32_t dpd_low[96];
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uint32_t idac_11b[48];
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uint32_t idac_high[48];
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uint32_t idac_low[48];
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uint32_t loft_res[18];
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uint32_t rx_iqim_res[16];
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} rf_misc_ram_t;
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typedef struct {
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uint32_t bit_mask[4];
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uint32_t dpd_high[96];
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uint32_t loft_res[18];
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} rf_misc_ram_lite_t;
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#define MEMBER_SIZE(type, member) sizeof(((type *)0)->member)
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#define DPD_RESULT_SIZE_8800DC sizeof(rf_misc_ram_lite_t)
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extern rf_misc_ram_lite_t dpd_res;
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int aicwf_plat_calib_load_8800dc(struct rwnx_hw *rwnx_hw);
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int aicwf_dpd_calib_8800dc(struct rwnx_hw *rwnx_hw, rf_misc_ram_lite_t *dpd_res);
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int aicwf_dpd_result_load_8800dc(struct rwnx_hw *rwnx_hw, rf_misc_ram_lite_t *dpd_res);
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int aicwf_dpd_result_apply_8800dc(struct rwnx_hw *rwnx_hw, rf_misc_ram_lite_t *dpd_res);
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uint32_t aicwf_dpd_get_result(void);
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#endif /* CONFIG_DPD */
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#ifdef CONFIG_LOAD_USERCONFIG
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void aicwf_userconfig_init(void);
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void get_nvram_txpwr_idx(txpwr_idx_conf_t *txpwr_idx);
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void get_nvram_txpwr_ofst(txpwr_ofst_conf_t *txpwr_ofst);
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void get_nvram_xtal_cap(xtal_cap_conf_t *xtal_cap);
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void get_userconfig_txpwr_lvl(txpwr_lvl_conf_t *txpwr_lvl);
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void get_userconfig_txpwr_lvl_v2(txpwr_lvl_conf_v2_t *txpwr_lvl_v2);
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void get_userconfig_txpwr_lvl_v3(txpwr_lvl_conf_v3_t *txpwr_lvl_v3);
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void get_userconfig_txpwr_ofst(txpwr_ofst_conf_t *txpwr_ofst);
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void get_userconfig_txpwr_ofst2x(txpwr_ofst2x_conf_t *txpwr_ofst2x);
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void get_userconfig_xtal_cap(xtal_cap_conf_t *xtal_cap);
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#endif /* CONFIG_LOAD_USERCONFIG */
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void rwnx_get_chip_info(uint8* info);
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uint8_t *rwnx_get_fw_ver(void);
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#endif /* _RWNX_PLATFORM_H_ */
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