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134 lines
3.1 KiB
ArmAsm
134 lines
3.1 KiB
ArmAsm
/*
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* Copyright (c) 2022-2025, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: dwj <weijie.ding@artinchip.com>
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*/
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#include <rtconfig.h>
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#define DDRC_BASE 0x18400000
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#define DDR_PHY_BASE 0x18500000
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#define GTC_CNTVL 0x09050008
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#define GTC_CNTVH 0x0905000C
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#define RTC_GPIO_CFG 0x090300EC
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#define PRCM_AP_CORE_CFG 0x08020D80
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.macro delay_200us
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li s0, GTC_CNTVL
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li s1, GTC_CNTVH
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lw s2, (s0) //start value 32bit low
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lw s3, (s1) //start value 32bit high
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1:
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lw s4, (s0) //current value 32bit low
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lw s5, (s1) //current value 32bit high
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sub s6, s4, s2 //s6 save 32bit low of sub
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sltu s7, s4, s6 //s7 save carry
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sub s8, s5, s3 //s8 save 32bit high of sub
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sub s8, s8, s7 //s8 sub carry
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bnez s8, 2f
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li s4, 800 //GTC frequency is 4000000Hz, 200us counter 800
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bltu s6, s4, 1b
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2:
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.endm
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.section .entry, "ax", %progbits
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.align 3
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.option pic
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.global aic_suspend_resume
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aic_suspend_resume:
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//step1: DDR enter self refresh
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//ddr self-refresh flow
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li t0, DDRC_BASE
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li t1, DDR_PHY_BASE
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//disable DDR port
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li t2, 0
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li t3, 0
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li t5, 5
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addi t0, t0, 0x490
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port_close_loop:
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add t0, t0, t2
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sw zero, (t0)
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addi t2, t2, 0xb0
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addi t3, t3, 1
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bltu t3, t5, port_close_loop
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//enter self refresh
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li t0, DDRC_BASE
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lw t1, 0x30(t0)
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ori t1, t1, 0x21
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sw t1, 0x30(t0)
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#ifndef FPGA_BOARD_ARTINCHIP
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//Setting AP_GPIO_PAD_HOLD
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li t0, RTC_GPIO_CFG
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li t1, 0xFF
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sw t1, (t0)
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//Setting AP_CORE_ISO
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li t0, PRCM_AP_CORE_CFG
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lw t1, (t0)
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li t2, 0x10000
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or t1, t1, t2
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sw t1, (t0)
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//Reset AP_CORE
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li t2, 0xFEFFFFFF
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and t1, t1, t2
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sw t1, (t0)
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//TODO: verified on IC
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#endif
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wfi
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#ifndef FPGA_BOARD_ARTINCHIP
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//Release AP_CORE
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li t0, PRCM_AP_CORE_CFG
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lw t1, (t0)
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li t2, 0x1000000
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or t1, t1, t2
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sw t1, (t0)
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//Clear AP_CORE_ISO
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li t2, 0xFFFEFFFF
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and t1, t1, t2
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sw t1, (t0)
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//disable AP_GPIO_PAD_HOLD
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li t0, RTC_GPIO_CFG
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li t1, 0
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sw t1, (t0)
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//TODO: verified on IC
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#endif
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//DDR exit self-refresh
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li t0, DDRC_BASE
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lw t2, 0x30(t0)
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li t3, 0xDE
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and t2, t2, t3
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sw t2, 0x30(t0) //exit self-refresh
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check_ddr_exit_sr_status:
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lw t2, 0x4(t0)
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andi t2, t2, 0x3
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li t3, 0x1
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bne t2, t3, check_ddr_exit_sr_status
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delay_200us
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li t2, 0
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li t3, 0
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li t4, 1
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li t5, 5
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addi t0, t0, 0x490
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port_open_loop:
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add t0, t0, t2
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sw t4, (t0)
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addi t2, t2, 0xb0
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addi t3, t3, 1
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bltu t3, t5, port_open_loop
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aic_suspend_resume_end:
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.data
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.align 3
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.global aic_suspend_resume_size
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aic_suspend_resume_size:
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.word aic_suspend_resume_end - aic_suspend_resume
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