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https://gitee.com/Vancouver2017/luban-lite.git
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245 lines
6.1 KiB
C
245 lines
6.1 KiB
C
/*
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* Copyright (c) 2023, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: Mingfeng.Li <mingfeng.li@artinchip.com>
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*/
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#include <rtconfig.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <aic_common.h>
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#include <string.h>
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#include <aic_core.h>
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#include <aic_hal.h>
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#include <driver.h>
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#include <xspi_psram.h>
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#include <hal_xspi.h>
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#include "aic_core.h"
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#define XSPI_DDR_MODE 1
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#define XSPI_SDR_MODE 0
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#define XSPI_MODE_XCCELA 0
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#define XSPI_MODE_HYPERBUS 1
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#define XSPI_MODE_OPI 2
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#define XSPI_MODE_SPI 3
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#define XSPI_IO_1 0x0
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#define XSPI_IO_2 0x1
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#define XSPI_IO_4 0x2
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#define XSPI_IO_8 0x3
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#define XSPI_PARALLEL_MODE 1
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#define XSPI_SINGLE_MODE 0
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#define BASE_PSRAM 0x40000000
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// usually config by menuconfig
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#ifndef AIC_XSPI_PSRAM_CLK
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#define AIC_XSPI_PSRAM_CLK 99000000
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#endif
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#ifndef AIC_XSPI_PSRAM_CS0_PINS
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#define AIC_XSPI_PSRAM_CS0_PINS 0
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#endif
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#ifndef AIC_XSPI_PSRAM_CS1_PINS
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#define AIC_XSPI_PSRAM_CS1_PINS 0
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#endif
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static struct aic_xspi aic_xspi_controller[] = {
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{
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.name = "xspi",
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.idx = 0,
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.clk_id = CLK_XSPI,
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/* XSPI IP hw Frequency division=2 */
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.clk_in_hz = AIC_XSPI_PSRAM_CLK * 2,
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},
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};
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static struct aic_xspi *aic_get_xspi_by_index(u32 idx)
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{
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struct aic_xspi *xspi;
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u32 i;
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xspi = NULL;
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for (i = 0; i < ARRAY_SIZE(aic_xspi_controller); i++) {
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if (i == idx) {
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xspi = &aic_xspi_controller[i];
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break;
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}
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}
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return xspi;
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}
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static int aic_xspi_psram_dev_reset(hal_xspi_handle *handle)
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{
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pr_info("aic_xspi_psram_dev_reset %s:%d\n\n\n", __FUNCTION__, __LINE__);
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hal_xspi_set_cmd_width(handle, XSPI_DDR_MODE, XSPI_IO_8);
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hal_xspi_set_cmd(handle, XSPI_DDR_MODE, 0xff);
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hal_xspi_set_addr_width(handle, XSPI_DDR_MODE, XSPI_IO_8, 3);
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hal_xspi_set_addr(handle, 0x0);
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hal_xspi_set_dummy(handle, XSPI_IO_8, 0x0);
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hal_xspi_set_write_cnt(handle, XSPI_DDR_MODE, XSPI_IO_8, 1);
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u8 buf = 0;
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struct hal_xspi_transfer t;
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t.rx_data = NULL;
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t.tx_data = &buf;
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t.data_len = 1;
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hal_xspi_transfer_cpu_sync(handle, &t);
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pr_info("aic_xspi_psram_dev_reset %s:%d\n\n\n", __FUNCTION__, __LINE__);
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return 0;
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}
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static int aic_xspi_psram_dev_init(hal_xspi_handle *handle)
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{
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hal_xspi_set_cmd_width(handle, XSPI_DDR_MODE, XSPI_IO_8);
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hal_xspi_set_cmd(handle, XSPI_DDR_MODE, 0xc0);
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hal_xspi_set_addr_width(handle, XSPI_DDR_MODE, XSPI_IO_8, 3);
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hal_xspi_set_addr(handle, 0x0);
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hal_xspi_set_dummy(handle, XSPI_IO_8, 0x0);
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hal_xspi_set_write_cnt(handle, XSPI_DDR_MODE, XSPI_IO_8, 2);
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u8 buf1[2] = {0x19, 0x00};
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struct hal_xspi_transfer t2;
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t2.rx_data = NULL;
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t2.tx_data = (u8 *)buf1;
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t2.data_len = 2;
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hal_xspi_transfer_cpu_sync(handle, &t2);
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hal_xspi_set_addr(handle, 0x4);
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u8 buf11[2] = {0x80, 0x00};
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struct hal_xspi_transfer t22;
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t22.rx_data = NULL;
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t22.tx_data = (u8 *)buf11;
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t22.data_len = 2;
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hal_xspi_transfer_cpu_sync(handle, &t22);
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return 0;
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}
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static int aic_xspi_psram_read_id(hal_xspi_handle *handle)
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{
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u32 data = 0;
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pr_info("aic_xspi_psram_read_id %s:%d\n", __FUNCTION__, __LINE__);
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hal_xspi_set_cmd_width(handle, XSPI_DDR_MODE, XSPI_IO_8);
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hal_xspi_set_cmd(handle, XSPI_DDR_MODE, 0x40);
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hal_xspi_set_addr_width(handle, XSPI_DDR_MODE, XSPI_IO_8, 3);
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hal_xspi_set_addr(handle, 0x02);
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hal_xspi_set_dummy(handle, XSPI_IO_8, 3);
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hal_xspi_set_read_cnt(handle, XSPI_DDR_MODE, XSPI_IO_8, 4);
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struct hal_xspi_transfer t3;
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t3.rx_data = (u8 *)&data;
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t3.tx_data = NULL;
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t3.data_len = 4;
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hal_xspi_transfer_cpu_sync(handle, &t3);
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pr_info("APS3208K_ID= 0x%x\n", data);
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return 0;
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}
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static int aic_xspi_psram_xip(hal_xspi_handle *handle, hal_xspi_proto_cfg_t proto)
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{
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hal_xspi_xip_cfg(handle, proto);
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hal_xspi_xip_enable(handle);
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return 0;
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}
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int aic_xspi_psram_init(void)
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{
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u32 ret = 0;
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struct aic_xspi *xspi;
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struct hal_xspi_config cfg;
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xspi = aic_get_xspi_by_index(0);
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if (!xspi)
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return -1;
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if (xspi->inited)
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return 0;
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memset(&cfg, 0, sizeof(cfg));
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cfg.idx = xspi->idx;
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cfg.clk_in_hz = xspi->clk_in_hz;
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cfg.clk_id = xspi->clk_id;
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cfg.cs0_port = AIC_XSPI_PSRAM_CS0_PINS;
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cfg.cs1_port = AIC_XSPI_PSRAM_CS1_PINS;
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ret = hal_xspi_init(&xspi->handle, &cfg);
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if (ret) {
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pr_err("xspi init failed.\n");
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return ret;
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}
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hal_xspi_set_cs(&xspi->handle, 0);
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aic_xspi_psram_dev_reset(&xspi->handle);
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aic_udelay(500);
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aic_xspi_psram_dev_init(&xspi->handle);
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aic_xspi_psram_read_id(&xspi->handle);
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hal_xspi_set_cs(&xspi->handle, 1);
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aic_xspi_psram_dev_reset(&xspi->handle);
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aic_udelay(500);
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aic_xspi_psram_dev_init(&xspi->handle);
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aic_xspi_psram_read_id(&xspi->handle);
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// set Boundary_Control = 2k.
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hal_xspi_set_boudary(&xspi->handle, BOUNDARY_2K);
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hal_xspi_proto_cfg_t psram_proto_cfg = {0};
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psram_proto_cfg.mode = XSPI_MODE_OPI;
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psram_proto_cfg.clk_mode = XSPI_DDR_MODE;
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psram_proto_cfg.parallel_mode = XSPI_SINGLE_MODE;
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psram_proto_cfg.wr_cmd_lines = XSPI_IO_8;
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psram_proto_cfg.wr_cmd_val = 0x80;
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psram_proto_cfg.addr_lines = XSPI_IO_8;
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psram_proto_cfg.addr_width = 3;
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//psram_proto_cfg.wr_dummy = 0;
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psram_proto_cfg.wr_dummy = 2; // >166M
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psram_proto_cfg.rd_dummy = 0x06;
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psram_proto_cfg.wr_cnt_lines = XSPI_IO_8;
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psram_proto_cfg.wr_cnt = 2;
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psram_proto_cfg.rd_cnt_lines = XSPI_IO_8;
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psram_proto_cfg.rd_cnt = 3;
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psram_proto_cfg.rd_cmd_lines = XSPI_IO_8;
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psram_proto_cfg.rd_cmd_val = 0x00;
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aic_xspi_psram_xip(&xspi->handle, psram_proto_cfg);
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void *psram_training_buf = (u32*)(BASE_PSRAM);
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int len = 1024 * 256;
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ret = hal_xspi_dll_training(&xspi->handle, 0, 2, psram_training_buf, len);
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if (ret) {
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pr_err("xspi cs0 trainning failed.\n");
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while(1);
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}
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ret = hal_xspi_dll_training(&xspi->handle, 1, 2, psram_training_buf, len);
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if (ret) {
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pr_err("xspi cs0 trainning failed.\n");
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while(1);
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}
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hal_xspi_set_parallel_mode(&xspi->handle, XSPI_PARALLEL_MODE);
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return 0;
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}
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