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v1.0.2: optimize schedule

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刘可亮
2023-12-14 18:38:43 +08:00
parent da098fba4d
commit 21048e056f
3 changed files with 48 additions and 2 deletions
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4
bsp/artinchip/sys/d21x/vectors.S
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@@ -57,7 +57,7 @@ Default_IRQHandler:
la sp, g_top_irqstack la sp, g_top_irqstack
/* ipush */ /* ipush */
addi sp, sp, -(18 * FREGBYTES) addi sp, sp, -(18 * REGBYTES)
STORE x1, 1 * REGBYTES(sp) // ra STORE x1, 1 * REGBYTES(sp) // ra
csrr x1, mepc csrr x1, mepc
STORE x1, 0 * REGBYTES(sp) // mepc STORE x1, 0 * REGBYTES(sp) // mepc
@@ -213,7 +213,7 @@ Default_IRQHandler:
LOAD x30, 16 * REGBYTES(sp) // t5 LOAD x30, 16 * REGBYTES(sp) // t5
LOAD x31, 17 * REGBYTES(sp) // t6 LOAD x31, 17 * REGBYTES(sp) // t6
addi sp, sp, (18 * FREGBYTES) addi sp, sp, (18 * REGBYTES)
/* Restore sp to normal stack */ /* Restore sp to normal stack */
csrr sp, mscratch csrr sp, mscratch

23
kernel/rt-thread/libcpu/risc-v/artinchip/c906/context_gcc.S
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@@ -63,6 +63,12 @@ rt_hw_context_switch_to:
li t1, 1 li t1, 1
sw t1, (t0) sw t1, (t0)
/* make sure wite instruction is complete */
fence
lw t1, (t0)
fence
sync.is
/* enable global interrup */ /* enable global interrup */
csrsi mstatus, 8 csrsi mstatus, 8
@@ -83,6 +89,11 @@ rt_hw_context_switch_to:
rt_hw_context_switch: rt_hw_context_switch:
.globl rt_hw_context_switch_interrupt .globl rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt: rt_hw_context_switch_interrupt:
addi sp, sp, -(3 * REGBYTES)
STORE t0, 0 * REGBYTES(sp)
STORE t1, 1 * REGBYTES(sp)
STORE t2, 2 * REGBYTES(sp)
/* check rt_thread_switch_interrupt_flag */ /* check rt_thread_switch_interrupt_flag */
la t0, rt_thread_switch_interrupt_flag la t0, rt_thread_switch_interrupt_flag
lw t1, (t0) lw t1, (t0)
@@ -99,11 +110,23 @@ rt_hw_context_switch_interrupt:
/* update to_thread */ /* update to_thread */
la t0, rt_interrupt_to_thread la t0, rt_interrupt_to_thread
STORE a1, (t0) STORE a1, (t0)
/* set software interrupt */ /* set software interrupt */
li t0, TSPEND_INTIP li t0, TSPEND_INTIP
li t1, 1 li t1, 1
sw t1, (t0) sw t1, (t0)
/* make sure wite instruction is complete */
fence
lw t1, (t0)
fence
sync.is
LOAD t0, 0 * REGBYTES(sp)
LOAD t1, 1 * REGBYTES(sp)
LOAD t2, 2 * REGBYTES(sp)
addi sp, sp, (3 * REGBYTES)
ret ret
/* /*

23
kernel/rt-thread/libcpu/risc-v/artinchip/e9xx/context_gcc.S
View File

@@ -71,6 +71,12 @@ rt_hw_context_switch_to:
or t1, t1, t2 or t1, t1, t2
sb t1, (t0) sb t1, (t0)
/* make sure wite instruction is complete */
fence
lb t1, (t0)
fence
sync.i
/* enable global interrup */ /* enable global interrup */
csrsi mstatus, 8 csrsi mstatus, 8
@@ -91,6 +97,11 @@ rt_hw_context_switch_to:
rt_hw_context_switch: rt_hw_context_switch:
.globl rt_hw_context_switch_interrupt .globl rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt: rt_hw_context_switch_interrupt:
addi sp, sp, -(3 * REGBYTES)
STORE t0, 0 * REGBYTES(sp)
STORE t1, 1 * REGBYTES(sp)
STORE t2, 2 * REGBYTES(sp)
/* check rt_thread_switch_interrupt_flag */ /* check rt_thread_switch_interrupt_flag */
la t0, rt_thread_switch_interrupt_flag la t0, rt_thread_switch_interrupt_flag
lw t1, (t0) lw t1, (t0)
@@ -107,6 +118,7 @@ rt_hw_context_switch_interrupt:
/* update to_thread */ /* update to_thread */
la t0, rt_interrupt_to_thread la t0, rt_interrupt_to_thread
STORE a1, (t0) STORE a1, (t0)
/* set software interrupt */ /* set software interrupt */
li t0, TSPEND_INTIP li t0, TSPEND_INTIP
lb t1, (t0) lb t1, (t0)
@@ -114,6 +126,17 @@ rt_hw_context_switch_interrupt:
or t1, t1, t2 or t1, t1, t2
sb t1, (t0) sb t1, (t0)
/* make sure wite instruction is complete */
fence
lb t1, (t0)
fence
sync.i
LOAD t0, 0 * REGBYTES(sp)
LOAD t1, 1 * REGBYTES(sp)
LOAD t2, 2 * REGBYTES(sp)
addi sp, sp, (3 * REGBYTES)
ret ret
/* /*